Fusion Compiler: Design Implementation
2 Setting up CTS
Learning Objectives
The purpose of this lab is for you become familiar with the
setup steps for clock tree balancing, NDRs as well as
timing/DRCs.
After CTS setup, you will run the build_clock /
route_clock clock tree synthesis stages to confirm the
results.
After completing this lab, you should be able to
• Set up clock tree balancing
• Create and apply Non-Default routing rules
• Apply clock-related timing and DRC constraints
Lab Duration:
45 minutes
Setting up CTS Lab 2-1
Lab 2
Instructions
Answers / Solutions
You are encouraged to refer to the back of the lab to verify your answers, and to
look for hints.
Task 1. Load the Design and Analyze the Clocks
Change to the work directory for the CTS lab, then load the starting design:
UNIX% cd lab2_cts
UNIX% fc_shell -gui -f [Link]
The script will open a block that is ready for the upcoming tasks.
Open the [Link] file in the Fusion Compiler script editor, as in previous
labs.
This file contains all the commands that you will be executing in this lab.
Select the commands from this file, ensure that Selected is checked, then
click the Run button, instead of typing them yourself, to save time and avoid
typing errors.
Select the menu Window→Clock Tree Analysis Window.
Expand the SDRAM_CLK entry in func mode(click on the “+” in front of it) and
you will see the two SD_DDR_CLK* clocks. Notice that the is_generated
column is set to true for these clocks, and their sources are sd_CK*.
Also, you will see “M” and “G” symbols in front of the clocks, which identifies
them as Master or Generated clocks, respectively. In summary: The
SD_DDR_CLK and SD_DDR_CLKn clocks are generated from the master
clock SDRAM_CLK. The SDRAM_CLK clock is applied to its source port
sdram_clk. The generated clocks are applied to their source ports sd_CK
and sd_CKn, respectively.
Lab 2-2 Setting up CTS
© Synopsys, Inc. Fusion Compiler: Design Implementation
Lab 2
Perform closer analysis of SDRAM_CLK in func mode by right-clicking on it,
then selecting “Clock Tree Object List”. In the “Find CTS Object”
dialog that appears, select OK.
You should see a new window as shown above.
In this new window, you will see all valid sink pins of this clock. You will not
see the output ports sd_CK and sd_CKn in this list. You’ll see why later.
If you scroll to the right, you will see many more attributes associated with the
pins/ports. To better display the information that is important to you, you can
move the position of the columns to the left/right, and you can sort the order
by the values in any column.
Close the CTS window.
To report what type of balance points exist on the clock tree endpoints
(implicit or explicit ignore or sink pins), generate a clock structure report:
v report_clock_qor -type structure
In the view window, type Ctrl-F (or click on Search…) then enter the search
string “sd_CK” and press enter. You should see the line beginning with
sd_CK [out Port], and at the end of the line you will see a balance point
exception (something other than an implicit SINK PIN).
Question 1. What balance point exception is set on sd_CK, and why?
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Do NOT close the view window yet.
Setting up CTS Lab 2-3
Fusion Compiler: Design Implementation © Synopsys, Inc.
Lab 2
Task 2. Clock Tree Balancing
Many designs have special or non-default requirements for their clock trees, in
which case executing a default clock tree synthesis is not enough.
CTS will only balance the delays (minimize skew) to sink pins, which, by default,
are clock pins of sequential cells or macros. If there are additional pins that need to
be balanced along with these clock pins, Fusion Compiler needs to be explicitly told
about them prior to CTS.
Figure 1. SDRAM interface
Figure 1 shows the SDRAM interface. The clock SDRAM_CLK is connected directly to
the select pins of muxes, which in turn will drive the output ports of the ORCA_TOP
block. The dummy mux driving sd_CK is required because of the tight timing
requirement of the DDR SDRAM interface, which produces data at its output data
ports on both the rising and the falling clock edges. This design requires that the
clock skew from SDRAM_CLK to sd_DQ_out and sd_CK be optimized. By default,
select (S0) pins are marked as implicit ignore pins. To have CTS balance the skew
you need to redefine these select pins as sink pins.
In the view window that should still be open (see the last step of the previous
Task), notice that just above and below the sd_CK line, the MUX select pins
described in Figure 1, I_SDRAM_TOP/I_SDRAM_IF/sd_mux_CK*/S0, are,
in fact, also implicit ignore pins.
Click on Dismiss Search and then Exit the view window.
Lab 2-4 Setting up CTS
© Synopsys, Inc. Fusion Compiler: Design Implementation
Lab 2
As a reminder, select and run the commands from the [Link] script using
the built-in script editor.
Apply balancing constraints for the S0 pins in all modes:
set_clock_balance_points \
-modes [all_modes] \
-balance_points [get_pins "I_SDRAM_TOP/I_SDRAM_IF/sd_mux_*/S0"]
Generate the following report to verify the user-defined balance points:
v report_clock_balance_points
Note that you will find many balance point constraints. These were created by
compile_fusion CCD, which is enabled by default.
The balance points you set will be listed below the following lines:
Clock Independent:
Balance Points:
The reason the balance points are “Clock Independent” is because you did
not specify a clock to go with the exception. If the exception is intended to be
balanced with regard to a specific clock, and there are multiple clocks
reaching this point, then a clock should be specified. This is not the case
here.
Have another look at a clock structure report, and search for sd_mux:
v report_clock_qor -type structure
In the view window, search for sd_CK.
Question 2. How are the S0 (select) pins of the MUXes labeled now?
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Question 3. How is the sd_CK port labeled now? What does this mean?
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Close the view window.
Instruct CTS to not change the SDRAM muxes: They have been chosen to
achieve the best timing and should be left as they are.
set_dont_touch \
[get_cells "I_SDRAM_TOP/I_SDRAM_IF/sd_mux_*"]
Setting up CTS Lab 2-5
Fusion Compiler: Design Implementation © Synopsys, Inc.
Lab 2
Verify your settings with the report_dont_touch command:
report_dont_touch I_SDRAM_TOP/I_SDRAM_IF/sd_mux_*
Return to Window→Clock Tree Analysis Window. Expand the
SYS_2x_CLK (click on the “+” in front of it). You should see the SYS_CLK
clock.
Question 4. What is the source of this generated clock?
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Instruct CTS to not change the register that is used as the clock divider:
set_dont_touch \
[get_cells "I_CLOCKING/sys_clk_in_reg"]
Verify with the reporting command used in a previous step.
Set a skew target of 0.05ns for all the slow (ss) corners, and 0.02ns for the
fast (ff) corners.
Generate the following report and confirm:
report_clock_tree_options
When performing CTS, it is generally desirable to use specific cells for
synthesis, instead of letting Fusion Compiler choose any cell from the library,
for example: Cells which help to reduce skew (identical rise/fall ramp times);
Cells which help to better balance between power consumption and
speed/drive-strength, size, etc.
CTS-specific cells are defined using:
set_lib_cell_purpose -include cts
First, automatically identify the gates and ICGs that are already on the clock
network, and their logical equivalents (leq’s):
derive_clock_cell_references -output cts_leq_set.tcl
Note that the above will only work if all library cells already have the cts
purpose.
Have a look at the file that was created - cts_leq_set.tcl.
As you can see, all cells that are on the clock network currently have been
identified, along with their LEQ’s. You could copy and paste the commands to
a new file, uncomment the appropriate lines, and source it later, however,
you do NOT have to do this - we have already done this for you.
Next, choose the buffers and/or inverters you want to use for the clock tree –
this is done using the following lines:
Lab 2-6 Setting up CTS
© Synopsys, Inc. Fusion Compiler: Design Implementation
Lab 2
set CTS_CELLS [get_lib_cells \
"*/NBUFF*LVT */NBUFF*RVT * \
/INVX*_LVT */INVX*_RVT * \
/CGL* */LSUP* */*DFF*"]
set_dont_touch $CTS_CELLS false
set_lib_cell_purpose -exclude cts [get_lib_cells]
set_lib_cell_purpose -include cts $CTS_CELLS
Select/run these lines from [Link].
Instead of sourcing an edited copy of the cts_leq_set.tcl file that you
created earlier, you can source our version:
source scripts/cts_include_refs.tcl
Generate a report to ensure that the correct lib-cell purpose was indeed set,
and dont_touch was removed, on the key CTS cells:
v report_lib_cells -objects [get_lib_cells] \
-columns {name:20 valid_purposes dont_touch}
In the view window, search for the string “cts”.
You could also use the workshop-provided alias _full_lib_report.
Setting up CTS Lab 2-7
Fusion Compiler: Design Implementation © Synopsys, Inc.
Lab 2
Task 3. Define CTS Non-Default Routing Rules
In this task you will specify CTS non-default routing rules, as well as clock cell
spacing rules.
Open the file scripts/[Link] in an editor.
Review the file and answer the following questions:
Question 5. Which net segment(s) of the clock tree do the two clock
routing rules apply to?
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Question 6. What are some key differences between the rules?
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Apply the clock NDRs:
source –echo scripts/[Link]
First, verify that the routing rules that were created:
v report_routing_rules -verbose
You should see the metal layer details for each of the two rules that were
created. In addition, you should see a section for the vias.
Now verify where the rules were applied:
report_clock_routing_rules
The report shows which net segments (net type) the rules apply to (sink
overrides all), and the min/max layer constraints for each clock segment.
Lab 2-8 Setting up CTS
© Synopsys, Inc. Fusion Compiler: Design Implementation
Lab 2
Task 4. Timing and DRC Constraints
Generate a port report for the master clock sources:
report_ports -verbose [get_ports *clk]
Verify that the master clock sources are input ports, and that they are all
constrained by either a Driving Cell or input Transition.
Question 7. Why is it important for clock input ports to be constrained by
set_driving_cell or set_input_transition?
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Take another look at the clock uncertainty numbers using
report_clocks -skew. Next, we will change the clock uncertainty
numbers to account for post-CTS propagated clock timing. This is
accomplished by reducing the uncertainty by the value that was intended to
model the skew. The uncertainty should still model the effects of clock jitter
or additional timing margin.
Apply the following commands:
foreach_in_collection scen [all_scenarios] {
current_scenario $scen
set_clock_uncertainty 0.1 -setup [all_clocks]
set_clock_uncertainty 0.05 -hold [all_clocks]
}
Apply a max transition constraint of 0.15ns on all clocks, in all corners of
the func mode.
Enable the removal of clock reconvergence pessimism to eliminate the
timing pessimism of OCV timing derating on shared launch/capture clock tree
branches.
Generate the following report to confirm the max transition setting:
v report_clock_settings
Note: To see the correct max transition information, you have to scroll down
past the second ##Global section, and search for the “Mode = func”
section which lists all the individual clocks. The report first lists Global
settings for all modes/corners, which were not set in our case. Instead, we
applied clock-specific settings (to all clocks) by using “-clock_path
[get_clocks]”, in the current func mode.
Setting up CTS Lab 2-9
Fusion Compiler: Design Implementation © Synopsys, Inc.
Lab 2
Task 5. Perform CTS and Analyze the Results
Build and route the clock trees. Remember to disable CCD, it’s not needed
for now:
set_app_options -name clock_opt.flow.enable_ccd \
-value false
clock_opt -to route_clock
In the GUI, turn off the visibility of power and ground nets, and zoom in to
have a closer look at the clock routes. If you hover the mouse cursor over a
net, in the query window that appears, you will be able see the NDRs routing
rule that has been applied.
Report the skew between all the sd_mux* pins, which were defined as sink
pins in an earlier Task. An easy way to do this is:
report_clock_qor \
-to I_SDRAM_TOP/I_SDRAM_IF/sd_mux_*/S0 \
-corners ss_125c
You should find that the global skew is pretty small.
Have a look at the clock tree latency graph for SDRAM_CLK:
a. In the GUI: Window → Clock Tree Analysis Window
b. Check the little box in the top right corner next to ‘Filter clock by
corner’. This allows us to analyze the latency, since latency calculation
is done on a corner-by-corner basis (without selecting a corner, the x-
axis of the latency graph displays “levels of logic” instead).
c. Right click on SDRAM_CLK under the func scenario, then select Clock
Tree Latency Graph of selected Corner.
Time permitting, perform any additional analysis which is of interest to you.
You have successfully completed the Setting up CTS lab.
Lab 2-10 Setting up CTS
© Synopsys, Inc. Fusion Compiler: Design Implementation
Answers / Solutions Lab 2
Setting up CTS Lab 2-11
Fusion Compiler: Design Implementation © Synopsys, Inc.