Fusion Compiler: Design Implementation

1 Introduction to
Floorplanning

Learning Objectives

The purpose of this lab is to familiarize you with the basic

block-level floorplanning operations in Fusion Compiler.

After completing this lab, you should be able to

• Define a rectilinear block shape
• Place voltage areas inside the block
• Perform placement to determine macro locations
• Define block pin locations
• Analyze congestion and netlist connectivity
• Run PG prototyping
• Source a script that builds a power network using
Pattern-based Power Network Synthesis

Lab Duration:
45 minutes

Introduction to Floorplanning Lab 1-1

Lab 1

Introduction

ORCA Design
The example design used in all labs is called ORCA which was specifically created
to address the needs of training. The design was created by the Synopsys
Customer Education Services department.

SAED32nm Library
The technology library used in this workshop is a 32 nm library which can be freely
distributed amongst Synopsys customers. It was created by Synopsys Inc. to serve
as a means of demonstrating the various needs of modern high-frequency, multi-
voltage, multi-scenario designs. For more information about this library please visit
[Link]

This Lab
You will be creating a basic floorplan for the ORCA_TOP design. This will include
creating the initial outline of the block, shaping and placing the voltage areas,
placing the macros, performing analysis on macro placement, and finally
implementing the power network.

Lab 1-2 Introduction to Floorplanning

© Synopsys, Inc. Fusion Compiler: Design Implementation
 Lab 1

Instructions

Task 1. Invoke Fusion Compiler and load the

ORCA_TOP Block

Change your current directory to lab1_floorplan , then invoke

Fusion Compiler:

UNIX% cd lab1_floorplan
UNIX% fc_shell -gui

Look at the Console and Script Editor tabs in the bottom-left of your GUI
window. If you see the Expand (up-arrow) icon circled below, the Console
window is collapsed. Expand it by clicking on the Expand icon (if you do not
see the up-arrow icon, the window should already be expanded):

Note: The GUI window configuration when you last exited the GUI
(collapsed or expanded console window, for example) is
saved, by default, and restored when the GUI is
re-invoked.

Select the Script Editor tab to open the script editor window:

Introduction to Floorplanning Lab 1-3

Fusion Compiler: Design Implementation © Synopsys, Inc.
Lab 1

If the Script Editor window is “unpinned”, you will see the “pin” icon shown
below. To keep the Script Editor window from auto-closing when you make a
different GUI area “active”, click on the pin icon.

Now click the Open (folder) button, then select and Open the file [Link].

This file contains the commands that you will be executing in this lab. Instead
of opening the file in a separate editor and using copy/paste to transfer
commands, you can use the built-in Script Editor to simply highlight/select
lines you want to execute, and then click on the Run (play) icon.
Try this now: Select the entire line echo "hello world", ensure that
Selected is checked, then click the Run button. Look at the results in the
shell window or by selecting the Console tab (switch back to the Script Editor
tab when done).

Open the block which has been initialized with Verilog, UPF and timing
constraints, ready to be floorplanned. Use the GUI (Open an existing
block), or select/run the following command:

open_block ORCA_TOP.dlib:ORCA_TOP/floorplan

Lab 1-4 Introduction to Floorplanning

© Synopsys, Inc. Fusion Compiler: Design Implementation
 Lab 1

Task 2. Initial Floorplanning using the Task Assistant

For this task you will use the Task Assistant. You do not need to run commands
from [Link] for the next few tasks.

Open the Tasks palette (if not already open) by right-clicking your mouse
anywhere in the tab area on the right (where the View Settings palette is),
then selecting Tasks. In the pull-down menu at the top of the Tasks palette,
select Design Planning.
Note: You could also use the full task assistant by pressing F4, or
using the menu Task→Task Assistant. Then, select the
“>” (Show task navigation tree) icon in the upper-left
corner of the Task Assistant
window, and in the pull-down
menu choose Design
Planning.

Select Floorplan Preparation →Floorplan Initialization.

This opens the Floorplan Initialization dialog.

Use the boundary Type and Orientation pull-down

fields to create the block L-shape shown here (click
on Preview under the black Display Window in the
dialog to double check your set up):

Verify that the Side size control is set to Ratio.

Enter the correct Sides ratio numbers so

that side “c” is half the size of sides “a”,
“b” and “d” (which are equal).
Hint: Use whole numbers only.

Core shape should be set to “L-shape”, Orientation should be set to “West”.

Set the 4 parameters as follows: a=2, b=2, c=1, d=2

Preview the floorplan, and once it looks correct, specify a Uniform spacing
value of 20 between the core and the die.

Click on Apply to generate the initial floorplan and then Close the Task
Assistant dialog box.

Introduction to Floorplanning Lab 1-5

Fusion Compiler: Design Implementation © Synopsys, Inc.
Lab 1

You should now see something like this in the Block Layout Window:

!m

Task 3. Block Shaping

From the Tasks palette, select Block Shaping → Block Shaping: This is
used to automatically create (shape) voltage areas.

Select Shape Blocks and click

Apply.
After shape_blocks completes,
bring the layout view to the
foreground.

Enable visibility of voltage areas by selecting Voltage Area from the View
Settings → Objects panel and expand Voltage Area to enable Guardband
visibility as well.
You should find that there are two voltage areas displayed. PD_RISC_CORE
in the top-right corner, and DEFAULT_VA for the remaining area.
You should also see that the macros in DEFAULT_VA have been placed
(although not very carefully), but not the macros in PD_RISC_CORE: There
are four macros inside that voltage area are stacked on top of one another.
This is normal. Only the top-level macros are placed at this time, macros
belonging to non-default voltage areas will be placed during the next Task 4.

Lab 1-6 Introduction to Floorplanning

© Synopsys, Inc. Fusion Compiler: Design Implementation
 Lab 1

Task 4. Macro and Standard Cell Placement

From the Tasks palette, select Cell Placement → Cell Placement.

Note: Note: There is a Cell Placement → Hard Macro
Constraints entry that can be used to apply macro
keepout margins. We are skipping this, for simplicity.

In the Cell Placement dialog, check the box next to Use floorplanning
placement.

If you want to try out free form macro placement as discussed in lecture, run
the following command to enable it:

set_app_options -name [Link] -value freeform

Run placement by clicking on Apply.

Enable pin visibility and examine the placement of the macros in the GUI.
You should see that the placer has automatically created channels between
the macros and has added soft placement blockages in the narrow channels,
to reduce congestion and improve routability. The more pins along a macro’s
edge, the larger the channel width.
You should also see that the macros have been flipped so that the sides with
common pins face each other. This is done to minimize the overall number of
channels that require routing and possibly buffering between macros.

Introduction to Floorplanning Lab 1-7

Fusion Compiler: Design Implementation © Synopsys, Inc.
Lab 1

Task 5. Place the Block Ports

You could also use the Task Assistant to place the pins of the block, but this
time just select/run the corresponding commands from [Link]:

set_block_pin_constraints -self -allowed_layers {M3 M4 M5 M6}

place_pins -self

Have a look at the layout, you should see that all the block’s ports, the logical
representations of the physical pins, have been placed.

Zoom in to individual ports to verify that the pins have, indeed, only been
placed on layers M3-M6.
Note: To be able to select the physical block “pins”, turn on
Terminal selectability (terminals are the physical pins of the
current block).

Search for the *clk ports/terminals and zoom into their location. See
[Link] for hints.
Apply the commands from [Link] to create a pin guide. This will constrain
all the specified clock pins to be placed in a certain area. Afterwards, turn on
pin guide visibility by turning on Guide→Pin Guide from the View Settings
→ Objects panel, or apply the command from the script. To see the pin
guide, zoom in to the highlighted area as shown below.

Change the width of the *clk ports (the terminal shapes) to 0.1 and the
length to 0.4, then rerun pin placement. You should find that all clock pins
are now located inside the pin guide, and that they have been resized as
specified.
This was just one example of applying pin constraints. Review the man page
to see what other adjustments are possible.

Lab 1-8 Introduction to Floorplanning

© Synopsys, Inc. Fusion Compiler: Design Implementation
 Lab 1

Task 6. Congestion Map

Now that macros and standard cells have been placed, as well as the block ports, it
is a good idea to check if there are any congestion issues.

Bring up the congestion map by selecting

the “Global Route Congestion” entry from
the GUI maps pull-down menu.

Select “Reload”, then confirm the dialog that

appears by pressing OK.
After global routing completes, you should
see that the layout has been updated to display the
heat map.
You will not see any congestion to speak of: From
the colored histogram, most “overflows” are 1, and
overflow # of GRC edges
very few overflows are greater than 2.

To make the display a little more interesting, try the following steps.
Change the Bins/From/To settings as shown in the following screenshot:
Bins has been reduced from 9, and from/to has been
changed from 0/7: Now, overflows from -2 to 2 have
their own individual bin; All overflows greater than 2
are grouped into a combined bin, and the same for
overflows less than -2.
This should drastically change what you see, by making the low overflows
brighter/hotter: You will see that there are a lot of areas with 0 overflow.
Display changes do not alter the results: The design has no serious
congestion issues. If you want to see a detailed calculation of the overflow
for an edge, move the mouse over that edge and you will see a popup with all
the details, as shown here:

Introduction to Floorplanning Lab 1-9

Fusion Compiler: Design Implementation © Synopsys, Inc.
Lab 1

Close the congestion map, either by clicking on the Draw Global Route

Congestion … icon in the top banner, or by closing the palette.

Task 7. Analyze Macro Placement using DFF

Data Flow Flylines (DFF) is a feature that allows you to analyze not just simple pin-
to-pin connections, but connections that cross through combinational gates as well
as registers. This enables a very insightful view of your overall design and makes it
easier to make informed decisions about macro placement which has a large
impact on standard cell placement.

Bring up Data Flow Lines by selecting the

appropriate entry from the connectivity pull-
down, located to the left of the maps pull-down.

Select Reload. In the dialog that appears you

can configure the tracing behavior of DFF. For
example, you can specify how many register
levels to trace through. The higher this number,
the longer the calculations will take. For our
purposes, accept the defaults and click on OK.

Once this completes, select Macros and Ports for items to

Include in the Data Flow Flylines analysis, and click on
Apply (highlighted in blue once you make changes) to
accept the changes.
You can also change the configuration of this panel and
choose “Auto apply”, so the changes take effect
immediately.

Now select one macro to see its connections to other macros and ports.
Limit the tracing by checking “Number of registers” or “Number of gates”
and changing the Min/Max numbers. Using this method, you can quickly
figure out whether objects are connected directly, or through several gate
levels, or through several register levels. You can select several macros at
the same time using the Control key. If you click on a flyline, you will get
detailed information about the connection(s).

Note that DFF will not show you any flylines if they terminate at a register.
You will only see flylines between macros or between macros and ports,
depending on the selection you have made under “Include”. In the next Task
we will show you how to perform register tracing.

Close the DFF palette.

Lab 1-10 Introduction to Floorplanning

© Synopsys, Inc. Fusion Compiler: Design Implementation
 Lab 1

Task 8. Register Tracing

Select Register Tracing from the connectivity pull-down, located right under
the Data Flow Flylines entry.

Select any macro. The registers connecting to that macro will be highlighted
immediately, skipping any logic that may be in between. Select Show flylines
to see the flylines between the macro and registers.

To see the next level of registers, increase Max levels to 2 under the Limit
Tracing heading, and under Show Levels, check Level 2. If there is a
second level of registers they will be highlighted in a different color.

Under Highlight, you have the option to also display End points: These are
the endpoints from the last level of registers displayed. You can also display
Direct end points, which are endpoints that connect directly (level 0) to the
selected source, i.e. our macro.

Close the Register Tracing palette.

We will assume for this lab that the macros are placed to our satisfaction, so
the next step is to fix their location. You can do this by selecting the macros

then clicking on , or by entering:

set_fixed_objects [get_flat_cells -filter "is_hard_macro"]

Introduction to Floorplanning Lab 1-11

Fusion Compiler: Design Implementation © Synopsys, Inc.
Lab 1

Task 9. PG Prototyping

PG prototyping can help you create a basic PG mesh very quickly. All you need to
specify are the PG net names, the layers and the percentage of the layers you want
to use for PG routing. This is most commonly used as a place-holder for the final
power mesh, in order to check congestion issues that a PG mesh may cause.

From the Tasks palette, select PG Planning → PG Prototyping

Click the Default button in the f to show the default settings. Notice that, by
default, the upper-two metal PG layers from the technology file, MRDL and
M9, are listed to be used as the vertical and horizontal PG layers,
respectively.

Specify M8 and M7 instead of the default vertical and horizontal layers,

respectively, using the pull-down menus.

Click on Apply. In a couple of seconds, you should see a basic PG mesh

inserted, which does not route over hard macros.

You can remove the PG mesh by clicking on Remove PG Routes.

If you like, play around with the layer and percentage parameters to test
different PG mesh configurations. Remove PG routes before re-applying new
parameters.

In the next task you will build the final mesh using a pre-written script.

Lab 1-12 Introduction to Floorplanning

© Synopsys, Inc. Fusion Compiler: Design Implementation
 Lab 1

Task 10. Power Network Synthesis

Planning an entire power network for a design can be a complex task, especially in
a multi-voltage environment. The purpose of this task is to just give you an idea of
what is possible in Fusion Compiler using pattern-based power network synthesis
(PPNS), and to demonstrate how few commands it takes to create a full multi-
voltage PG mesh.

Quickly review the script that inserts the entire power structure. Open the file
scripts/[Link] in an editor (or in the script editor!).
After first deleting any pre-existing PG mesh structures, you will see how the
patterns are created (create_pg_*_pattern), followed by the strategies
(set_pg_strategy). Once both are defined, the strategies are
implemented using compile_pg.

Source the script:

source -echo scripts/[Link]

Once the script has completed, review the power mesh, the macro PG
connections, and the standard cell rails in the layout view.
Note: The power mesh will have a few issues here and there,
which will have to be taken care of for final implementation.

Save and exit the tool:

save_lib
exit

You have completed the floorplanning lab!

Introduction to Floorplanning Lab 1-13

Fusion Compiler: Design Implementation © Synopsys, Inc.
Lab 1

This page was intentionally left blank

Lab 1-14 Introduction to Floorplanning

© Synopsys, Inc. Fusion Compiler: Design Implementation