Fusion Compiler Design Creation
3 Compile Flow
Learning Objectives
The purpose of this lab is to run through the 7 stages of
compile_fusion and perform quick analysis steps
inbetween, to get an overview of what happens when.
Lab Duration:
30 minutes
Compile Flow Lab 3-1
Synopsys I-101-03-LG-05
Lab 3
Instructions
Task 1. Read the RTL, Complete the Setup
In this task, you will start by running a setup script that performs the following steps,
some of which we have not yet covered in lecture:
• Read the RTL and link the design
• Apply technology setup
• Apply the UPF power intent
• Create the modes/corners/scenarios and apply the timing constraints
• Apply auto-floorplan settings
Invoke Fusion Compiler from the lab directory:
UNIX% cd lab3_compile
UNIX% fc_shell -gui
In the GUI, click on the button
In the file dialog that opens, select the file [Link], then Open.
This will perform all the steps outlined above. If you want, take a quick look at
the file, but don’t spend too much time on this since we will be covering most
of these steps in later labs.
From the Script Editor bottom tab select Open (folder), then if needed use the
Parent Directory up-arrow to Open the lab3_compile directory, then
Open [Link].
This file contains all the commands that you will be executing in this lab.
Check the Selected box, select command(s) from this file and press ,
instead of typing them yourself, to save time and avoid typos.
Lab 3-2 Compile Flow
© 2024 Synopsys, Inc. Fusion Compiler Design Creation
Lab 3
Task 2. Run compile_fusion initial_map
Run stage 1 of compile, initial_map:
_run_compile_stage_save initial_map
Note: _run_compile_stage_save is a procedure that runs an
individual compile stage, creates a log file for the executed
stage, then saves the block under that stage name. It is a
little simpler to enter compared to
compile_fusion -from <stage> -to <stage>
save_block -as <stage>
This is not a native command to Fusion Compiler. This
procedure was created specifically for this workshop.
Have a look at the log file compile_fusion.initial_map.log. You
should be able to observe that:
• MV cells are inserted (if necessary – here, none are required)
• Shift registers are identified
• Unloaded registers are removed
Report the unloaded registers (includes removed registers):
report_unloaded_registers
ICG insertion also occurs during initial_map. Verify that 5 ICGs were
inserted:
report_clock_gating
Compile Flow Lab 3-3
Fusion Compiler Design Creation © 2024 Synopsys, Inc.
Lab 3
Task 3. Run compile_fusion logic_opto
Run stage 2 of compile, logic_opto:
_run_compile_stage_save logic_opto
You should see that the floorplan has been created automatically, pins are
placed along all 4 edges, and a first coarse placement has taken place (zoom
in to examine). Timing-driven logic optimization occurs before and after
placement. Here is a screenshot of the design after stage 2:
Lab 3-4 Compile Flow
© 2024 Synopsys, Inc. Fusion Compiler Design Creation
Lab 3
Create a test protocol for specified clock signals and control signals.
create_test_protocol
Here, the test protocol is created for two clocks namely pclk and sys_clk
and the two asynchronous control ports namely pci_rst_n and
sys_reset. For the user specifications, please refer pci_dft.tcl which is
present in script directory.
Checks the current design against test design rules.
dft_drc -v
You should get DRC summary report without any violations.
Enable the use of insert_dft in the breakpoint flow, after the
compile_fusion -to logic_opto is performed.
set_app_option -name dft.insertion_post_logic_opto \
-value true
Insert the DFT structures in the current design and save it.
insert_dft
save_block
Compile Flow Lab 3-5
Fusion Compiler Design Creation © 2024 Synopsys, Inc.
Lab 3
Task 4. Run compile_fusion initial_place
Run stage 3 of compile, initial_place:
_run_compile_stage_save initial_place
The placement performed here is buffering-aware timing-driven placement
(confirm by searching for the second “Placement Options” table in the log file
compile_fusion.initial_place.log).
Note that the placement is still coarse, the standard cells are not legalized.
Find high-fanout nets:
all_high_transitive_fanout -nets -threshold 100
You should see the reset net pci_rst_n. This will be buffered during the
next stage. The other net is the output net of an integrated clock-gating cell
(ICG) which will be buffered during clock tree synthesis (CTS).
Report design statistics:
report_design
From the Count column note down the number of:
Standard cells: ____________
Buffer/inverter: ____________
Lab 3-6 Compile Flow
© 2024 Synopsys, Inc. Fusion Compiler Design Creation
Lab 3
Task 5. Run compile_fusion initial_drc
Run stage 4 of compile, initial_drc:
_run_compile_stage_save initial_drc
Run report_design, and note down the number of:
Standard cells: ____________
Buffer/inverter: ____________
Notice that the standard cell count increase is primarily due to DRC buffering.
Confirm that the reset net pci_rst_n has been buffered:
all_high_transitive_fanout -nets -threshold 100
all_high_transitive_fanout -nets -threshold 40
The *clk nets are clock nets, which will be buffered later during CTS.
Find out how many scan chains there are:
get_scan_chain_count
You should get an answer “5”.
Have a look at a global route congestion map of the design by first selecting:
Compile Flow Lab 3-7
Fusion Compiler Design Creation © 2024 Synopsys, Inc.
Lab 3
In the new panel that appears, select Reload then OK to run global routing
and display the congestion map:
You should see that there are no bright-green, yellow or red “hotspots”, which
indicates that there is hardly any congestion (discussed in a later Unit).
Close the congestion map by clicking on the “X” on the Map Mode panel tab
on the right of the GUI.
Lab 3-8 Compile Flow
© 2024 Synopsys, Inc. Fusion Compiler Design Creation
Lab 3
Task 6. Run compile_fusion initial_opto
Run stage 5 of compile, initial_opto:
_run_compile_stage_save initial_opto
This stage performs many optimization steps, CCD, scan insertion, etc.
Zoom into the layout and you will see that placement seems to be fully
legalized – standard cells are placed inside the placement rows and are not
overlapping. Run the following command to check whether all cells are
indeed placed legally:
check_legality
You will find that this is not the case: Several cells are overlapping. Some
remaining illegal placement is expected at this stage of the design. Final legal
placement will be accomplished during the last compile stage.
Verify that the design is already close to meeting timing. Even though this is a
simple testcase, a lot of timing optimization has occurred during this stage:
rt
At any time, even after closing and reopening the design, you can find out
what compile stages have been run. Execute the following command:
report_optimization_history
This shows the stages that were run, the time of execution as well as the
runtime of each stage.
Compile Flow Lab 3-9
Fusion Compiler Design Creation © 2024 Synopsys, Inc.
Lab 3
Task 7. Run compile_fusion final_place
Run stage 6 of compile, final_place:
_run_compile_stage_save final_place
Check placement legality again:
check_legality
This time cell placement is fully legal. This is not the last stage though, more
optimizations and incremental placement will occur during the 7th compile
stage, after which final legalization takes place.
Review the log file compile_fusion.final_place.log.
Run a timing summary:
report_qor -summary
You should see that there are a few timing as well as max tran/cap violations
due to the finalized placement, which the next stage should improve.
Report the power consumption of the design:
report_power
Note down the Total Internal and the Total Leakage Power:
Total Internal Power: ___________
Total Leakage Power: ___________
Lab 3-10 Compile Flow
© 2024 Synopsys, Inc. Fusion Compiler Design Creation
Lab 3
Task 8. Run compile_fusion final_opto
Run stage 7 of compile, final_opto:
_run_compile_stage_save final_opto
You should see a significant improvement in leakage power:
report_power
Total Internal Power: ___________
Total Leakage Power: ___________
Confirm that there are no (or very few and very small) timing violations left:
report_qor -summary
Exit out of Fusion Compiler by entering
exit
then selecting the following in the GUI: Discard All → Close Block → Exit
You have completed the compile flow lab!
Compile Flow Lab 3-11
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Lab 3
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Lab 3-12 Compile Flow
© 2024 Synopsys, Inc. Fusion Compiler Design Creation