MICROPROCESSORS
Core Fundamentals (8085 / 8086) — Section A Study Notes
Prepared for APTRANSCO AEE (Telecom) Exam Prep
1. Basic Concepts
What Is a Microprocessor
A microprocessor is a single-chip CPU that fetches, decodes, and executes instructions. It performs arithmetic/logic
operations and controls data flow between memory, I/O, and its internal registers, but by itself has no memory or I/O
— those are added externally to form a microcomputer.
Basic Building Blocks
● ALU (Arithmetic Logic Unit): performs arithmetic and logical operations.
● Register array: temporary high-speed storage inside the CPU (accumulator, general-purpose registers,
program counter, stack pointer, etc.).
● Control unit: generates timing and control signals to coordinate fetch-decode-execute.
Buses
● Address bus: unidirectional, carries the memory/IO address; width determines addressable memory size (n-
bit bus → 2ⁿ locations).
● Data bus: bidirectional, carries actual data/instructions between CPU, memory, and I/O.
● Control bus: carries control signals (RD, WR, ALE, etc.) that direct and time the operations.
Instruction Cycle
Instruction cycle = Fetch cycle + Execute cycle (may include additional
wait/interrupt states)
Fetch: opcode is read from memory (addressed by the Program Counter) into the Instruction Register; PC is then
incremented. Decode: control unit interprets the opcode. Execute: the operation is carried out, which may involve
reading/writing operands from memory or registers.
2. 8085 Microprocessor Architecture
An 8-bit microprocessor with a 16-bit address bus (64KB addressable memory) and an 8-bit data bus, running on a
single +5V supply.
Register Set
● Accumulator (A): 8-bit, the primary register for arithmetic/logic operations — one operand always comes
from here, and the result is usually stored back here.
● General-purpose registers: B, C, D, E, H, L (8-bit each) — can be used individually or paired as BC, DE,
HL for 16-bit operations.
● HL pair: special role as an indirect memory pointer (used as a 'memory register' M, referring to the memory
location addressed by HL).
● Program Counter (PC): 16-bit, holds the address of the next instruction to be fetched.
● Stack Pointer (SP): 16-bit, points to the top of the stack in read/write memory.
● Flag register: 8-bit, holds condition flags — S (Sign), Z (Zero), AC (Auxiliary Carry), P (Parity), CY
(Carry).
Flag Register Bit Positions (D7...D0)
S Z X AC X P X CY — bits marked X are unused (don't-care).
When Each Flag Is Set
S (Sign): set if the result's MSB (D7) is 1, i.e., result is negative in signed interpretation.
Z (Zero): set if the result is exactly zero.
AC (Auxiliary Carry): set if there is a carry out of bit 3 (used internally for BCD operations, e.g., DAA).
P (Parity): set if the result has an even number of 1 bits.
CY (Carry): set if there is a carry out of (or borrow into) the MSB (D7) of the result.
Address Latch Enable (ALE)
Since the 8085 multiplexes the lower 8 bits of the address bus with the data bus (AD0–AD7), ALE is used to latch
the lower address byte externally at the start of each machine cycle, before the bus switches to carrying data.
3. Addressing Modes (8085)
Mode Example / Description
Immediate MVI A, 05H — operand is given directly in the instruction
Register MOV A, B — operand is in a CPU register
Direct LDA 2000H — operand's memory address is given directly in the instruction
Indirect (Register indirect) MOV A, M — operand's address is held in a register pair (HL)
Implied (Implicit) CMA, RAL — operand is implied by the opcode itself (usually the
accumulator)
4. Instruction Set Classification
● Data transfer: MOV, MVI, LDA, STA, LXI, LDAX, STAX, XCHG — move data without affecting flags
(except a few exceptions like XCHG, which never affects flags anyway).
● Arithmetic: ADD, ADC, SUB, SBB, INR, DCR, DAA, INX, DCX — affect flags (except INX/DCX,
which affect no flags).
● Logical: ANA, ORA, XRA, CMP, CMA, RLC, RRC, RAL, RAR — affect flags (CMA affects no flags;
it's a special case worth remembering).
● Branching: JMP, conditional jumps (JZ, JNZ, JC, JNC, etc.), CALL, RET, RST — control program flow,
generally don't affect flags.
● Machine control: HLT, NOP, DI, EI, RIM, SIM — control processor operation directly.
Commonly Confused Instruction Pairs
INR/DCR affect flags (except carry); INX/DCX affect NO flags at all — a classic exam trap.
MOV vs MVI: MOV copies between registers/memory; MVI loads an immediate (literal) value.
CALL/RET automatically use the stack (push/pop PC); JMP does not touch the stack.
5. Interrupts (8085)
A mechanism that lets external hardware (or software) divert the CPU from its normal instruction sequence to
service an urgent event, then resume where it left off.
Hardware Interrupts of the 8085
Interrupt Vector Address / Notes
TRAP 0024H — highest priority, non-maskable, edge AND level triggered
RST 7.5 003CH — maskable, edge triggered (rising edge)
RST 6.5 0034H — maskable, level triggered
RST 5.5 002CH — maskable, level triggered, lowest priority among RST lines
INTR lowest overall priority, maskable, vector address supplied externally by interfacing
hardware
Priority Order (Highest to Lowest)
TRAP > RST 7.5 > RST 6.5 > RST 5.5 > INTR
TRAP is the only non-maskable interrupt — it cannot be disabled and is used for critical events like power
failure.
Interrupt Enable/Disable
● EI (Enable Interrupt) / DI (Disable Interrupt): instructions that set/reset the interrupt enable flip-flop for
maskable interrupts.
● SIM (Set Interrupt Mask) / RIM (Read Interrupt Mask): used to individually mask/unmask RST 7.5, 6.5,
5.5 and to read pending interrupt status.
On RESET, and immediately after any interrupt is serviced, interrupts are automatically disabled — the service
routine must re-enable them (EI) if further interrupts should be accepted.
6. Memory and I/O Interfacing
Memory Mapping
Number of memory locations = 2^(address bus width)
For the 8085's 16-bit address bus: 2^16 = 65,536 locations = 64 KB of addressable memory space.
Memory-Mapped I/O vs I/O-Mapped I/O
Aspect Memory-Mapped I/O vs I/O-Mapped (Standard) I/O
Address space Shares the same address space as memory vs Separate 8-bit I/O address space (256
ports)
Instructions used Regular memory-reference instructions (MOV, LDA, etc.) vs Dedicated IN/OUT
instructions only
Address lines used Full 16-bit address vs Only 8-bit port address (duplicated on both halves of the
bus)
Memory space cost Reduces available memory space vs Does not reduce memory space
Machine Cycles and T-States
● Machine cycle: the time to complete one operation of accessing memory or I/O (e.g., opcode fetch,
memory read, memory write, I/O read, I/O write).
● T-state (clock cycle): the smallest unit of time, one period of the clock signal.
● Opcode fetch is the longest basic machine cycle, typically 4-6 T-states; memory read/write is typically 3 T-
states.
A full instruction cycle = one or more machine cycles, and each machine cycle = a specific number of T-states,
depending on the instruction and addressing mode involved.
7. 8086 Microprocessor — Key Differences from 8085
A 16-bit microprocessor with a 20-bit address bus, giving it a much larger addressable memory space than the 8-bit
8085.
Addressable memory: 2^20 = 1,048,576 locations = 1 MB
Internal Architecture — Two Functional Units
● Bus Interface Unit (BIU): handles all bus operations — fetching instructions, reading/writing memory and
I/O, and address generation. Contains the instruction queue (prefetch buffer, 6 bytes).
● Execution Unit (EU): decodes and executes instructions, contains the ALU and general-purpose registers;
has no direct connection to the system bus.
Because BIU fetches instructions into the queue WHILE the EU executes previous ones, the 8086 achieves basic
pipelining — the two units work in parallel, which significantly speeds up execution compared to the purely
sequential fetch-execute of the 8085.
Segmented Memory Addressing
Physical Address = (Segment Register × 10H) + Offset
The 8086 divides its 1MB memory into segments (Code, Data, Stack, Extra), each up to 64KB, addressed via four
segment registers (CS, DS, SS, ES) combined with a 16-bit offset — this is how a 16-bit-register machine addresses
a 20-bit (1MB) space.
Minimum vs Maximum Mode
● Minimum mode: single-processor system; 8086 itself generates all control signals.
● Maximum mode: multiprocessor system; an external Bus Controller (8288) generates control signals,
freeing the 8086 to work alongside coprocessors like the 8087 (math coprocessor).
8. DMA and Support Devices
Direct Memory Access (DMA)
Allows peripherals to transfer data directly to/from memory without routing through the CPU, greatly speeding up
bulk data transfers (disk I/O, etc.).
● HOLD/HLDA handshake (8085): a DMA controller asserts HOLD; CPU finishes its current machine
cycle, releases (tri-states) its buses, and acknowledges with HLDA; DMA controller then takes over the
bus.
● 8257 / 8237: common programmable DMA controller ICs used with 8085/8086 systems.
Common Programmable Support ICs (8085/8086 family)
IC Function
8255 Programmable Peripheral Interface (PPI) — 3 ports (A, B, C) for parallel I/O
8253 / 8254 Programmable Interval Timer/Counter — 3 independent 16-bit counters
8259 Programmable Interrupt Controller — manages up to 8 (cascadable to 64) interrupt lines
with priority
8237 Programmable DMA Controller — 4 independent DMA channels
8251 USART — Universal Synchronous/Asynchronous Receiver-Transmitter for serial
communication
8255 Modes of Operation
● Mode 0: simple I/O, no handshaking — ports simply latch input/output data.
● Mode 1: I/O with handshaking — uses some Port C lines for handshake signals (STB, IBF, OBF, ACK).
● Mode 2: bidirectional data transfer — only available on Port A, uses Port C lines for handshaking in both
directions.
9. Consolidated Reference Sheet
Concept Key Fact
8085 data/address bus 8-bit data, 16-bit address → 64KB memory
8086 data/address bus 16-bit data, 20-bit address → 1MB memory
8086 physical address (Segment × 10H) + Offset
Flags in 8085 S, Z, AC, P, CY (5 flags used, 3 bits unused)
Interrupt priority (8085) TRAP > RST7.5 > RST6.5 > RST5.5 > INTR
Only non-maskable interrupt TRAP
ALE purpose Latches lower-order address byte (demultiplexes AD0–AD7)
INX/DCX effect on flags None (unique among arithmetic instructions)
8255 Programmable Peripheral Interface, 3 ports
8259 Programmable Interrupt Controller
8253/8254 Programmable Interval Timer
HOLD/HLDA DMA bus request/acknowledge handshake
10. Common Exam Traps and Clarifications
● 8085 is a von Neumann architecture (single shared memory for code and data), while many DSP/advanced
processors use Harvard architecture (separate code/data memory) — don't mix these up when a question
asks about architecture type.
● The multiplexed AD0–AD7 bus in the 8085 exists specifically to reduce pin count on the IC package —
this is why ALE and external latching are needed.
● PUSH/POP always operate on register PAIRS (16-bit) and always affect the Stack Pointer by 2 (decrement
on PUSH, increment on POP) — never a single 8-bit register directly.
● CALL pushes the return address (PC) onto the stack automatically before jumping; RET pops it back into
PC — this is different from PUSH/POP of general registers, which the programmer controls explicitly.
● In 8086, even though CS:IP together can address more than 64KB combinations, a single segment is still
limited to 64KB — overlapping segments are how the full 1MB space is used flexibly.
● Wait states are inserted (via READY pin) when interfacing slower memory/peripherals that can't keep up
with the CPU's normal timing — this stretches the machine cycle without changing the instruction's logical
operation.
8085 vs 8086 — Quick-Fire Comparison
Bits: 8085 is 8-bit; 8086 is 16-bit.
Address bus: 8085 = 16-bit (64KB); 8086 = 20-bit (1MB).
Pipelining: 8085 has none (strictly sequential); 8086 has a 2-stage pipeline via BIU/EU overlap.
Clock: 8085 has an on-chip clock generator; 8086 needs an external clock generator (8284).
Instruction queue: absent in 8085; present in 8086 (6-byte prefetch queue).
11. Self-Test — Answer Before Checking Notes
Timed check: give yourself 20 minutes. Flag anything you get wrong and retest it in a few days rather than moving
on.
Conceptual
● Why does the 8085 need ALE, and what problem does it solve?
● List the 8085 hardware interrupts in priority order and state which one is non-maskable.
● Explain why INX/DCX don't affect flags while INR/DCR do.
● What is the purpose of the instruction queue in the 8086, and how does it improve performance over the
8085?
● Explain how 8086 segmented addressing allows a 16-bit register machine to address 1MB of memory.
● Differentiate memory-mapped I/O from I/O-mapped I/O, including which instructions are used for each.
Numerical / Applied (set these up yourself)
● If CS = 3000H and IP = 0250H, compute the physical address the 8086 will access.
● An 8085 system uses a 16-bit address bus. How many distinct memory locations can it address?
● List, in order, the sequence of bus states during a HOLD/HLDA DMA transaction.
● A programmer writes MVI A, 25H followed by ADI 3AH. What will the flag register show after the ADI
executes (consider at least the Carry and Zero flags)?
Next Steps
Once solid here, move to writing and tracing small 8085 assembly programs (sorting, searching, BCD arithmetic)
since program-tracing questions are a common exam format that tests this material practically rather than just
recalling facts.