0% found this document useful (0 votes)
1 views2 pages

Tutorial 5 Compression 2025 2

The document is a tutorial for the course EC3242: VLSI Testing and Testability at Manipal University Jaipur, focusing on compression techniques. It includes six questions related to Linear Feedback Shift Registers (LFSRs), fault detection methods, and signature analysis. Each question requires analysis of specific circuits and input sequences to determine states, fault detection, and signatures.

Uploaded by

875kps8w7n
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
1 views2 pages

Tutorial 5 Compression 2025 2

The document is a tutorial for the course EC3242: VLSI Testing and Testability at Manipal University Jaipur, focusing on compression techniques. It includes six questions related to Linear Feedback Shift Registers (LFSRs), fault detection methods, and signature analysis. Each question requires analysis of specific circuits and input sequences to determine states, fault detection, and signatures.

Uploaded by

875kps8w7n
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Manipal University Jaipur

Department of Electronics and Communication Engineering


EC3242: VLSI Testing and Testability (Session 2024-2025)

Tutorial#5
Topic- Compression
Dated:

Question 1: For the LFSR shown in Fig. 1(a) (F(x) = 1+x2+x3) and Fig. 1(b) (F(x) = 1 +x2 +x7 +x8),
determine the states when seed is 100 and 01000000 respectively.

Fig. 1(a)

Fig.1(b)

Question 2: Determine if the s-a-1 fault at line a is detected using (i) ones count (ii) transition count
(iii) Parity compaction method for the circuit shown in Fig. 2 when the five test patterns are as given.

Fig. 2
Question 3: Find the signature for the three inputs to MISR shown in Fig. 3 for seed 000.

Fig. 3

Question 4: For LFSR shown in Fig. 4, determine the signature generated for the given 8-bit input
sequence.

Fig. 4

Question 5: For each of LFSR implementation in Fig. 5, find the sequence of test patterns generated
for the seed 0001. Determine period for each LFSR.

Fig. 5

Question 6: Design a single-input signature analyzer for P*(x) = 1 + x2 + x5 + x6. Determine the
signature if the input sequence to this signature analyzer is 11011011. Verify your answer by modulo-
2 polynomial multiplication/division method.

You might also like