Scribd
Upload
2 views2 pages

Study Guide - 2025

The study guide for EC 3242 VLSI Testing and Testability covers essential topics including physical fault modeling, fault simulation techniques, and automatic test pattern generation for combinational circuits. It emphasizes the importance of controllability and observability, scan design for board-level testing, and memory testing methodologies. Additionally, it introduces compression techniques and Built-In Self-Test (BIST) concepts, detailing their architectures and test pattern generation methods.

Uploaded by

875kps8w7n
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
2 views2 pages

Study Guide - 2025

The study guide for EC 3242 VLSI Testing and Testability covers essential topics including physical fault modeling, fault simulation techniques, and automatic test pattern generation for combinational circuits. It emphasizes the importance of controllability and observability, scan design for board-level testing, and memory testing methodologies. Additionally, it introduces compression techniques and Built-In Self-Test (BIST) concepts, detailing their architectures and test pattern generation methods.

Uploaded by

875kps8w7n
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

EC 3242 VLSI TESTING AND TESTABILITY | STUDY GUIDE | ETE (May 2025)

STUDY GUIDE

PHYSICAL FAULTS AND THEIR MODELING: Stuck at Faults; Fault Collapsing – Equivalence,
Dominance:
Study basic definitions, stuck at fault model, bridging fault, IDDQ fault and delay fault; fault collapsing
techniques and apply them to different circuits to calculate collapsed fault set, test vectors to detect
SSFs, etc. Practice the numerical problems done in the class and Tutorial.

FAULT SIMULATION: Deductive, Parallel and Concurrent Fault Simulation:


You should know in detail each of these fault simulation techniques and how to apply these
methodologies to various digital circuits for deducing the faults detected by the given test patterns.
Practice the numerical problems done in the class and Tutorial.

ATPG FOR COMBINATIONAL CIRCUITS: Path sensitization method, D-Algorithm, Boolean difference,
PODEM algorithm
You should learn to apply these algorithms for automatic test pattern generation for a given fault in a
combinational circuit and hence find fault coverage and coverage efficiency. Practice the numerical
problems done in the class and Tutorial.

CONTROLLABILITY AND OBSERVABILITY


You should be able to present the definition and purpose of these quantities and also should be able
to calculate observabilities and controllabilities of combinational and sequential circuits. Learn
definitions.

SCAN DESIGN, BOUNDARY SCAN FOR BOARD LEVEL TESTING


You should be able to understand the need of scan design, various options with their limitations. You
should be able to apply testing method for Scan Circuits; and determine the test pattern (for each
time frame) for detecting specified fault. The IEEE1149.1 Wrapper architecture should be known with
details of SCAN cell and its working with various test modes.

MEMORY TESTING: PERMANENT, INTERMITTENT AND PATTERN SENSITIVE FAULTS, MARCHING


TESTS
You should be able to explain various memory cell and address faults and draw their transition diagram
wherever applicable with definition and explanation. Application of March Test to memory testing
should be known.

COMPRESSION TECHNIQUES: GENERAL ASPECTS OF COMPRESSION TECHNIQUES; ONES-COUNT,


TRANSITION COUNT AND PARITY CHECK COMPRESSION; SYNDROME TESTING; SIGNATURE
ANALYSIS
You should be able to state the need of compaction and derive the signature for response compaction
and hence determine if the fault is detectable or not. You should be able to analyze LFSR for its next
state for random number generator as well as signature analyzer. You should be able to analyze MISR
for signature analyzer.

BUILT-IN-SELF-TEST (BIST) CONCEPT: TEST PATTERN GENERATION FOR BIST; SPECIFIC BIST
ARCHITECTURE; INTRODUCTION TO BUILT-IN-SELF-REPAIR (BISR) APPROACHES
You should be able to explain need, advantages, costs and architecture of BIST architecture as well as
features of different test patterns generation methods for BIST.

You might also like