Module 2 — Answer Key

MOS and BiCMOS Circuit Design Processes

Source key: = directly from your uploaded Module-2 notes | ✍ =

not in your notes / only partially covered, so I’ve written a standard
textbook-style answer, adapted from the closest matching example in
your notes wherever possible

Q1. Draw the stick diagram for the following CMOS

Logic: (a) 2-input NAND Gate (b) 3-input NOR Gate ✍
(adapted from your notes)

Your notes give the nMOS versions of a 2-input NAND and 2-input
NOR (with circuit + stick diagrams), plus the full color/stick encoding
table for layers — but not the CMOS (with PMOS pull-up network)
stick diagrams, and not a 3-input NOR. Using the same drawing
conventions as your notes (green = n-diffusion, red = polysilicon, blue
= metal, VDD/VSS as horizontal rails), here’s how to extend them to
CMOS:

(a) CMOS 2-input NAND (Y = (AB)’): - Pull-down network

(nMOS): two nMOS transistors in series between the output node
and VSS (ground) rail, gates driven by A and B (poly stripes crossing
n-diffusion, exactly like the nMOS NAND pull-down in your notes). -
Pull-up network (pMOS): two pMOS transistors in parallel
between VDD and the output node, gates also driven by A and B (poly
stripes crossing p-diffusion, drawn just above the n-diffusion row,
separated by the p-well/n-well demarcation line as shown in your
CMOS encoding table). - Output taken from the shared node where
the series nMOS pair meets the parallel pMOS pair. - Stick diagram
layout: VDD rail (top) → pMOS pair (parallel, side-by-side polysilicon
gates A and B) → output tap → nMOS pair (series, stacked polysilicon
gates A and B) → VSS rail (bottom). This mirrors the structure of your
nMOS NAND stick diagram, but duplicated in p-diffusion above the
demarcation line for the pull-up.

(b) CMOS 3-input NOR (Y = (A+B+C)’): - Pull-down network

(nMOS): three nMOS transistors in parallel between output and
VSS, gates A, B, C. - Pull-up network (pMOS): three pMOS
transistors in series between VDD and output, gates A, B, C. - Stick
diagram: extends your nMOS NOR stick diagram (which shows a 2-
input parallel nMOS pull-down) by adding a third parallel poly gate
stripe (C) for the pull-down, and mirrors this as three series pMOS
gates above the demarcation line for the pull-up network.

(General CMOS stick-diagram rule illustrated by both: whatever

topology (series/parallel) the pull-down network uses, the pull-up
network uses the dual — parallel becomes series and vice versa —
since AND-like combinations pull down in series but must pull up via
any single parallel path, and OR-like combinations pull down via any
parallel path but must pull up only when all series paths conduct.)

Q2. With figures, explain the CMOS Lambda-based

design rules

(Directly from your notes)

Design rules are the communication link between the circuit

designer (who wants tighter, smaller layouts for performance/area)
and the fabrication/process engineer (who wants a controllable,
reproducible process). Lambda (λ)-based rules express every rule as a
multiple of λ, tied to the minimum feature size of the process — this
lets a design scale to a limited extent across process generations
without redrawing.

Design rules for wires (nMOS and CMOS): - Minimum width of n-

diffusion, p-diffusion, and polysilicon = 2λ - Minimum separation
between n-diffusion and p-diffusion (Thinox regions) = 3λ - Minimum
separation between polysilicon lines = 2λ - Minimum separation of
same-type diffusion regions = 1λ (where specified) - Minimum width
of Metal 1 = 3λ, minimum separation = 3λ - Minimum width of Metal
2 = 4λ, minimum separation = 4λ (Metal 2 used for global VDD/VSS
routing in a double-metal process, kept separate from Metal 1 signal
routing to avoid unwanted capacitance)

Transistor design rules (nMOS, pMOS, CMOS): - Minimum-size

nMOS enhancement transistor = 2λ × 2λ - Minimum-size pMOS
enhancement transistor = 2λ × 2λ - Minimum-size nMOS
depletion transistor = 2λ (channel), with a 6λ × 6λ implant region
- Extensions and separations: - Separation from a contact cut to a
transistor gate = 2λ minimum - Implant (for depletion-mode
transistor) must extend 2λ minimum beyond the channel in all
directions (and beyond polysilicon, if a buried contact is used) -
Separation from implant of one transistor to another transistor = 2λ
minimum - Polysilicon must extend a minimum of 2λ beyond
diffusion boundaries (width constant) - Diffusion must not decrease
in width to less than 2λ from polysilicon - Thinox mask = union of
n-diffusion, p-diffusion, and channel regions

Contact cut / via rules: - Metal 1 to polysilicon or diffusion:

minimum 3λ overall; contact cut is 2λ × 2λ, centered on a 4λ × 4λ
overlap area of the layers being joined; multiple cuts require 2λ
minimum separation. - Via (Metal 2 → Metal 1 → other layers):
2λ minimum separation between via and cut (if other spacings
allow); via itself is 2λ × 2λ, centered in a 4λ × 4λ overlap area with
Metal 1; a via + cut together are used to connect Metal 2 down to
diffusion.

General observations from your notes: - If wire widths are made

too small, discontinuities can occur → acts as an open circuit. - If
wires in the same layer are placed too close together, they may
unintentionally merge → causes a short circuit.

Color/monochrome encoding used to draw these layouts (from

your notes’ table): Green = n-diffusion, Red = polysilicon, Blue =
Metal 1, Black = contact cut, Gray = overglass, Yellow = implant/p⁺
mask (nMOS/CMOS specific), Dark blue/purple = Metal 2, Brown =
buried contact (nMOS) / p-well demarcation line (CMOS).

Q3. Draw the stick diagram for the CMOS Logic: Y =

(A + B + C).D ✍ (adapted from your notes’ AOI
method)

Your notes work through the closely related example Y = (AB + C)′
with full circuit + stick diagram (an AND-OR-INVERT structure). The
same systematic method extends directly to Y = (A+B+C).D:

Function structure: Y = (A+B+C)·D → this is an AOI-style (here,

OI/AOI combination) gate: an OR of A, B, C, ANDed with D, output not
inverted… but since static CMOS gates are naturally inverting, the
direct CMOS realization gives Y’ = ((A+B+C).D)’ at the shared
output node; if true Y is required, an inverter stage is added.

Pull-down network (nMOS), realizing (A+B+C).D: - A, B, C nMOS

transistors in parallel with each other (implementing the OR term),
and this parallel group placed in series with a single nMOS transistor
gated by D — exactly mirroring how your notes build the pull-down for
(AB+C)′ by combining a parallel branch with a series branch, just with
the roles of series/parallel swapped to match this new expression.

Pull-up network (pMOS), the dual: - A, B, C pMOS transistors in

series with each other, and this series group placed in parallel with a
single pMOS transistor gated by D.

Stick diagram layout (following your notes’ drawing

convention): - VDD rail at top, VSS rail at bottom. - Poly gate stripes
for A, B, C run as parallel horizontal crossings over a shared n-
diffusion column (pull-down), continuing down to a series-connected D
transistor before reaching VSS. - Mirror this above the demarcation
line in p-diffusion: A, B, C in series (stacked), in parallel with D, up to
VDD. - Output Y’ is tapped at the node between the pull-up and pull-
down networks, same tap-off style shown in your (AB+C)′ stick
diagram.

(If the true, non-inverted Y is required for the final circuit, cascade a
standard CMOS inverter stage after this AOI gate, exactly as shown
for the standalone inverter stick diagram in your notes.)

Q4. Write the schematic and stick diagram for

Boolean expression y = a + bc using CMOS logic ✍
(adapted from your notes’ AOI method)

This is the direct dual/complement companion of the (AB+C)′

example in your notes — same construction method, different
expression.

Function: y = a + bc → CMOS realizes this inverting, giving y′ = (a +

bc)′ at the gate’s natural output (add an inverter afterward if non-
inverted y is needed).

Pull-down network (nMOS) — implements (a + bc): - Transistor A in

parallel with the series combination of transistors B and C. - (i.e., A
parallel with (B series C), between output node and VSS)

Pull-up network (pMOS) — the dual: - Transistor A in series with

the parallel combination of transistors B and C. - (i.e., A series with
(B parallel C), between VDD and output node)

Schematic: - VDD → pMOS(A) → node X → [pMOS(B) ‖ pMOS(C)] →

output node - Output node → [nMOS(B) series nMOS(C)] and
separately nMOS(A) → both paths → VSS, with A’s nMOS in parallel to
the B-C series pair

Stick diagram (following your notes’ style for AOI gates): - Poly
gate stripe for A crosses both an n-diffusion column (pull-down) and a
p-diffusion column (pull-up), same as any single transistor in your
notes’ figures. - B and C poly stripes cross the n-diffusion column in
series (stacked, one diffusion break shared) for the pull-down, and
cross separate parallel p-diffusion branches for the pull-up —
mirroring exactly how your notes handle the AB term in (AB+C)′, just
swapped between pull-up/pull-down since the pull-up must always be
the dual topology of the pull-down. - Output tapped at the diffusion
node common to both networks, exactly as shown in your (AB+C)′
example.

Q5. Estimate the rise time and fall time of a CMOS

Inverter with equations and model. Summarize the
result

(Directly from your notes)

The inverter either charges or discharges the load capacitance CL.

Rise time estimation (0 → VDD, load capacitance charging through

the pMOS device, assumed in saturation):

Idsp = βp(Vgs − |Vtp|)² / 2 …(1)

Vout = Idsp × t / CL …(2)

Vgsp = Vg − Vs = Vin − VDD ⟹ since Vin = 0, Vgsp = −VDD, and

Vtp = −0.2 VDD …(3)

Substituting (2) and (3) into (1):

Tr = 3.125·CL / (βp·VDD)

Fall time estimation (VDD → 0, load capacitance discharging

through the nMOS device, assumed in saturation — same approach,
by symmetry):

Idsn = βn/2 · [Vgsn − Vtn]² …(1)

Vgsn = Vin − 0 = Vin = VDD, and Vtn = 0.2 VDD …(2)

Vout = Idsp × t / CL …(3)

Substituting (2) and (3) into (1):

Tf = 3.125·CL / (βn·VDD)

Result:

Tr / Tf = βn / βp ⟹ Tr/Tf = μn/μp, if Zpu = Zpd

Since μn = 2.5 μp:

Tr = 2.5 × Tf

Summary: Because electron mobility (μn) is roughly 2.5× hole

mobility (μp), a CMOS inverter with equal-sized pMOS and nMOS
devices (Zpu = Zpd) will have a rise time 2.5× longer than its fall
time — the pMOS pull-up is inherently “weaker” than the nMOS pull-
down for the same device sizing. This is why pMOS transistors are
typically sized wider (larger W) than nMOS in real CMOS designs, to
balance rise and fall times.

Q6(a). List and explain the basic layers of MOS

Circuits

(Directly from your notes)

Any MOS circuit consists of four basic layers: 1. N-diffusion 2. P-

diffusion 3. Polysilicon 4. Metal

The interaction of the polysilicon and thinox (diffusion) regions is what

forms a transistor — wherever a polysilicon line crosses a diffusion
(thinox) region, a transistor is created at that crossing. If two layers
need to be deliberately joined (connected) rather than just crossing, a
contact must be made between them.

Stick diagram color/monochrome encoding (nMOS process,

from your notes’ table):

Color Layer CIF Layer

Green n-diffusion (n⁺ active) / Thinox ND
Red Polysilicon NP
Blue Metal 1 NM
Black Contact cut NC
Gray Overglass NG
Yellow (nMOS only) Implant NI
Brown (nMOS only) Buried contact NB

For CMOS process (additional/extended encoding from your

notes): - Green (or Green in P⁺ mask/Yellow stick) → p-diffusion (p⁺
active) - Dark blue or purple → Metal 2 - Black → VIA - Brown → p-well
edge, shown as a demarcation line in stick diagrams (p-type
transistors placed above the line, n-type below) - Black (X symbol) →
VDD or VSS contact

Monochrome coding (black-and-white lines, without color) is also used

to convey the same layer information where color isn’t available,
without losing any layer distinction.

Q6(b). With circuit diagram explain the working of

nMOS Inverter. Obtain the pull-up to pull-down ratio

(Directly from your notes)

Circuit: An nMOS inverter has a pull-up transistor (Q1), typically a

depletion-mode device, connected between VDD and the output node,
and a pull-down transistor (Q2), an enhancement-mode device,
connected between the output node and ground, gated by the input
Vin. The output node also has a load capacitance (shown as 1□Cg in
your notes).

Working: - When Vin = 0 (logic 0): Q2 (pull-down) is OFF, Q1 (pull-

up) is always ON (its gate is tied appropriately to stay conducting) —
so the output charges up toward VDD through Q1. Output = logic 1. -
When Vin = 1 (logic 1): Q2 turns ON, and since Q1 is always on, both
transistors conduct simultaneously — the output is pulled low
through the resistive divider formed by Q1 and Q2, and this condition
causes continuous static power dissipation through the direct VDD-
to-GND current path.

Pull-up to pull-down ratio: - Given Zpu:Zpd (channel resistance

ratio, where Z = L/W), your notes use the example Zpu:Zpd = 4:1. -
Channel resistance R = Z·Rs, so with Rsn (sheet resistance of n-
channel) = 10 kΩ per square: - Pull-up resistance: Zpu = 4 → R = 4 ×
10k = 40 kΩ - Pull-down resistance: Zpd = 1 → R = 1 × 10k = 10 kΩ
- With Vin = 1 (both transistors ON): total resistance Ron = 40k + 10k
= 50 kΩ, which sets up a continuous DC current path from VDD to
ground — this is the source of static power dissipation unique to
nMOS (ratioed) logic, and is precisely why CMOS logic (which never
has both pull-up and pull-down networks simultaneously ON) is
preferred for low static power.

Q8. Derive the expression of delay in terms of τ (time

constant) for nMOS inverter pair

(Directly from your notes — numbered “8” in the question bank,

matching your notes’ “nMOS inverter pair delay” section)

Time constant (τ or T): defined as the time taken to charge one

standard gate area capacitance (1□Cg) through one feature-size-
square of n-channel resistance (1 Rs):

τ = Rs(n-channel) × Cg (per square)

Setup: Consider a pair of cascaded nMOS inverters, each with
identical Zpu:Zpd = 4:1. Let Q1, Q2 be the pull-up/pull-down of
inverter 1, and Q3, Q4 be the pull-up/pull-down of inverter 2.

Case 1: Vin = 0 - Inverter 1: Q1-ON, Q2-OFF → inverter 1 charges

through Q1: Tcharge = 4Rs × 1□Cg = 4T - Inverter 2: Q3-ON, Q4-ON
→ inverter 2 discharges through Q4: Tdischarge = 1Rs × 1□Cg = 1T
- Total delay: Ttot = Tcharge + Tdischarge = 4T + 1T = 5T

Case 2: Vin = 1 - Inverter 1: Q1-ON, Q2-ON → inverter 1 discharges

through Q2: Tdischarge = 1Rs × 1□Cg = 1T - Inverter 2: Q3-ON, Q4-
OFF → inverter 2 charges through Q3: Tcharge = 4Rs × 1□Cg = 4T -
Total delay: Td = Tdischarge + Tcharge = 1T + 4T = 5T

General result:

Td = (1 + Zpu/Zpd) × T

(With Zpu/Zpd = 4, Td = (1+4)T = 5T, matching both cases above.)

Note from your text: for the analogous CMOS inverter pair (with
matching Zpu:Zpd = 4:1, but using different Rs for p and n devices),
the total delay works out to 7T, which is higher than the nMOS pair
delay of 5T.

Q9(i). Define sheet resistance with equation

(Directly from your notes)

Consider a uniform slab of conducting material of resistivity ρ, width

W, thickness t, and length L.

The resistance between two opposite faces:

RAB = ρL / A, where A = area of cross-section = W·t

RAB = ρL / (Wt)

For a square slab (L = W):

RAB = Rs = ρ/t

This is called the sheet resistance, Rs, with units of ohms per
square (Ω/□).

Rs is completely independent of the physical size of the square —

it depends only on the resistivity (ρ) and thickness (t) of the layer.

Typical Rs values (from your notes’ table):

Layer Rs (Ω/□)
Metal 0.03
Diffusion (n or active) 10 to 50
Silicide 2 to 4
Polysilicon 15 to 100
n-transistor channel 10⁴
p-transistor channel 2.5 × 10⁴

For a transistor (or any rectangular region) with channel length-to-

width ratio Z = L/W, the resistance is:

R = Z × Rs
Q9(ii). Calculate the area capacitance — (a) Metal-1,
relative cap = 0.075□Cg (b) Polysilicon, relative cap
= 0.1□Cg ✍ (method from your notes; specific area
value missing from the question)

Your notes give the exact method and relative-capacitance constants

needed here, via a very similar worked example (L=20λ, W=3λ).
However, the question as given in the question bank doesn’t
specify the actual layer dimensions (L × W) or area for this
particular part — only the relative capacitance-per-square values. So
here’s the full method from your notes; you just need to plug in
whatever area/dimensions your instructor’s figure specifies:

Method (from your notes):

1. Find the relative area of the layer, compared to a standard gate

(a 2λ × 2λ square, since 1□Cg is defined for a transistor with W =
L = feature size):

Relative area = (Actual Area) / (2λ × 2λ)

2. Multiply relative area by the given relative capacitance value

to get the area capacitance in units of □Cg:

Capacitance (in □Cg) = Relative Area × Relative

Capacitance value

(a) If the layer is Metal-1, relative capacitance = 0.075□Cg per

unit relative area:

Capacitance = (Relative Area) × 0.075 □Cg

(e.g., using your notes’ worked example area of L=20λ, W=3λ →

relative area = 15 → Capacitance to substrate = 15 × 0.075 = 1.125
□Cg, exactly as shown in your notes for Metal-1.)

(b) If the layer is Polysilicon, relative capacitance = 0.1□Cg per

unit relative area:

Capacitance = (Relative Area) × 0.1 □Cg

(Using the same example area → 15 × 0.1 = 1.5 □Cg, again matching
your notes’ worked example for polysilicon.)

Reminder of the standard unit (1□Cg): defined as the gate-to-

channel capacitance of a MOS transistor with W = L = feature size.
For a 5 µm technology: Area = 5µm × 5µm = 25 µm², Ca = 4×10⁻⁴
pF/µm² ⟹ 1□Cg = 25 × 4×10⁻⁴ = 0.01 pF.

Summary — What’s Actually From Your

Notes
Q Topic Source
✍ adapted (notes
CMOS NAND/NOR
Q1 have nMOS-only
stick diagrams
versions)
Lambda-based
Q2 notes
design rules
✍ adapted (notes
Stick diagram Y=
Q3 have similar (AB+C)′
(A+B+C).D
example)
✍ adapted (notes
Schematic/stick
Q4 have similar (AB+C)′
diagram y=a+bc
example)
Q5 Rise/fall time of notes
CMOS inverter
Basic layers of MOS
Q6(a) notes
circuits
nMOS inverter +
Q6(b) notes
pull-up/down ratio
nMOS inverter pair
Q8 notes
delay (τ)
Sheet resistance
Q9(i) notes
definition
✍ method from
Area capacitance notes, but exact area
Q9(ii)
calculation value missing from
question

Bottom line: 6 of 10 sub-questions are directly from your notes with

full working; the 4 flagged as adapted/method-only follow the exact
same construction techniques your notes use (just applied to slightly
different logic expressions or missing a numeric input), so you can
walk through them with confidence using the same drawing
conventions.