Module 1 — Answer Key

MOS Transistor

Source key: = directly from your uploaded Module-1 notes | ✍ =

adapted (numbers recalculated using the exact method from your
notes, since the question bank uses different values than the worked
example)

Great news: 19 of 20 questions are directly and thoroughly covered

in your notes — this is a very strong module for you.

Q1. Briefly explain how a MOS transistor can be

viewed as a simple ON/OFF switch, with relevant
diagrams

The gate of a MOS transistor controls the flow of current between

source and drain. Simplifying this to the extreme allows MOS
transistors to be viewed as simple ON/OFF switches, using g, s, d to
indicate gate, source, and drain:

MOS Transistor Gate = Logic ‘1’ Gate = Logic ‘0’

nMOS Switch ON Switch OFF
pMOS Switch OFF Switch ON

nMOS: with g = 0, the switch between d and s is OFF (open); with g

= 1, the switch is ON (closed) — current can flow between drain and
source.

pMOS: behaves oppositely — g = 0 gives ON, g = 1 gives OFF.

This is because for an nMOS transistor, the body is grounded and the
source/drain are n-type. When the gate is grounded (g=0), the source–
body and drain–body p-n junctions are reverse-biased, so no current
flows — the transistor is OFF. When the gate voltage is raised, an
electric field attracts free electrons under the gate, forming a
conducting n-type channel (inversion) between source and drain —
the transistor is ON. For pMOS, the situation is reversed (body held at
a positive voltage, conduction via holes).

Q2. Explain MOS structure demonstrating: (a)

Accumulation (b) Depletion (c) Inversion

Consider an isolated MOS structure (gate + gate oxide + body, no

source/drain) with a p-type body, body grounded, and a voltage
applied to the gate. The gate oxide (SiO₂) is a good insulator, so
almost no current flows from gate to body.

(a) Accumulation mode (Vg < 0): A negative voltage on the gate
creates negative charge on the gate. The mobile positively charged
holes in the p-type body are attracted to the region directly beneath
the gate — this is accumulation mode. Condition: VGS < 0.

(b) Depletion mode (0 < Vg < Vt): A small positive voltage on the
gate creates positive charge on the gate. Holes in the body are
repelled from the region beneath the gate, forming a depletion
region (devoid of free carriers) below the gate. Condition: 0 < VGS <
Vt.
(c) Inversion mode (Vg > Vt): A higher positive potential,
exceeding a critical threshold voltage (Vt), attracts even more
positive charge to the gate. Holes are repelled further, and free
electrons in the p-type body are now attracted to the region beneath
the gate, forming a conductive layer of electrons — the inversion
layer. Condition: VGS > Vt.

(Each mode is illustrated in your notes with a cross-section showing

the polysilicon gate, SiO₂ insulator, and p-type body, with + charges
(holes) or − charges/circles (electrons) redistributing beneath the
gate as Vg changes.)

Q3. Explain with necessary sketches the working of n-

channel enhancement type transistor

An nMOS transistor consists of the MOS stack (gate–oxide–body)

placed between two n-type regions called the source and drain. Its
operation has three regions:

(a) Cut-off (Vgs < Vtn): Source grounded; junctions between body
and source/drain are zero- or reverse-biased. No channel forms, so
Ids = 0. The transistor is OFF.

(b) Linear/resistive region (Vgs > Vtn, Vds < Vgs − Vtn): Gate
voltage exceeds threshold, forming an inversion channel (conducting
path of electrons) between source and drain — transistor turns ON. A
small positive Vds causes Ids to flow from drain to source, and Ids
increases with both Vds and Vgs. Also called triode, non-saturated,
or unsaturated region.

(c) Saturation (Vgs > Vtn, Vds > Vgs − Vtn): If Vds becomes large
enough that Vgd < Vtn, the channel is no longer inverted near the
drain — it becomes pinched off. Conduction continues via electron
drift under the positive drain field; electrons reach the channel end
and are injected into the depletion region, accelerated toward the
drain. Beyond this point, Ids is controlled only by gate voltage and
no longer depends on Vds.

Summary table (from your notes):

Condition Region
Vgs < Vtn Cut-off
Vgs > Vtn, Vds < Vgs − Vtn Linear/Resistive
Vgs > Vtn, Vds > Vgs − Vtn Saturation

Q4. With necessary assumptions, derive an

expression for drain current in the linear region for a
long-channel nMOS transistor

Assumptions: Long channel length L (lateral field is relatively low) —

this is the long-channel/ideal/first-order/Shockley model; current
through an OFF transistor is assumed 0.

Derivation:

Charge on the channel (modeled as a capacitor, Q = CV):

Qchannel = Cg (Vgc − Vt) …(1.1)

where Cg = gate-to-channel capacitance, and (Vgc − Vt) = voltage

attracting charge beyond the minimum needed for inversion.

With source at Vs, drain at Vd, average channel potential Vc = Vs +

Vds/2, and Vgs = Vg − Vs:
Vgc = Vg − Vc = Vgs − Vds/2 …(1.2)

Modeling the gate as a parallel-plate capacitor (length L, width W,

oxide thickness tox):

Cg = Cox · W · L, where Cox = εrε₀/tox …(1.3)

Each carrier drifts at velocity v = μE (μ = mobility), where E = Vds/L

…(1.4, 1.5)

Current is the total channel charge divided by transit time:

Ids = Qchannel / (L/v) …(1.6)

Substituting (1.1)–(1.5) into (1.6):

Ids = μCox (W/L)(Vgs − Vt − Vds/2)·Vds

This is rewritten using β = μCox(W/L) (the process parameter):

Ids = β [(Vgs − Vt)Vds − Vds²/2] …(1.7)

Condition: This applies when Vds < Vgs − Vt (channel not yet
pinched off) — the linear/resistive region.

Q5. Derive a drain current expression of the 1st-order

Shockley model for nMOS operating as a constant
current source (saturation)

Starting from the linear-region equation (1.7):

Ids = β [(Vgs − Vt)Vds − Vds²/2]

At the boundary of saturation, Vds = Vgs − Vt (pinch-off condition —

channel no longer inverted near the drain, refer Q3/Q4). Substituting
Vds = Vgs − Vt into (1.7):

Ids = β [(Vgs − Vt)(Vgs − Vt) − (Vgs − Vt)²/2]

⟹ Ids = (β/2)(Vgs − Vt)² …(1.8)

Condition: Vgs > Vt and Vds > Vgs − Vt — this is the saturation
region. Beyond the pinch-off point, increasing Vds has no further
effect on current — Ids is controlled only by the gate voltage,
behaving as a constant current source.

Worked example (from your notes): For an nMOS transistor, W/L =

2, tox = 100 Å, μn = 350 cm²/V·s, Vt = 0.6 V, Vgs = 1.2 V, Vds = 1.2 V:

Cox = εrε₀/tox = (3.9 × 8.854×10⁻¹⁴)/(100×10⁻¹⁰×10²) = 0.345 µF

β = μCox(W/L) = 350 × 0.345µ × 2 = 241.71 µA/V²
Since Vds > Vgs − Vt, device is in saturation:
Ids = (β/2)(Vgs−Vt)² = (241.71µ/2)(1.2−0.3)² = 97.89 µA

Q6. List out the V-I expressions for nMOS and pMOS
in all modes of operation, with necessary operating
conditions

nMOS transistor (Table 1.1 from your notes):

Region Expression Condition

Cut-off Ids = 0 Vgs < Vt
Ids = β[(Vgs−Vt)Vds − Vgs > Vt, Vds <
Linear
Vds²/2] Vgs−Vt
Vgs > Vt, Vds >
 Saturation Ids = (β/2)(Vgs−Vt)² Vgs−Vt

For pMOS transistor, the equations are structurally identical (with

all polarities/voltages reversed, since pMOS conducts via holes and
Vtp is negative):

Region Condition
Cut-off Vgs-p > Vtp (equivalently Vin > Vtp + Vdd)
Linear Vgs-p < Vtp, and Vds-p > Vgs-p − Vtp
Saturation Vgs-p < Vtp, and Vds-p < Vgs-p − Vtp

(Your notes’ Table 1.1 in section 1.5.1 gives the full nMOS/pMOS
voltage relationships side by side — see Q8 below for that full table,
since it directly answers both questions.)

Q7. Briefly explain the following non-ideal V-I effects

for an nMOS enhancement transistor: (a) Mobility
degradation (b) Velocity saturation (c) Body effect (d)
DIBL (e) Channel length modulation (f) Sub-
threshold conduction (g) Gate leakage

The ideal Shockley model (Table 1.1) ignores several real, non-ideal
behaviors:

(a) Mobility degradation: v = μE assumes μ is independent of the

vertical field E. This breaks down for strong fields — a high gate
voltage attracts carriers in the inversion layer so strongly that they
collide with the oxide interface, causing effective mobility to decrease
as Vgs increases.

(b) Velocity saturation: Under strong lateral fields (from Vds),

carriers accelerate and collisions with the silicon lattice increase;
beyond a certain field strength, drift velocity saturates at vsat. Since
E = Vds/L, shorter channels reach velocity saturation at much lower
Vds than long-channel devices.

(c) Body effect: If the body is not tied to the source (held at a
different potential), the threshold voltage varies:

Vt = Vt0 + γ(√(φs + Vsb) − √φs) …(1.9)

where Vt0 = threshold when Vsb = 0, γ = body effect coefficient, φs =

surface potential at threshold. Threshold voltage increases with
source voltage and decreases with body voltage.

(d) Drain-induced barrier lowering (DIBL): The drain-body p-n

junction is reverse-biased; as Vds increases, this reverse bias
increases, expanding the depletion region into the channel. Since the
depletion region has no mobile carriers, the gate has less channel left
to deplete/invert — so threshold voltage decreases. Prominent only
in short-channel devices, where channel length is comparable to
depletion-region length.

(e) Channel length modulation: As Vds increases, the depletion

region grows and effective channel length shortens; since Ids ∝ 1/L,
current increases with Vds even in “saturation.” Incorporating this:

Ids = (β/2)(Vgs − Vt)² × (1 + λVds) …(1.10)

where λ is the channel-length-modulation parameter. Most prominent

in short-channel devices.

(f) Sub-threshold conduction: Ids does not cut off abruptly at Vgs =

Vt — as Vgs drops below Vt, Ids decreases exponentially rather
than becoming exactly zero.
(g) Gate leakage: Ideally the gate-channel capacitor passes no
current. But as oxide thickness decreases, electrons tunnel across
the thin oxide, creating gate leakage current — reducible by using
higher-dielectric-constant gate materials instead of SiO₂.

Q8. Obtain the relationships between voltages for the

three regions of operation of a CMOS inverter, with
necessary conditions

(Directly from Table 1.1, section 1.5.1 of your notes)

Let Vtn = nMOS threshold, Vtp = pMOS threshold (negative value).

With nMOS source grounded: Vgs-n = Vin, Vds-n = Vout. With pMOS
source at VDD: Vgs-p = Vin − Vdd, Vds-p = Vout − Vdd.

Region nMOS condition pMOS condition

Cut-off Vin < Vtn Vin > Vtp + Vdd
Vin > Vtn and Vout Vin < Vtp + Vdd and
Linear/Resistive
< Vin − Vtn Vout > Vin − Vtn
Saturation/Current Vin > Vtn and Vout Vin < Vtp + Vdd and
source > Vin − Vtn Vout < Vin − Vtn

These voltage relationships are exactly what defines the five

operating regions (A–E) of the CMOS inverter’s DC transfer
characteristic — see Q9 below.

Q9. With necessary diagrams, explain the operation

of a static CMOS inverter and mention the state of
transistors in various regions of operation

Circuit: A CMOS inverter has a pMOS pull-up (source at VDD) and

nMOS pull-down (source at GND), gates tied together to Vin, drains
tied together at Vout.

For simplicity, assume Vtn = −Vtp and βn = βp. The DC transfer

characteristic (Vout vs. Vin) divides into five regions:

Region Condition nMOS pMOS Output

0 ≤ Vin ≤ Vout = VDD
A Cut-off Linear
Vtn (Logic ‘1’)
Vtn ≤ Vin ≤ Vout >
B Saturation Linear
VDD/2 VDD/2
Vin = Vout drops
C Saturation Saturation
VDD/2 sharply
VDD/2 ≤
Vout <
D Vin ≤ Linear Saturation
VDD/2
(VDD+Vtp)
(VDD+Vtp)
Vout = VSS
E ≤ Vin ≤ Linear Cut-off
(Logic ‘0’)
VDD

Key observations: - Region A: nMOS OFF (Ids-n = 0) ⟹ since Ids-n

= −Ids-p, pMOS current is also zero ⟹ Vout = VDD. - Region B:
nMOS starts to turn ON, pulling output down while still > VDD/2. -
Region C: Both transistors in saturation simultaneously — ideal
transistors are only exactly here at Vin = VDD/2; output transitions
sharply. - Region D: pMOS partially ON, pulling output further down
(< VDD/2). - Region E: pMOS OFF (Ids-p = 0) ⟹ nMOS current also
zero ⟹ Vout = 0 V.
The supply current IDD = Idsn = |Idsp| forms a pulse as Vin sweeps
between GND and VDD — both transistors are momentarily ON
simultaneously, drawing current from the supply (this is the source of
dynamic/short-circuit power dissipation in CMOS).

Q10. What are skewed inverters? Obtain the transfer

characteristic of skewed inverters

When βp = βn, the CMOS inverter switching threshold Vinv =

VDD/2 — this maximizes noise margins and gives equal current
source/sink capability (equal charge/discharge times for capacitive
loads).

Inverters with a beta ratio r = βp/βn ≠ 1 are called skewed

inverters: - r > 1 → HI-skewed: stronger pMOS ⟹ Vinv > VDD/2 - r
< 1 → LO-skewed: weaker pMOS ⟹ Vinv < VDD/2 - r = 1 → normal
skew / unskewed: Vinv = VDD/2

Transfer characteristic: As the beta ratio βp/βn is varied (e.g., 0.1,

0.5, 1, 2, 10 as plotted in your notes), the switching threshold moves
left or right along the Vin axis — but the output transition remains
sharp in every case. Gates are typically skewed by adjusting
transistor widths (keeping length at minimum, for speed).

Analytical derivation of Vinv: In the region where both transistors

are in saturation:

Ids-n = (βn/2)(Vinv − Vtn)², Ids-p = (βp/2)(Vinv − VDD − Vtp)²

Setting currents equal and opposite and solving for Vinv:

Vinv = [Vdd + Vtp + Vtn√(1/r)] / [1 + √(1/r)]

When Vtn = −Vtp and βp = βn (r = 1), this reduces to Vinv = VDD/2,

as expected.

Q11. Derive the threshold voltage of a CMOS inverter

(This is the same derivation as Q10’s analytical part — “threshold

voltage of a CMOS inverter” = the switching threshold Vinv)

In region C, both nMOS and pMOS operate in saturation:

Ids-n = (βn/2)(Vinv − Vtn)² and Ids-p = (βp/2)(Vinv − VDD − Vtp)²

Since the currents through both devices must be equal and opposite:

(βn/2)(Vinv − Vtn)² = −[(βp/2)(Vinv − VDD − Vtp)²]

Taking square roots and rearranging:

√(βn/βp) · (Vinv − Vtn) = −(Vinv − VDD − Vtp) = (VDD + Vtp − Vinv)

Solving for Vinv, in terms of r = βp/βn:

Vinv = [VDD + Vtp + Vtn√(βn/βp)] / [1 + √(βn/βp)] = [VDD +

Vtp + Vtn√(1/r)] / [1 + √(1/r)]

If Vtn = −Vtp and βp = βn (r=1): Vinv = VDD/2.

Q12. Define the following for digital circuits: (a)

Noise Margin (b) Noise Immunity
Noise Margin: the parameter that determines the allowable noise
voltage on the input of a gate such that the output is not corrupted. It
is described using two values: - NML (LOW noise margin):
difference between the maximum LOW input voltage recognized by
the receiving gate and the maximum LOW output voltage produced by
the driving gate: NML = VOL-Max − VIL-Max - NMH (HIGH noise
margin): difference between the minimum HIGH output voltage
produced by the driving gate and the minimum HIGH input voltage
recognized by the receiving gate: NMH = VOH-Min − VIH-Min

Noise Immunity: the general property/ability of a logic gate or

circuit to tolerate a certain amount of unwanted noise voltage on
its inputs without producing an incorrect (corrupted) output — noise
margin is the quantitative measure used to describe this immunity.

Q13. Explain Noise Margin and its related

parameters with a neat diagram

Inputs between VIL and VIH fall in the indeterminate region

(forbidden zone) — not valid logic levels. It is desirable to have VIH
as close as possible to VIL, ideally midway in the logic swing (VOL to
VOH).

Diagram structure (as in your notes’ Fig. 12): two cascaded

inverter symbols with, on the left, the driving gate’s Output
Characteristics (Logical High Output Range near VDD, Logical Low
Output Range near GND) and on the right, the receiving gate’s Input
Characteristics, split by an Indeterminate Region in the middle: -
VOH marks the top of the driving gate’s guaranteed HIGH output; VIH
marks where the receiving gate’s HIGH input range begins — the gap
between them is NMH. - VOL marks the driving gate’s guaranteed
LOW output; VIL marks the top of the receiving gate’s LOW input
range — the gap between them is NML.

Related parameters: VIH-Min (minimum HIGH input voltage), VIL-

Max (maximum LOW input voltage), VOH-Min (minimum HIGH output
voltage), VOL-Max (maximum LOW output voltage).

Worked example (from your notes): Two cascaded inverters with

VDD=5V, VIL=1.35V, VIH=3.15V, VOL=0.33V, VOH=3.84V: - NMH =
VOH-Min − VIH-Min = 3.84 − 3.15 = 0.69 V - NML = VIL-Max −
VOL-Max = 1.35 − 0.33 = 1.02 V - For 1 V of noise: the circuit
cannot tolerate noise on a HIGH signal (NMH = 0.69 V < 1 V), but
can tolerate noise on a LOW signal (NML = 1.02 V > 1 V).

Q14. With relevant diagrams, brief out how voltage

drops occur in nMOS and pMOS pass transistor
circuits

An nMOS transistor is an almost perfect switch when passing logic

‘0’ (strong 0), but is imperfect passing logic ‘1’ — the high level is
somewhat less than VDD, called a degraded/weak 1.

A pMOS transistor behaves oppositely — passes strong 1s but

degraded 0s.

Transistor State Logic ‘0’ Logic ‘1’

nMOS Gate=1, ON strong 0 degraded/weak 1
pMOS Gate=0, ON degraded/weak 0 strong 1

Why the voltage drop occurs (nMOS passing a 1): With gate and
drain tied to VDD, and source initially at Vs = 0, Vgs > Vtn so the
transistor is ON. As the source voltage rises (charging up), once Vs =
VDD − Vtn, Vgs falls to exactly Vtn and the transistor cuts itself
OFF — so nMOS transistors passing a 1 never pull the source above
VDD − Vtn. This loss is called the threshold drop.

Similarly, a pMOS transistor passing a 0 cuts off once its source drops

to |Vtp| above GND — so pMOS transistors only pull down to within a
threshold of GND.

Series transistors: Since the source can rise to within a threshold of

the gate, several nMOS transistors in series produce output no more
degraded than a single transistor. However, if a degraded output
drives the gate of a subsequent transistor, that second transistor’s
output becomes even further degraded (e.g., two cascaded
degraded stages can compound to a 2Vtn or 2Vtp loss).

Q15. Give an expression for the output voltage for the

pass transistor networks shown in Fig. Neglect the
body effect

(From your notes’ Example 3, Figure 16 — four pass-transistor

network configurations)

(a) Two nMOS transistors, gates both tied to VDD, source of first
transistor tied to GND: - Gate = ‘1’ for both ⟹ both nMOS ON,
passing logic ‘0’ perfectly (no degradation, since nMOS passes strong
0). - Vout = 0

(b) First pMOS’s gate tied to GND, its drain tied to GND (second
pMOS gate driven by first’s output): - Gate = ‘0’ ⟹ t1 ON, passing a
degraded logic ‘0’ (Vtp) to the gate of t2. - t2’s gate isn’t a perfect
‘0’ (it’s 1·Vtp above true 0), so t2’s output is further degraded by
another Vtp. - Vout = 2|Vtp|

(c) pMOS (t1) gate tied to GND; nMOS (t2) gate tied to VDD — both
ON; drain connected to GND: - pMOS passes the degraded logic ‘0’
(Vtp) to the source of the nMOS (t2). - The nMOS passes this same
value straight through to its output (since nMOS passes 0s perfectly
with no further degradation, once it has a valid input). - Vout = |Vtp|

(d) Similar analysis (nMOS pass network passing a ‘1’): - Vout = VDD
− Vtn

Q16. Suppose VDD = 1.8 V and Vt = 0.8 V. Determine

Vout for the following. Neglect the body effect. (a)
Vin=0V (b) Vin=0.6V (c) Vin=0.9V (d) Vin=1.2V ✍
(method directly from your notes’ worked Example 4,
recalculated for these VDD/Vt values)

Setup (from your notes’ Fig. 17): A single nMOS pass transistor
with its gate tied to VDD, Vin driving one side, Vout on the other. For
the nMOS to stay ON, VGS > Vt must hold. With VG = VDD = 1.8 V
and Vt = 0.8 V, the transistor remains ON only up to an output
voltage of VDD − Vt = 1.8 − 0.8 = 1.0 V. Beyond that, the nMOS
cuts itself off (threshold drop, per Q14).

(a) Vin = 0 V: VGS = VG − VS = 1.8 − 0 = 1.8 V > 0.8 V, so

transistor is ON. Since Vin = 0 V is well below the 1.0 V cutoff limit,
output tracks input fully. Vout = 0 V

(b) Vin = 0.6 V: Still below the 1.0 V cutoff limit, so the nMOS
conducts fully and Vout tracks Vin. Vout = 0.6 V

(c) Vin = 0.9 V: Still below 1.0 V, transistor still conducting. Vout =
0.9 V
 (d) Vin = 1.2 V: This exceeds the 1.0 V limit. Once Vout charges up to
VDD − Vt = 1.0 V, the nMOS’s effective VGS drops to exactly Vt and it
ceases to conduct (turns OFF) — the output cannot rise any
further, even though Vin = 1.2 V. Vout = 1.0 V (capped/degraded due
to threshold drop — this is the classic nMOS “weak/degraded 1”
behavior from Q14)

Q17. With necessary diagram, explain the nMOS

fabrication process

(From your notes, section 1.6.1, Figure 17 a–l)

1. (a) Start: bare silicon (Si) substrate.

2. (b) Oxidation: a relatively thick SiO₂ layer, the field oxide, is
grown on the surface.
3. (c) Selective etching: the field oxide is selectively etched to
expose bare silicon where the MOS transistor will be formed.
4. (d) Thin gate oxide growth: a thin, high-quality oxide layer is
grown on the exposed area — this becomes the gate oxide.
5. (e) Polysilicon deposition: a layer of polysilicon (polycrystalline
silicon) is deposited over the thin oxide — used both as the
transistor’s gate electrode and as an interconnect medium.
(Undoped poly has high resistivity; doping reduces it.)
6. (f) Pattern polysilicon: the polysilicon is patterned/etched to
form the gate and interconnects; the thin gate oxide not covered
by poly is also etched away, exposing bare silicon where
source/drain will form.
7. Doping: the exposed silicon surface is doped with a high
concentration of donor impurities (n-type doping) via diffusion or
ion implantation, forming the n+ source and drain regions.
Because the poly gate (patterned earlier) blocks doping directly
beneath it, the source/drain are automatically aligned to the gate
edges — this is called the self-aligned process.
8. (i) Insulating oxide: the whole surface is covered again with
insulating SiO₂.
9. Contact windows: the insulating oxide is patterned to open
contact windows down to the source/drain junctions.
10. (l) Metallization: the surface is covered with evaporated
aluminum, which is then patterned/etched to form the
interconnects, completing the transistor wiring. (A second/third
metal layer may be added similarly, using further insulating layers
and via holes.)

Q18. With necessary diagram, explain the p-well

CMOS fabrication process

(From your notes, section 1.6.2, Figure 18)

The p-well process starts with an n-type substrate. The n-type

substrate directly hosts the pMOS transistor; to build the nMOS
transistor, a p-well must be diffused into the substrate to provide the
p-type body it needs — so both device types coexist on the same n-
type substrate.

Mask sequence: 1. Mask 1: defines the areas where deep p-well

diffusion takes place. 2. Mask 2: defines the thin oxide (thinox)
region — where thick field oxide is stripped and thin gate oxide
grown. 3. Mask 3: patterns the polysilicon layer (deposited after the
thin oxide). 4. Mask 4: a p+ mask (ANDed with mask 2) defining
where p-diffusion takes place. 5. Mask 5: the negative
(complement) of mask 4, defining where n-diffusion takes place. 6.
Mask 6: defines the contact cuts. 7. Mask 7: defines the metal
layer pattern. 8. Mask 8: applies an overall passivation (overglass)
layer, with openings for bonding pads.
Cross-section (Fig 18): shows the n-type substrate with a p-well (4–
5 µm deep) diffused into one region; SiO₂ field oxide separates active
areas; polysilicon gates sit over thin oxide; p-diffusion (source/drain of
the pMOS, in the n-substrate) and n-diffusion (source/drain of the
nMOS, in the p-well) are formed via the p+ mask and its complement
respectively. The final CMOS p-well inverter cross-section shows VDD
connected to the pMOS (in the n-substrate) and VSS connected to the
nMOS (in the p-well), with Vin driving both gates and Vout taken from
the shared drain node.

Q19. With necessary diagram, explain the n-well

CMOS fabrication process

(From your notes, Figure 19 — main process steps)

Process flow (as a sequence of steps): 1. Formation of n-well

regions — the first mask defines the n-well; a low-dose phosphorous
implant is driven in via high-temperature diffusion to form the n-wells.
Well depth is optimized to avoid p-substrate-to-p+ diffusion
breakdown, without compromising n-well-to-n+ mask separation. 2.
Define nMOS and pMOS active areas. 3. Field and gate
oxidations (thinox). 4. Form and pattern polysilicon. 5. p+
diffusion — forms the pMOS source/drain (in the n-well) and, along
with its complement, defines the VDD/VSS contact regions. 6. n+
diffusion — forms the nMOS source/drain (directly in the p-type
substrate). 7. Contact cuts. 8. Deposit and pattern metallization.
9. Overglass, with cuts for bonding pads.

Key note (from your notes): an n+ mask and its complement

may be used to define the n- and p-diffusion regions respectively
(these masks also include the VDD and VSS contacts). Alternatively, a
p+ mask and its complement could be used instead, since n+ and
p+ masks are generally complementary.

Q20. With necessary diagram, explain the twin-tub

CMOS fabrication process

(From your notes — Twin-tub process)

The twin-tub process uses both a p-well and an n-well approach

simultaneously. The starting point is a substrate of high-resistivity n-
type material (with an epitaxial layer), into which both an n-well and
a p-well are formed.

Advantage: By independently optimizing both wells, this process

makes it possible to preserve the performance of the n-
transistors without compromising the p-transistors (unlike
single-well processes, where one device type is built directly in the
native substrate and the other in a compromise well). Doping control
is more readily achieved, and some relaxation in manufacturing
tolerances results.

Cross-section (Fig. 19, twin-tub): shows an n-substrate with an

epitaxial layer on top; an n-well region hosts one device type and a
p-well region hosts the other, side by side; VDD connects to the
transistor in the n-well, VSS to the transistor in the p-well, with
Vin/Vout forming the inverter’s input/output nodes at the shared
gate/drain connections.

Important note from your text: the twin-tub process is one of

the solutions to the latch-up problem — a parasitic issue where
CMOS structures can form unwanted thyristor-like (SCR) paths
between adjacent n-well/p-well junctions, causing a short-circuit
condition; independently optimized wells help suppress this.
Summary — What’s Actually From Your
Notes
Q Topic Source
MOS transistor as ON/OFF
Q1 notes
switch
Q2 Accumulation/depletion/inversion notes
n-channel enhancement
Q3 notes
transistor working
Linear-region drain current
Q4 notes
derivation
Saturation-region (Shockley)
Q5 notes
derivation
V-I expressions nMOS/pMOS all
Q6 notes
modes
Non-ideal V-I effects (7 sub-
Q7 notes
parts)
CMOS inverter region voltage
Q8 notes
relationships
Q9 Static CMOS inverter operation notes
Skewed inverters + transfer
Q10 notes
characteristic
CMOS inverter threshold voltage
Q11 notes
derivation
Noise Margin / Noise Immunity
Q12 notes
definitions
Noise margin diagram +
Q13 notes
example
Q14 Pass transistor voltage drops notes
Pass transistor network output
Q15 notes
expressions
✍ same method,
Numeric Vout calculation
Q16 recalculated
(VDD=1.8V, Vt=0.8V)
values
Q17 nMOS fabrication process notes
Q18 p-well CMOS fabrication notes
Q19 n-well CMOS fabrication notes
Q20 Twin-tub CMOS fabrication notes

Bottom line: This is your strongest module by far — 19 of 20

questions come straight from your notes with full derivations,
diagrams, and worked examples. Q16 just needed the numbers
recalculated for the specific VDD/Vt given in the question bank, using
the identical method your notes already walk through.