TECHNICAL REVISION HANDBOOK

Memristors & Neuromorphic Computing

From Circuit Fundamentals to Brain-Inspired Hardware

Field Information
Audience Undergraduate engineering students with foundational circuit knowledge
Scope Circuit theory → Memristor mathematics → Device physics →
Neuromorphic systems
Primary References Chua (1971) IEEE Trans. Circuit Theory; Strukov et al. (2008) Nature
Institutional Context DRDO–SSPL Internship Research Programme, Four-Week Study Track
Structure Ten chapters progressing from first principles to advanced applications
Pedagogical Tools Worked analogies, memory aids, error flags, exam preparation, interview
guides

Pedagogical Goals: build conceptual depth from zero; prioritise understanding over memorisation; remain self-
contained throughout.
Chapter 1 — Circuit Theory Foundations
Every aspect of memristor theory draws from a small set of fundamental circuit variables. A clear
command of these variables — and the relationships among them — is the prerequisite from which
everything else follows.

1.1 The Four Fundamental Circuit Variables

Classical circuit analysis is anchored by two measurable, primary quantities and two derived
quantities obtained by integrating them over time:

Variable Symbol Unit Physical Significance Mathematical Form

Current i(t) Ampere (A) Rate at which electric charge i = dq/dt
traverses a cross-section
Voltage v(t) Volt (V) Energy delivered per unit charge; v = dφ/dt
also the time-rate of flux change
Charge q(t) Coulomb (C) Cumulative charge that has passed q(t) = ∫ i(τ) dτ
through a terminal
Flux-linkage φ(t) Weber (Wb) Running time-integral of the φ(t) = ∫ v(τ) dτ
terminal voltage

⚠️Frequent Misconception: The flux-linkage φ used in memristor theory is not the same as
the magnetic flux threading a coil. It is simply the mathematical integral of terminal voltage
— no coil or magnetic field is involved. The terminology is borrowed from classical circuit
theory and carries no electromagnetic implication.

1.2 The Six Pairwise Relationships Among Circuit Variables

Four variables can be combined in C(4,2) = 6 distinct pairs. Two of those pairings are identities by
definition; the remaining four correspond to physical circuit elements. As of 1971, only three
elements had been identified, leaving one pairing without a physical realisation:

Variable Pair Relationship Class Circuit Element Status in 1971

i↔v Instantaneous Resistor (R) → v = R·i ✅ Established
q↔v Integral Capacitor (C) → q = C·v ✅ Established
φ↔i Integral Inductor (L) → φ = L·i ✅ Established
φ↔q Unknown MEMRISTOR (M) — the missing ❌ Predicted; not yet
element found
q↔i Definitional q = ∫ i dt ✅ By definition
φ↔v Physical law v = dφ/dt ✅ Follows from Faraday

💡 Historical Analogy: Chua's theoretical deduction of the memristor parallels Mendeleev's

prediction of undiscovered chemical elements through the periodicity of the atomic table in
 1869. In both cases, an observed mathematical symmetry demanded a missing physical
entity — and in both cases, experiment confirmed the prediction decades later.

1.3 Recapitulation: The Three Classical Elements

Element Symbol Constitutive Relation Defining Characteristic
Resistor R v = R·i (Ohm's Law) Instantaneous response; no energy
storage; dissipates power
Capacitor C q = C·v Stores energy in the electric field; voltage
reflects charge history
Inductor L φ = L·i Stores energy in the magnetic field; flux
reflects current history
Memristor M dφ = M(q)·dq Resistance encodes full charge history —
the element has memory

⚡ Chapter 1 — Key Takeaways: • Four variables: current i, voltage v, charge q, flux-linkage φ

• Six pairings → two definitions + three classical elements + one missing → memristor • φ =
∫v dt, not magnetic flux in a coil • The memristor is the sole element directly linking φ to q
Chapter 2 — The Memristor: Theory and Mathematics
2.1 Defining the Memristor
A memristor is a passive, two-terminal element whose instantaneous resistance is not a fixed
property of the material but rather a functional of the entire past current waveform. Critically, when
current ceases, the device retains its most recent resistance value — it "remembers" the
accumulated effect of prior charge flow.
💧 Pipe Analogy: Picture a water pipe whose bore diameter shifts permanently in response to
the cumulative volume of water that has ever passed through it. Greater total flow widens
the bore, lowering flow resistance; reversed flow narrows it again. The pipe carries a
permanent record of its own history — that is the operating principle of a memristor.

2.2 Constitutive Relation

The memristor is formally characterised by a single-valued functional relationship between φ and q,
typically expressed as g(φ, q) = 0. This traces out a curve in the φ–q plane that plays the same role as
the v–i characteristic for a resistor.

Case A — Charge-Controlled Formulation

When flux-linkage is a unique function of accumulated charge (φ = φ(q)), the terminal voltage obeys:
v(t) = M(q(t)) · i(t) [Equation 1, Chua 1971]
where the incremental memristance is:
M(q) ≡ dφ(q)/dq [Unit: Ohms, Ω]

Case B — Flux-Controlled Formulation

When charge is a unique function of flux-linkage (q = q(φ)), the terminal current obeys:
i(t) = W(φ(t)) · v(t) [Equation 3, Chua 1971]
where the incremental memductance is:
W(φ) ≡ dq(φ)/dφ [Unit: Siemens, S]
🔑 Core Insight: At any instant t₀, the memristor satisfies v = M(q)·i — superficially identical to
Ohm's Law. However, M(q) is not a fixed constant; it equals dφ/dq evaluated at the value of
q(t₀), which itself encodes the complete prior history of current flow. The device is therefore
instantaneously Ohmic but with a time-varying, history-dependent resistance.

2.3 The φ–q Curve

The φ–q plot is to the memristor what the v–i plot is to a resistor — a complete behavioural
fingerprint. Key geometric properties:
• Slope at any point equals M(q) at that accumulated charge
• A straight-line φ–q locus → M(q) = constant → the device degenerates to a linear resistor
• A nonlinear locus → M(q) varies with charge → the device exhibits genuine memory behaviour
• Monotonic increase in φ with q is required by Theorem 1 (passivity) for any physically
realisable passive device
 ❌ Common Confusion: The φ–q curve cannot be observed on a standard oscilloscope; that
instrument displays v vs i. Chua had to construct a dedicated φ–q tracer using analogue
integrators to measure it directly.

2.4 The Pinched Hysteresis Loop

Under sinusoidal excitation, the plot of v(t) versus i(t) for a memristor produces a characteristic
figure-eight curve that is pinched at the origin. This pinched hysteresis loop serves as the primary
experimental diagnostic for memristive behaviour. Four properties must hold simultaneously:
• The loop always intersects the origin — the "pinch point"
• The enclosed area contracts monotonically as driving frequency rises
• At sufficiently high frequency, the loop collapses to a straight line through the origin, indicating
resistor-like behaviour
• At low frequencies, the loop is widest, signifying the strongest memory effect
🎯 Examination Note: The experimental verification protocol demands three concurrent
tests: (1) the i–v curve forms a pinched loop passing through the origin; (2) loop area
decreases with increasing frequency; (3) the loop degenerates to a line at high frequency. All
three must be satisfied — any single criterion alone is insufficient.
❌ Diagnostic Rule: A hysteresis loop that does not pass through the origin disqualifies the
device as a memristor. Such a device is more likely a nonlinear capacitor or inductor
exhibiting spurious hysteresis.

2.5 Physical Basis of Frequency Dependence

At elevated driving frequencies, each half-cycle is too brief for significant charge to accumulate. The
state variable q therefore oscillates near its initial value, M(q) scarcely changes, and the device
approximates a fixed resistor — the loop collapses. At low frequencies, charge accumulates
substantially over each half-cycle; M(q) sweeps a wide range, and the hysteresis is pronounced.

2.6 Memory Aid — RICE-M

🧠 Mnemonic: R — Resistor (v ↔ i) | I — Inductor (φ ↔ i) | C — Capacitor (q ↔ v) | E —
"Extra" = Memristor (φ ↔ q) | M — Memory is its defining attribute
⚡ Chapter 2 — Key Takeaways: • M(q) = dφ/dq [Ω]; W(φ) = dq/dφ [S] • Instantaneously
Ohmic, but M depends on cumulative charge history • Pinched hysteresis loop through
origin = necessary experimental signature • Loop collapses at high frequency; widens at low
frequency • Passivity demands monotonically increasing φ–q curve
Chapter 3 — Five Foundational Theorems (Chua, 1971)
Chua established five rigorous theorems governing the behaviour of memristors and networks
composed of them. Mastery of each theorem — statement, derivation, and physical implication — is
essential for both examination and research discussions.

Theorem 1 — Passivity Criterion

Statement:
A memristor is passive if and only if M(q) ≥ 0 for every value of accumulated charge q.
Three-Step Proof:
Instantaneous power: p(t) = v(t)·i(t) = M(q(t))·[i(t)]²
If M(q) ≥ 0 for all q → p(t) ≥ 0 at all times → the device absorbs (or at most returns) energy → it is
passive.
If M(q₀) < 0 for some q₀ → an input can be constructed that keeps q near q₀, yielding p < 0 → the
device generates net energy → it is active.
Physical Implication:
Only those memristors whose φ–q curves are monotonically non-decreasing can serve as standalone
passive components. A negative memristance region signals dependence on an internal energy
source.
🔗 Connection to HP 2008: The TiO₂ device reported by Strukov et al. satisfies M(q) > 0
throughout its operating range. Theorem 1 is what allowed HP's researchers to classify it as a
genuinely passive memristor.

Theorem 2 — Closure Under Interconnection

Statement:
Any one-port network constructed exclusively from memristors is electrically equivalent to a single
memristor.
💡 Resistor Analogy: Just as an arbitrarily complex network of linear resistors collapses to a
single Thévenin-equivalent resistance, a network built solely from memristors collapses to a
single equivalent memristor. The class of memristors is 'closed' under interconnection.
Proof Sketch:
Applying KCL and KVL to the network and integrating both relations over time converts all equations
into φ–q relations. The composite port therefore satisfies a φ–q relation, confirming it is itself a
memristor. □

Theorem 3 — Existence and Uniqueness

Statement:
A network composed entirely of memristors with M(q) > 0 everywhere admits exactly one solution.
Why This Matters:
The governing equations of an all-memristor network are structurally identical to those of an all-
nonlinear-resistor network, for which uniqueness proofs already exist. The result therefore transfers
directly without requiring a new derivation.
Theorem 4 — Principle of Stationary Action
Statement:
The solution charge vector q of a pure memristor network is a stationary point of the total action
functional A(q):
A(q) = ∫₀ᵂ φ(q′) dq′ [Units: Wb·C]
That is, ∂A/∂q = 0 at the network solution.
Engineering Significance:
• Action A(q) plays a role analogous to energy in resistor network analysis
• Enables variational (energy-minimisation) techniques for memristor circuit analysis
• Predicts that gain scales as frequency² in memristive upconverters
• Implies near-unity efficiency in harmonic generation applications

Theorem 5 — Network Order of Complexity

Statement:
For a network containing inductors (b_L), capacitors (b_C), memristors (b_M), and sources, the
number of independent state variables m is:
m = (b_L + b_C + b_M) − (n_M + n_CE + n_LM) − (n̂ _M + n̂ _LJ + n̂ _CM)
Key Point:
Each memristor contributes exactly one state variable — its charge q or flux φ — to the network, on
a par with each inductor or capacitor. Topological constraints (all-memristor loops or cut-sets)
reduce this count in the standard way.

Theorem One-Sentence Summary Central Physical Significance

Formula/Condition
T1 — Passivity Passive ⟺ M(q) ≥ 0 p(t) = M(q)·i² Physical realisability as standalone
element
T2 — Closure All-memristor network ≡ φ = f(q) preserved under Structural completeness of the
one memristor KCL/KVL memristor class
T3 — Uniqueness Positive M(q) → unique Identical form to Well-posedness of circuit analysis
network solution nonlinear-R proof
T4 — Stationary Solution = stationary ∂A/∂q = 0 Variational analysis framework
Action point of A(q)
T5 — Complexity Each memristor adds m = b_L+b_C+b_M − State-space dimensioning for
one state variable constraints simulation

🎯 Interview Guidance: Theorem 1 is the most frequently tested. If asked whether a

memristor can possess negative resistance, the correct answer is: 'A passive memristor
cannot — M(q) < 0 would make it active, requiring an internal energy source, which
Theorem 1 explicitly forbids. Active memristive circuits can exhibit apparent negative
differential resistance, but they depend on a power supply and are not passive devices.'
⚡ Chapter 3 — Key Takeaways: • T1: Passive ⟺ M(q) ≥ 0 everywhere | p(t) = M(q)·i² • T2:
All-memristor network ≡ single memristor (closure property) • T3: Positive M(q) → unique
network solution • T4: Solution is stationary point of A(q) = ∫φ dq • T5: Each memristor
contributes exactly one state variable
Chapter 4 — Physical Realisation of the Memristor
4.1 The Thirty-Seven-Year Interval
Chua established the memristor's theoretical necessity in 1971. Physical confirmation did not arrive
until Strukov et al. published their findings in 2008 — a gap of 37 years. Several factors account for
this delay:
Factor Explanation
Incorrect search target Researchers anticipated that memristance would involve actual magnetic flux
linkage (misled by the term 'flux-linkage'). It does not — no magnetic field is
required.
Scale mismatch The memristive effect scales as 1/D², where D is film thickness. At micrometer
device dimensions, the effect is negligibly small; only nanoscale geometries (D ≈
10 nm) produce a dominant memristive response.
Instrumentation gap Dedicated φ–q curve tracers were not standard laboratory equipment.
Researchers using conventional v–i oscilloscopes often misclassified the
hysteresis they observed.
Misattribution of Numerous devices — ovonic threshold switches, electrochemical timing cells,
existing devices organic switching films — were memristors in retrospect but were modelled
using other frameworks.

🔬 1/D² Scaling Law: Memristive strength is proportional to 1/D². Reducing device thickness
from 10 µm to 10 nm — a factor of 1000 — amplifies the memristive effect by 10⁶. This
scaling behaviour is the reason the memristor only became experimentally accessible in the
era of nanoelectronics.

4.2 Active Circuit Emulation — Mutators (Chua, 1971)

Prior to identifying a physical device, Chua demonstrated that arbitrary φ–q characteristics could be
synthesised using active two-port circuits he termed mutators. Each mutator type maps a known
element on one port to a memristor on the other:
Mutator Type Transformation Port 1 (presented) Port 2 (physical)
M–R Mutator (Type 1) Converts v–i curve to φ–q Memristor Nonlinear resistor
locus
M–L Mutator Converts (φ_L, i_L) to φ–q Memristor Nonlinear inductor
locus
M–C Mutator Converts (q_C, v_C) to φ–q Memristor Nonlinear capacitor
locus

Chua constructed working Type-1 M–R mutator circuits using operational amplifiers and transistors,
and built a φ–q tracer incorporating analogue integrators to confirm the output experimentally.

4.3 The HP Labs Breakthrough — Strukov et al. (2008)

📰 Primary Reference: D. B. Strukov, G. S. Snider, D. R. Stewart, R. S. Williams, "The missing
memristor found," Nature, vol. 453, pp. 80–83, 2008.
Device Architecture
Layer Material Electrical Character Functional Role
Upper electrode Platinum (Pt) Inert conductor Applied-bias terminal; does not
dissolve
Conducting sub- TiO₂₋ₓ (w nm thick) Conducting Hosts mobile oxygen-vacancy
layer dopants (V⁺⁺O)
Insulating sub-layer TiO₂ ((D−w) nm thick) Insulating Stoichiometric oxide; high
resistivity
Lower electrode Platinum (Pt) Inert conductor Reference terminal

Operating Mechanism
• Positive applied voltage: oxygen-vacancy dopants drift toward the insulating layer →
conducting-region width w increases → total resistance falls → SET state (ON)
• Negative applied voltage: dopants reverse direction → w decreases → resistance rises →
RESET state (OFF)
• Voltage removed: drift force disappears, dopants are immobile → w is frozen → resistance is
retained indefinitely

HP Model Equations
The device is modelled as two sub-layers in series, giving a total resistance:
M(w) = R_ON · (w/D) + R_OFF · (1 − w/D)
The state variable w evolves in proportion to current (linear drift approximation):
dw/dt = (μ_v · R_ON / D) · i(t)
Integrating and applying R_ON ≪ R_OFF yields the charge-controlled memristance:
M(q) ≈ R_OFF · [1 − (μ_v · R_ON / D²) · q(t)]
Parameter Symbol Typical Value Physical Meaning
ON-state resistance R_ON ~100 Ω Resistance when conducting layer spans full
film
OFF-state resistance R_OFF ~16 kΩ Resistance when insulating layer spans full
film
Total film thickness D ~10 nm Combined thickness of both TiO₂ sub-layers
Ion drift mobility μ_v ~10⁻¹⁴ m²/V·s Speed of oxygen-vacancy migration per unit
field
State variable w 0≤w≤D Width of the conducting (doped) region

❌ Model Limitation: The linear drift equation permits w to fall below zero or exceed D, both
of which are physically impossible. In practice, vacancy drift decelerates near the sub-layer
boundaries. Joglekar (2009) and Biolek (2009) introduced window functions that enforce 0 ≤
w ≤ D and reproduce the sharp on/off transitions observed experimentally.

Switching Regime When It Occurs v–i Signature Principal Application

Soft switching w remains well inside [0, Smooth double-loop Analogue computing;
D] hysteresis multi-level data storage
Hard switching w reaches a boundary (0 Abrupt ON/OFF transitions Binary non-volatile
or D) memory (ReRAM)
Switching Regime When It Occurs v–i Signature Principal Application
Apparent NDR w at boundary while Negative-slope region in v–i Dynamic artefact; no static
voltage continues rising NDR

⚡ Chapter 4 — Key Takeaways: • HP TiO₂ device: conducting/insulating bilayer; dopant

boundary position w = state variable • M(w) = R_ON·(w/D) + R_OFF·(1−w/D) • dw/dt = (μ_v
R_ON/D)·i(t) — state changes proportionally to current • Memristive effect scales as 1/D² —
only significant at nanoscale • Soft switching → analogue; hard switching → binary memory
Chapter 5 — Classification of Memristive Devices
5.1 Classification by Switching Polarity
Type SET Voltage RESET Voltage Representative Key Remark
Materials
Unipolar Positive pulse Positive pulse NiO, Fe₂O₃ Both operations require the
(higher amplitude) same polarity; magnitude
distinguishes them
Bipolar Positive Negative TiO₂, HfO₂ Opposite polarities required;
the dominant class in modern
research
Threshold Either polarity Self-resets when VO₂, NbO₂ No persistent non-volatile
(volatile) bias is removed state; deployed as crossbar
selector elements

5.2 Classification by Physical Switching Mechanism

Mechanism Description Representative Retention
Materials
Conductive Filament A nanoscale conducting HfO₂, TaO₂, TiO₂, SiO₂ Non-volatile
(CF) filament nucleates during SET
and ruptures during RESET
Electrochemical Active metal electrode (Ag or Ag/GeSe, Cu/SiO₂ Non-volatile
Metallisation (ECM / Cu) dissolves; ions migrate to
CBRAM) form a metallic bridge
Valence Change Drift of oxygen vacancies alters TiO₂, HfO₂, WO₃ Non-volatile
(VCM) local stoichiometry without
forming a metallic filament
Phase Change (PCM) Joule heating switches active GST (Ge₂Sb₂Te₅), AIST Non-volatile
material between amorphous
and crystalline phases
Ferroelectric Tunnel Reversal of ferroelectric BaTiO₃, BiFeO₃ Non-volatile
Junction (FTJ) polarisation modulates
tunnelling current magnitude
Spintronic Magnetic domain-wall position CoFe/MgO multilayer Non-volatile
serves as the state variable stacks

5.3 Classification by Material Platform

Category Representative Chief Advantage Principal Limitation
Materials
Oxide-based TiO₂, HfO₂, Al₂O₃, NiO CMOS process Cycle-to-cycle variability;
(OxRAM) compatibility; extensively endurance degradation
characterised
CBRAM Ag or Cu with GeSe/SiO₂ Low switching voltage Long-term reliability of Ag-
(~0.2 V) based bridges
Category Representative Chief Advantage Principal Limitation
Materials
Phase-Change GST, AIST Multi-level storage; high High RESET current (power
(PCM) endurance budget concern)
Organic/Polymer PEDOT:PSS, PCBM Mechanical flexibility; Limited switching speed and
biocompatibility long-term stability
Carbon-Based Graphene, carbon High speed; ultralow Complex large-area fabrication
nanotubes power potential
2D Materials MoS₂, h-BN, MXenes Atomically thin switching Still at an early research stage
medium

⚡ Chapter 5 — Key Takeaways: • Bipolar switching = most prevalent class; SET(+) / RESET(−)
• Conductive filament formation = most studied physical mechanism • VCM (oxygen-vacancy
drift) = mechanism in HP TiO₂ model • PCM (GST) = technology base for Intel Optane
products • CMOS-compatible materials: HfO₂, TiO₂, TaO₂
Chapter 6 — Applications of Memristors
6.1 Applications Demonstrated by Chua (1971)
Device Modelling
Chua showed that the amorphous ovonic threshold switch is precisely described by a piecewise-
linear φ–q characteristic, including its onset time delay Td = [Φ₀ + (R₁+R₂)Q₀]/E. Similarly, the
electrochemical E-Cell (Coulometer) was modelled as a memristor, yielding output waveforms that
matched laboratory measurements almost exactly.

Signal Processing
An N-segment φ–q curve driven by a square-wave input produces an N-step staircase output
waveform, enabling waveform synthesis for sampling oscilloscopes. Chua also predicted gain scaling
as f² in memristive frequency upconverters and near-unity efficiency in harmonic generators.

6.2 Non-Volatile Memory — Resistive RAM (ReRAM)

Performance Metric Flash Memory Memristive ReRAM
Write speed ~milliseconds ~nanoseconds (≈ 10⁶× faster)
Write energy ~picojoules per bit ~femtojoules per bit (≈ 10³×
lower)
Endurance ~10⁵ write cycles ~10¹² cycles (target)
Scalability ~10 nm (approaching limits) < 5 nm feasible (two-terminal,
gateless)
Bits per cell 1–3 bits Multi-level: 4+ bits demonstrated
Cell architecture 3-terminal (transistor + capacitor) 2-terminal (crossbar-compatible)

Commercial implementations include Panasonic (HfO₂ ReRAM, 2013), Fujitsu (ReRAM), and Intel
Optane (3D XPoint — PCM-based).

6.3 Neuromorphic Computing

🧠 Why Memristors Are Near-Ideal Artificial Synapses: 1. Conductance G = 1/M(q) is
continuously variable — analogous to graded synaptic weight 2. Non-volatile: learned weight
is stored at zero quiescent power 3. Nanoscale dimensions: millions of synapses fit on a
single crossbar tile 4. STDP: the natural response of a memristor to asymmetric voltage
pulses implements Hebbian learning directly in hardware 5. Energy efficiency: switching
energies down to femtojoules per update

The Crossbar Array Architecture

An N×N crossbar provides the hardware substrate for memristive neural computation:
• Rows carry pre-synaptic input voltages Vᵢ
• Columns carry post-synaptic output currents I_j
• Each crosspoint memristor encodes synaptic weight as conductance G_ij = 1/M_ij
• By Ohm's Law and KCL: I_j = Σ G_ij · Vᵢ — a complete matrix–vector product executed in a
single physical step
 📊 Computational Advantage: A conventional processor requires O(N²) multiply-accumulate
operations executed sequentially to compute I = G·V. A memristor crossbar performs the
entire operation in O(1) time, with all multiplications and additions occurring simultaneously
through the physics of Ohm's Law and Kirchhoff's Current Law.

STDP — Spike-Timing Dependent Plasticity

Condition Biological Effect Memristor Response Learning Term
Pre fires before post (Δt > Synapse strengthens Conductance increases — net Long-Term
0) charge lowers M Potentiation (LTP)
Pre fires after post (Δt < 0) Synapse weakens Conductance decreases — Long-Term Depression
reverse charge raises M (LTD)
Δt = 0 No change No net charge → no change No weight update
in M

Hardware implementation: temporally offset voltage pulses applied to the row (pre-synaptic) and
column (post-synaptic) lines produce a net voltage across the crosspoint device whose sign and
amplitude encode Δt. This net voltage drives a proportional charge update, modifying the
conductance according to the STDP rule.

6.4 In-Memory Computing — Overcoming the von Neumann Bottleneck

Architecture Memory Location Compute Location Data Movement Energy
Fraction in
Transport
Von Neumann (CPU + Off-chip DRAM CPU cores Every MAC traverses ~70% of total
RAM) memory bus system energy
GPU HBM stacked CUDA cores Still physically Improved, but
memory separate bottleneck
persists
Memristor Crossbar In the crossbar In the crossbar Zero movement for Near-zero
itself itself matrix–vector data-transport
multiply energy

❌ Sneak Path Problem: In dense crossbar arrays, unselected memristors provide parasitic
current paths — "sneak paths" — that corrupt the intended matrix–vector product. The
remedy is to place a selector device (diode, threshold switch, or transistor) in series with
each memristor to suppress unintended current flow.

6.5 Additional Application Domains

Application Memristor Contribution Domain Relevance
Physical Unclonable Device-to-device fabrication variation Hardware security, anti-
Functions (PUFs) generates a unique cryptographic counterfeiting
fingerprint
True Random Number Stochastic switching noise provides Cryptography, Monte Carlo
Generators genuine randomness, not algorithmic simulation
pseudo-randomness
Reconfigurable Logic (IMP) Material implication gate: memory Non-von Neumann computing
element is simultaneously the compute paradigms
Application Memristor Contribution Domain Relevance
element
Flexible/Wearable Organic memristors on deformable IoT sensors, electronic skin,
Electronics substrates bioelectronics
Biomedical Interfaces The Hodgkin–Huxley neuron model is Neural probes, brain–machine
provably a memristive system (Chua & interfaces
Kang, 1976)
Analogue Signal Processing Adaptive filters and phase-locked loops Radar, sonar, communications
with intrinsic memory

🎯 Defence Technology Relevance: Memristor applications of direct relevance to defence

research: (1) Low SWaP-C AI inference for unmanned aerial systems; (2) Neuromorphic
processors for radar signal exploitation; (3) PUF-based cryptographic key generation for
secure hardware; (4) Edge AI for autonomous systems operating in communications-denied
environments; (5) Ultra-low-power sensor nodes for persistent border-area surveillance.
⚡ Chapter 6 — Key Takeaways: • ReRAM: write speed ~ns; write energy ~fJ; far superior
scalability vs Flash • Crossbar: I_j = Σ G_ij·Vᵢ — matrix–vector multiply in O(1) via Ohm + KCL
• STDP: pre before post → LTP; post before pre → LTD • Sneak path remedy: series selector
device at each crosspoint • Von Neumann bottleneck: ~70% energy in data movement;
crossbar eliminates this
Chapter 7 — Neuromorphic Computing: A Detailed Study
7.1 The Biological Neuron as Design Blueprint
Component Anatomy Biological Function Hardware Analogue
Dendrites Arborising input Receive signals from Input voltage lines (rows of crossbar)
branches upstream neurons
Soma Cell body Spatiotemporal integration CMOS integrate-and-fire circuit
of all synaptic inputs
Axon Long output fibre Propagates action Output current line (columns of
potential to downstream crossbar)
targets
Synapse Inter-neuron Scales and routes signal; Crosspoint memristor
junction site of synaptic plasticity
Synaptic weight Efficacy of synaptic Determines influence of Conductance G = 1/M(q)
connection pre-neuron on post-neuron

7.2 The Action Potential and the LIF Neuron Model

Biological neurons communicate through brief (~1 ms, ~100 mV) voltage transients called action
potentials or spikes. Three defining properties:
• All-or-nothing: a neuron fires at full amplitude or not at all — no partial spikes occur
• Threshold-gated: firing requires accumulated input to exceed a fixed membrane potential
threshold
• Refractory: a short post-spike period during which the neuron cannot fire again
The Leaky Integrate-and-Fire (LIF) model is the most widely used mathematical abstraction:
C_m · dV/dt = −(V − V_rest)/R_m + I_input(t)
When V reaches V_threshold: neuron emits a spike output, then V resets to V_rest.
Parameter Symbol Biological Referent
Membrane capacitance C_m Capacitance of the lipid bilayer membrane (~1 pF/mm²)
Membrane resistance R_m Resistance to ion leakage through open channels (~10 MΩ)
Resting potential V_rest Equilibrium membrane voltage (~−70 mV)
Threshold potential V_thresh Voltage at which an action potential is triggered (~−55 mV)
Input current I_input Total synaptic current arriving from upstream neurons

7.3 Biology-to-Hardware Mapping

Biological Concept Hardware Implementation Memristor Role
Synapse (synaptic Memristor conductance G = The memristor directly embodies the synapse
weight) 1/M
STDP learning rule Temporally offset voltage pulses Net voltage ΔV drives weight update via net
on row/column lines charge Δq
Neuron soma CMOS integrate-and-fire circuit Sums column currents; generates spike when
Biological Concept Hardware Implementation Memristor Role
(integration) threshold reached
Action potential (spike) Short-duration voltage pulse on Reads current state; drives incremental write
row or column to memristor
Single neural network One N×N crossbar array V_in (rows) → I_out (columns) = G·V matrix
layer product
Multi-layer network Stacked crossbar arrays Each array computes one network layer;
outputs feed next

7.4 Spiking Neural Networks vs. Artificial Neural Networks

Aspect Artificial Neural Network (ANN) Spiking Neural Network (SNN)
Information encoding Continuous real-valued activations Spike timing and rate coding
Computation style Dense matrix multiply at every layer Sparse, event-driven (active only on
spikes)
Power consumption High — computation is continuous Very low — only active during spike
events
Learning algorithm Error backpropagation (offline, batch) STDP (online, local, biologically
plausible)
Optimal hardware GPU (high-throughput floating point) Memristor crossbar (analogue, in-
memory)
Accuracy status State of the art on benchmarks Slightly lower; closing gap rapidly

7.5 Major Neuromorphic Hardware Platforms

Platform Institution Memory Neurons Synapses Distinguishing Feature
Technology
TrueNorth IBM SRAM 1M 256 M 4096 parallel cores; sub-
milliwatt inference
Loihi 2 Intel SRAM 1 M+ 120 M+ On-chip STDP learning;
reconfigurable mesh
SpiNNaker 2 Univ. Manchester DRAM 144 M Billions ARM-core mesh;
entirely software-
configurable
BrainScaleS 2 Univ. Heidelberg Analogue SRAM 512 130 K Runs 10 000× faster
than biological real-time
Memristor HP / Stanford / IBM ReRAM / PCM Custom Custom Memory IS the compute
Crossbar element; no data
movement for inference

🎯 The Memristor Distinction: All CMOS-based platforms — TrueNorth, Loihi 2, SpiNNaker 2

— maintain a physical separation between memory cells and compute units at the device
level. Memristor crossbars are the only platform in which the memory element is itself the
computational element. This is not a quantitative engineering improvement but a
qualitatively different computational architecture.
7.6 Open Challenges in Memristive Neuromorphic Systems
Challenge Description Current Mitigation Strategies
Device variability Resistance distributions spread Statistical training protocols; hardware-aware
cycle-to-cycle and device-to- neural architecture design
device
Sneak path currents Parasitic current flows through 1T1R (transistor + memristor) or 1D1R (diode +
unselected crosspoints memristor) selector structures
Conductance drift Stored resistance drifts at Periodic refresh circuits; redundant coding
elevated temperature or under schemes
sustained bias
Limited analogue Effective weight resolution Mixed-precision training; algorithmic noise
precision typically 4–6 bits compensation
Write endurance Repeated switching degrades Advanced material engineering; wear-levelling
the oxide switching layer controllers
Stuck faults Devices permanently locked in Array redundancy; fault-tolerant weight-mapping
ON or OFF state algorithms

🎯 Interview Question Bank: Q1: "What is the von Neumann bottleneck and how does a
memristor crossbar address it?" A: The bottleneck arises because CPU and DRAM are
physically separate; every multiply-accumulate operation requires data to traverse the
memory bus, consuming ~70% of total system energy. A crossbar stores weights as
conductances and computes dot products through Ohm's Law and KCL — no data
movement occurs during inference. Q2: "What is STDP and why is it hardware-efficient?" A:
Spike-Timing Dependent Plasticity updates a synaptic weight based solely on the relative
timing of pre- and post-synaptic spikes. In hardware, this is purely local information (two
terminals of one crosspoint memristor) — no global error signal or backward pass is
required. Q3: "What is the sneak path problem?" A: Selecting one memristor (row r, column
c) applies voltage to all devices sharing that row or column. Current can flow through chains
of unintended paths to reach column c, adding spurious current that corrupts the dot
product. Series selector devices suppress these paths.
⚡ Chapter 7 — Key Takeaways: • LIF neuron: C_m·dV/dt = −(V−V_rest)/R_m + I_in; fires
when V > V_thresh • Synapse ↔ Memristor; Synaptic weight ↔ Conductance G = 1/M(q) •
Crossbar: I_j = Σ G_ij·Vᵢ — all rows and columns operate simultaneously • SNN + memristor =
event-driven + in-memory → maximum power efficiency • STDP is a purely local learning
rule — backpropagation through the network is not required
Chapter 8 — Master Formula and Reference Sheet
8.1 Core Memristor Equations
Quantity Formula Unit Source
Accumulated charge q(t) = ∫₋∞ᵗ i(τ) dτ Coulomb (C) Definition
Flux-linkage φ(t) = ∫₋∞ᵗ v(τ) dτ Weber (Wb) Definition
Memristance (charge- M(q) = dφ(q)/dq Ohm (Ω) Eq. 2, Chua (1971)
controlled)
Memductance (flux- W(φ) = dq(φ)/dφ Siemens (S) Eq. 4, Chua (1971)
controlled)
Terminal voltage (charge- v(t) = M(q(t))·i(t) Volt (V) Eq. 1, Chua (1971)
controlled)
Terminal current (flux- i(t) = W(φ(t))·v(t) Ampere (A) Eq. 3, Chua (1971)
controlled)
Instantaneous power p(t) = M(q)·[i(t)]² Watt (W) Eq. 5, Chua (1971)
Passivity condition M(q) ≥ 0 for all q — Theorem 1, Chua (1971)
Action functional A(q) = ∫₀ᵂ φ(q′) dq′ Wb·C Theorem 4, Chua (1971)
Network state-variable m = (b_L+b_C+b_M) − Dimensionless Theorem 5, Chua (1971)
count constraints

8.2 HP TiO₂ Device Model Equations

Quantity Formula Unit Physical Interpretation
Total resistance M(w) = R_ON(w/D) + Ω Linear mixing of two series
R_OFF(1−w/D) sub-layer resistances
State variable dynamics dw/dt = (μ_v R_ON/D)·i(t) m/s Boundary velocity
proportional to current
density
State vs. accumulated w(t) = (μ_v R_ON/D)·q(t) m Confirms device is charge-
charge controlled
Charge-controlled M(q) ≈ R_OFF·[1−(μ_v Ω Decreases linearly with
memristance R_ON/D²)·q] accumulated charge
Scaling law Memristive effect ∝ 1/D² Ω Explains why nanoscale
geometry is required

8.3 Neuromorphic Computing Equations

Quantity Formula Physical Meaning
LIF neuron dynamics C_m·dV/dt = −(V−V_rest)/R_m + Membrane voltage integrates input;
I_in(t) leaks toward rest
Crossbar output current I_j = Σᵢ G_ij·Vᵢ Matrix–vector product realised by
Ohm + KCL
Quantity Formula Physical Meaning
Synaptic weight G_ij = 1/M_ij(q) Conductance = reciprocal of
(conductance) crosspoint memristance
STDP rule — LTP branch ΔG ∝ +exp(−|Δt|/τ₊) for Δt > 0 Pre-before-post: strengthen synapse
STDP rule — LTD branch ΔG ∝ −exp(−|Δt|/τ₋) for Δt < 0 Post-before-pre: weaken synapse
Chapter 9 — Pitfalls, Examination Strategy, and Interview
Preparation
9.1 The Ten Most Common Conceptual Errors
Pitfall 1 — φ equals magnetic flux in a coil
Incorrect. In memristor theory, φ = ∫ v dt — the running integral of terminal voltage. No coil and no
magnetic field are involved. The label "flux-linkage" is standard circuit-theory terminology for this
integral and carries no electromagnetic field implication.
Pitfall 2 — Any hysteretic i–v device is a memristor
Incorrect. The necessary signature is a pinched loop that passes through the origin AND collapses to
a line at high frequency. A loop that does not pass through the origin indicates a nonlinear capacitor
or inductor, not a memristor.
Pitfall 3 — Memristance M and resistance R are interchangeable
Both carry units of Ohms, but R is a fixed property (or depends only on instantaneous temperature).
M(q) is a functional of the entire historical current waveform. The instantaneous behaviour looks
Ohmic, but the value of M changes continuously as charge accumulates.
Pitfall 4 — Any two-terminal device showing hysteresis is a memristor
Ferroelectric capacitors, spin-valve transistors, and numerous other devices exhibit hysteresis but do
not satisfy the memristor criteria. The pinch-at-origin and frequency-dependent collapse tests
together constitute the definitive diagnostic.
Pitfall 5 — The linear HP drift model is physically complete
The equation dw/dt = (μ_v R_ON/D)·i(t) permits w to leave the physical range [0, D]. Window
functions (Joglekar 2009; Biolek 2009) must supplement the model to enforce the boundary
constraints and reproduce hard-switching behaviour.
Pitfall 6 — Memristor crossbars are entirely CMOS-free
CMOS circuits are indispensable for integrate-and-fire neuron circuits, peripheral read/write
electronics (ADCs, DACs), and series selector devices. Memristors replace only the synaptic weight
storage and the multiply-accumulate computation.
Pitfall 7 — STDP is equivalent to backpropagation
STDP is a local rule that depends only on the timing of two spikes at one synapse. Backpropagation is
a global algorithm requiring an error signal to be propagated backward through all layers. STDP is
biologically consistent; backpropagation is not.
Pitfall 8 — Negative differential resistance equals negative memristance
NDR in hard-switching memristors is a transient dynamic effect: it occurs when w reaches a physical
boundary while the applied voltage is still rising. At DC, the effect disappears. True static NDR would
require M(q) < 0, violating Theorem 1 and implying an active device.
Pitfall 9 — Larger crossbar arrays are strictly better
Sneak-path interference grows with array size. A 1000×1000 crossbar exhibits far worse parasitic
currents than a 10×10 one. Practical high-density designs require hierarchical tiling with peripheral
isolation circuits.
Pitfall 10 — Chua (1971) discovered the physical memristor
Chua predicted the memristor's necessary existence from mathematical symmetry in 1971. The
physical realisation — the HP TiO₂ device — was reported by Strukov et al. in 2008, thirty-seven
years later. The 1971 paper is theoretical; the 2008 paper is experimental.

9.2 Ten Model Examination Questions

🎯 Q1: Define the memristor and distinguish it from a resistor. Answer: A memristor is a
passive two-terminal element whose resistance is determined by the cumulative charge that
has flowed through it and is retained when current ceases. A resistor has a fixed, time-
independent resistance; memristance M(q) varies continuously with charge history.
🎯 Q2: State and prove the passivity criterion. Answer: A memristor is passive ⟺ M(q) ≥ 0 for
all q. Proof: p(t) = M(q)·[i(t)]². M ≥ 0 → p ≥ 0 → passive. M(q₀) < 0 → construct input holding
q ≈ q₀ → p < 0 → energy generated → active. □
🎯 Q3: Explain why memristance is significant only at the nanoscale. Answer: The memristive
effect scales as 1/D². Reducing film thickness from 10 µm to 10 nm — a factor of 1000 —
amplifies the effect by 10⁶. At micrometer dimensions the effect is swamped by normal
resistance; only nanoscale geometries make it dominant.
🎯 Q4: Describe the sneak path problem and its engineering remedy. Answer: Selecting
crosspoint (r, c) places bias on the entire row r and column c. Current flows through chains
of unselected memristors that happen to share row r or column c, reaching column c via
indirect routes and adding spurious current. Remedy: a 1T1R (transistor+memristor) or 1D1R
(diode+memristor) cell structure blocks unintended paths.
🎯 Q5: Describe STDP and its hardware implementation in a memristor crossbar. Answer:
STDP dictates that synaptic weight increases when the pre-synaptic neuron fires before the
post-synaptic neuron (LTP, Δt > 0) and decreases in the reverse case (LTD, Δt < 0). In
hardware, temporally offset voltage pulses on row and column lines produce a net voltage
across the crosspoint memristor proportional in sign and magnitude to Δt, driving a
corresponding change in conductance.

9.3 Comparative Summary: Chua (1971) vs. Strukov et al. (2008)

Dimension Chua (1971) Strukov et al. (2008)
Methodology Axiomatic mathematical reasoning Physical device modelling and
from circuit symmetry experimental characterisation
Device realised Active circuit emulation using op- Passive TiO₂ thin-film device (~10 nm
amps and transistors thick)
Primary state variable Accumulated charge q and flux- Dopant-boundary position w (nm)
linkage φ
Governing equation v = M(q)·i; M(q) = dφ/dq M(w) = R_ON(w/D) + R_OFF(1−w/D)
Physical mechanism General / mechanism-agnostic Valence change (VCM) — oxygen-
vacancy ionic drift
Operating scale Macroscopic (centimetre-scale Nanoscale (D ~ 10 nm film thickness)
circuits)
Applications demonstrated Ovonic switch modelling, E-Cell, Nanoscale non-volatile memory,
staircase waveform synthesis, neuromorphic computing foundations
frequency conversion
Legacy Provides the complete theoretical Physical validation; resolved ~50 years
Dimension Chua (1971) Strukov et al. (2008)
framework for memristors of unexplained switching phenomena

9.4 Analogy Reference Sheet

Memristor Concept Explanatory Analogy
M(q) depends on charge history A suntan: today's skin tone reflects the entire accumulated history of sun
exposure, not just today's irradiance
φ–q curve vs. v–i curve A biography vs. a current snapshot: same person, radically different
temporal perspectives
Pinched hysteresis loop A spring with internal friction: the extension path differs from the
compression path, but both cross the neutral (zero-force, zero-
displacement) point
High-frequency loop collapse Shaking a dense suspension too rapidly: the particles cannot redistribute
fast enough and the fluid appears uniform
Crossbar matrix multiply 1000 cashiers totalling 1000 receipts simultaneously vs. one cashier
processing all 1000 sequentially
STDP learning rule "You receive credit for the prediction only if you committed to it before
seeing the outcome" — timing determines causality
Sneak path problem A municipal water network where opening one valve inadvertently draws
pressure from every other connected valve
Chapter 10 — Study Roadmap and Essential Literature
10.1 Four-Week Internship Study Plan
Week Days Subject Matter Measurable Outcome
Week 1 1–2 Circuit variables; symmetry Articulate why the fourth element must exist;
argument for the fourth element; derive M(q) from first principles
introduction to Chua (1971)
Week 1 3–4 Theorems 1–5 with derivations; φ–q Prove passivity criterion; explain frequency-
curve geometry; frequency dependent loop collapse mechanism
dependence of hysteresis loop
Week 1 5–7 Semiconductor physics; diffusion; Understand the TiO₂ device at the materials-
oxide defects and point defects science level
Week 2 1–2 HP TiO₂ device: structure, governing Derive M(q) ≈ R_OFF[1−(μ_v R_ON/D²)q] from
equations, state-variable dynamics the bilayer model
Week 2 3–4 Resistive switching categories; Compare VCM, ECM, and CF mechanisms;
hard/soft switching regimes; window explain need for window functions
functions
Week 2 5–7 Material classification: OxRAM, Reconstruct comparison table from memory
CBRAM, PCM, FTJ, spintronic without reference
Week 3 1–2 Biological neuron anatomy; synaptic Map each biological element to its memristor
plasticity; STDP; Hebbian learning crossbar counterpart
Week 3 3–4 LIF neuron equations; spiking neural Derive the crossbar dot-product formula;
networks; crossbar array simulate LIF response
architecture
Week 3 5–7 Neuromorphic platforms; von Compare TrueNorth vs. memristor crossbar on
Neumann bottleneck; in-memory key metrics
computing paradigm
Week 4 1–2 ReRAM vs. Flash comparison; PUFs; Reproduce ReRAM vs. Flash comparison table
stochastic computing applications from memory
Week 4 3–4 Active research frontiers: variability, Identify and explain the top three open
endurance limits, sneak paths, 3D engineering challenges
integration
Week 4 5–7 Prepare a 15-minute research Achieve fluent, unprompted oral explanation
presentation; practise all ten of all ten chapters
interview questions aloud

10.2 Essential Reading List (Priority Order)

Priority Reference Reason to Read Key Intellectual
Contribution
1— L. O. Chua, "Memristor — The missing Primary theoretical Symmetry argument;
Essential circuit element," IEEE Trans. Circuit source; all subsequent formal definition; five
Theory, vol. 18, no. 5, pp. 507–519, memristor theory traces theorems; mutator
1971 to this paper circuits
2— D. B. Strukov et al., "The missing First passive physical TiO₂ bilayer model; 1/D²
Priority Reference Reason to Read Key Intellectual
Contribution
Essential memristor found," Nature, vol. 453, pp. device; most-cited scaling law; resolution of
80–83, 2008 memristor paper in the 37-year gap
literature
3 — High L. O. Chua and S. M. Kang, "Memristive Generalises to the Proves Hodgkin–Huxley
devices and systems," Proc. IEEE, vol. broader class of neuron model is
64, no. 2, pp. 209–223, 1976 memristive systems memristive; broader
device taxonomy
4 — High Y. N. Joglekar and S. J. Wolf, "The Exposes linear drift- Boundary constraints;
elusive memristor," Eur. J. Phys., vol. model limitations; window-function
30, p. 661, 2009 introduces window formalism; hard-
functions switching dynamics
5 — High Z. Biolek et al., "SPICE model of Provides SPICE- Practical simulation
memristor," Radioengineering, vol. 18, compatible circuit workflow for memristive
no. 2, 2009 simulation model circuits in standard EDA
tools
6— S. H. Jo et al., "Nanoscale memristive First experimental Biological learning rule
Medium devices for memory and logic," Nano demonstration of STDP realised in hardware at
Letters, vol. 10, no. 4, p. 1297, 2010 in a nanoscale the nanoscale
memristor
7— G. W. Burr et al., "Neuromorphic Best comprehensive Full landscape of device
Medium computing using non-volatile memory," review of NVM-based options, array
Adv. Phys.: X, vol. 2, no. 1, p. 89, 2017 neuromorphic architectures, and
computing training algorithms
8— M. A. Zidan et al., "The future of Forward-looking Open engineering
Medium electronics based on memristive roadmap of the field challenges; system-level
systems," Nature Electronics, vol. 1, p. integration; co-design
22, 2018 opportunities

10.3 Ten Questions to Answer Before Meeting Your Research Guide

• 1. Why did Chua predict the memristor from symmetry alone? Reconstruct the six-pair
argument in full.
• 2. Derive M(q) = dφ/dq from first principles and provide a physical interpretation of each
symbol.
• 3. State Theorem 1 (Passivity) and provide a rigorous three-step proof. What does violation of
the criterion imply physically?
• 4. Describe the HP TiO₂ device layer structure and derive the state evolution equation dw/dt =
(μ_v R_ON/D)·i(t) from ionic drift physics.
• 5. Show mathematically why the memristive effect scales as 1/D² and explain why this
restricted its discovery to the nanoelectronics era.
• 6. Derive the crossbar matrix–vector product I_j = Σ G_ij·Vᵢ from Ohm's Law and Kirchhoff's
Current Law. State the computational complexity advantage.
• 7. Define STDP. Trace each step of its hardware implementation in a memristor crossbar from
spike timing to conductance update.
• 8. Explain the von Neumann bottleneck quantitatively. Show how in-memory computing
eliminates the dominant energy cost.
 • 9. Describe the sneak-path problem with a worked example for a 3×3 array. Evaluate two
engineering remedies.
• 10. Compare Chua (1971) and Strukov et al. (2008) across methodology, scale, device type,
governing equations, and scientific legacy.

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