Chapter 2

A Perspective on the Evolution of Analog Bench Validation

and Characterization
SOC designers understand that at arrival of first silicon some unexpected errors will come
that need to be taken care of. The errors are attributed to complex and sophisticated
subsystems of interconnected systems. Another source of errors arises from power system
or a clock. They can result from synchronization errors, crosstalk noise or process, voltage
and temperature (PVT) as well. They can even lead to an unexpected interaction between
hardware and software.

Silicon validation of a modern processor design encompasses testing the interacting

components in the embedded software. The post-silicon validation phase mainly consists
of logic and electrical validation and software debug. It is important to note that in silicon
validation [7], examining the chip efficacy with its ability to work at specified speed under
different operating conditions is always paramount. Ignoring the chip efficacy may lead to
catastrophic failure in real time applications. Debug of silicon failure is to find the cause of
a malfunction whenever the design is not working as per desired functionality. The first
debugging of silicon validation requires intensive engineering efforts of several months.
The difficulty of silicon validation process increases with reduction in technology length
(below 28nm).

The purpose behind post-silicon validation is to ensure the usefulness of design

functions, discover any sort of issues which is inhibiting silicon to work as per
specification, root cause the issue and get it fixed by design or through software settings.

In SoC design flow, silicon validation is the last phase after which silicon enters the real-
world applications. It consist of mainly digital validation (for digital portion of integrated
circuits), analog bench validation (for digital signal having analog nature & mixed and pure
analog signal of integrated circuits [8]), automatic test equipment (manufacturing Testing,
wafer probe) and system validation (for application level testing) . In semiconductor
 Chapter 2 A Perspective on the Evolution of Analog Bench Validation and
Characterization

industry post silicon validation team comprises of digital, analog bench validation, system
validation and ATE team. Hence, many organizations rely on analog bench validation [9].

Fig. 2.1: Post Silicon Validation

Lots of research in the field of silicon validation has been done and a lot is in progress.
These researches have been mainly done for digital validation section of silicon flow where
researchers focus on logic validation of silicon. Previously, digital and analog integrated
circuits were manufactured separately but now mixed signal SoC/IPs are maturing rapidly.
Mixed signal SoC/IP includes digital as well as analog portion on same SOC/IP. So, analog
bench validation is also crucial in silicon flow. In Fig. 2.1, it can be seen that SoC validation
(PostSilicon Validation) is mainly divided in to digital validation [10] for functional bug
hunting, automatic test equipment (ATE) for manufacture bugs, full volume testing, analog
bench validation for characterizing the analog nature of digital signal as well as analog IP
validation and system validation for application level testing. For the SoC technologies
involving high speed coupled with high level of integration & scaled technologies,
detecting and fixing bugs completely via verifications, automatic test equipment (ATE) &
digital validation become formidable task. Every mixed design circuit goes through
electrical validation steps. The digital validation engineer ensures that this complex design
functions properly in all specified cases. Embedding an analog design into a digital system
and subsequently, its validation is quite difficult. That opens up a new research opportunity.

Analog bench validation is crucial because digital validation alone is inadequate. Digital
validation is incapable of detecting analog/electrical bugs that appear in pure analog signal
IPs. Furthermore, complex System-on-Chips (SoCs) integrates multiple digital processor
cores, co-processors/accelerators, mixed signal IPs including high-speed serial interface,
significantly complicate analog bench validation [11]. Analog bench validation entails

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manufactured chips with digital and analog IPs in real application environments to validate
anticipated behaviors beneath specified running conditions. The objective is to make
certain annihilation of bugs. Numerous semiconductor enterprises reveal that analog bench
validation and characterization are extraordinarily difficult in nature and expensive. The
dilemma is attributed to reality that existing techniques cannot address the sheer complexity
of forthcoming systems.

However, above discussion concluded that analog bench validation (ABV) and other
domains of silicon validation ecosystem are having correlation with each other. In post-
silicon validation ecosystem, all components and their interactions which influence analog
bench validation are crucial (please see in Fig. 2.2). This multi-component/domain
interaction is the driving force for evolution of analog bench validation. For this reason, we
believe that it is imperative to survey of ABV. Furthermore, it gives us an opportunity to
evaluate ABV in the context of overall post-silicon validation flow. Thus, we analyzed the
major challenges of ABV , investigation on the recent state-of-the-art work of analog bench
validation & characterization with future research direction.

This work, to the best of our knowledge, is first such work explaining the validation
ecosystem and assessment of factors contributing to evolution of analog bench validation.
In this chapter, we intended to present a thorough analysis of work done in the area of post
silicon validation and present the post silicon ecosystem in a top down manner describing
all components and their interactions which influence analog bench validation with current
research thrust. It was also an attempt to evaluate flow of ABV in SOC/IP design flow and
its major challenges. It was also described the analysis on recent state-of-the-art work of
analog bench validation & characterization, with forthcoming research opportunities. The
contribution of this chapter are categorized in different sections, as delineated below. In
sections 2.1, opportunities for analog bench validation in the context of overall post-silicon
validation flow. Section 2.2 discusses the detailed flow of analog bench validation in
SOC/IP design flow and its major challenges. In Section 2.3, investigation on the recent
state-of-the-art work of analog bench validation, characterization, and forthcoming
research opportunities in this field are discussed. Section 2.4 provides a conclusion to this
article.

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2.1 Scope of Analog Bench Validation

This section attempts to describe the overall validation landscape through Fig. 2.2. It
derives the scope of analog bench validation under the influence of different validation
platforms.

Analog bench validation (ABV) has many unique challenges. Research in the field of
analog bench validation is inspired by the techniques used in every domain of post-silicon
validation flow (Fig. 2.2). Opportunities for analog bench validation in the context of
overall silicon validation flow and its comparative assessment with respect to other forms
of validation will be discussed in detail in this section. Fig. 2.2 describes different validation
domain that may exist in the validation flow of semiconductor organizations. Interrelation
of these domains with analog bench validation can be clearly seen. These domains
mentioned in Fig. 2.2 have their own advantages and disadvantages. We will describe the
opportunities for analog bench validation reference in the overall context of these domains.
Association of other forms of silicon validation with analog bench validation results in a
highly interdependent validation system. Analog bench validation seems to be an important
area where interesting opportunities for important innovations exist. Growth in different
sub area of post silicon validation, as shown in Fig. 2.2, will eventually lead to research
opportunity in analog bench validation.

Wafer Testing (WT) succeeds semi-conductor device fabrication [12]. Prior to the WT,
the die preparation is achieved. In this process, all ICs embedded with the wafer are tested
for flawless functional features. This involves special test patterns to them [13].
Semiconductor device scaling with high level of integration leads to greater cost of
manufacturing test. The higher test cost leads to the greater product cost of ICs. The cost
of product is one of the main deciding factors in the client electronics marketplace. The
next major contributor to the product price of SoC design is packaging. In one of the
techniques, known as wafer sort, the packaging cost and the test cost for packaged chips
can be minimized by adopting advanced powerful wafer testing. The development of a
reference wafer for on-wafer testing of extreme impedance devices could be a potential
area of research. At wafer level, setup frequency is not high. Therefore, scan testing is
performed usually at wafer levels. In this domain of silicon validation, static parameters

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Fig. 2.2. Analog Bench Validation in the context of overall Validation Framework

and leakage current are checked. So, this is the first level of testing in which wafer is
categorized as pass or fail. It does not go to block level testing.

Automatic Test Engineering (ATE) [14] is one of the popular methods to detect the
manufacturing bugs. These bugs may have analog behavior but ATE has several limitations
i.e. it can run only pattern based stimulus. So, silicon bugs also arise due to subtle
interactions between silicon components.

The Silicon component interaction arises from physical effects (due to parametric
characteristic of analog IPs) or by design errors (logic or functional bugs).

It is well known that ATE testing is done by loading patterns into the device under test
(DUT). These patterns do not have software level capability of exercising/handshaking the
subblocks of DUT. ATE testing is always subpar to application level testing. It takes level

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of design and validation one step above wafer level testing but not as much as analog bench
validation and application level testing due to inherent limitations. The test metrics such as
single-stuck-at coverage, transition fault coverage and N-detect coverage (pattern based)
are responsible for the success of the ATE testing. Better understanding of the effectiveness
of metrics for actual chips can be obtained from the experimental demonstration by Ma et
al. [15]. Automation of test pattern generation and fault simulation where the stimulus is
borrowed from design verification is empowered by such statics.

The primary objective of ATE testing is to identify errors that adopt similar patterns as
in pre-silicon verification. On the other hand, the major tasks of analog bench validation
are localizing, root-causing the design bugs, as shown in the analog bench validation flow
section of the chapter. This generally dominates design effort and costs [16]. The defect
diagnosis techniques ascertain bug localization. These strategies rely on scan design for
testability (DFT) that allows a sequential circuit, a sort of a combinational circuit in test
mode. ATE based method of bug localizations are not applicable to analog bench
validations. This can be seen as a new opportunity for analog bench validation.

As mentioned above, ATE based testing for detecting the analog bugs is very costly
whereas bench setup used in analog setup is much cheaper for localizing the bug, detecting
and fixing the same. Digital validation has cheaper setup but it is unable to detect the
bug/issues that arise due analog or mixed signal design.

Undetected analog/mixed-signal design bugs in silicon are increasing due to

unprecedented levels of device integration with scaling technology. For high performance
integrated circuits, in addition to these functional issues, there will be yield related issues
such as maximum frequency of operation. These errors occur under special operating
conditions for system on chip. It is hard to predict their effects. Stochastic test stimulation
generation algorithms are an ongoing research topic that deals with fault detection and
diagnosis in the traditional test generation for manufacturing. This provides new
opportunities to explore more as the nature of the design bugs are quite unpredictable [17].

ATE mainly measures the static parameters in expose/standalone mode. This testing is
done at post-package silicon. Some of the performance parameters ADC ENOB, phase
noise of clock signal and the measurement of the eye diagram are left for analog bench

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validation. ATE setup has inherent limitations since ATE test circuit board setup or
instrumentation setup is not at par with application level setup. ATE test circuit board is
different from customer application board setup. Apart from this, each of the end customer
application setups may be different from ATE setup.

Further, analog bench validation research is inspired from the ATE success in post-
silicon validation flow. The test engineer stimulates the device in a repeatable pattern. In
most likely cases, the technique used will a vector loop. To perform the same, test engineer
has to interface the optical probe to the imaging systems. To ensure accurate reproducible
results, close synchronization between the two systems is essential [18]. The DUTs internal
device behavior will be observed using the numerous evaluation techniques. A wide variety
of ATE test methods can benefit analog bench validation. Few examples of ATE methods
are fault simulation, coverage estimation, Power supply impedance emulation and Mixed-
signal ATE technology. Impedance emulation of power supply is to abolish the overkills
and under kills because of impedance mismatch between ATE [14], and customer board.
Further effort has been put to bridging Validation and Automatic Test Equipment
Environment [19]. Some of these developments in ATE research can immensely benefit
analog bench validation.

Boundary Scan Testing is a method for interconnections to test circuit boards or sub-
blocks in an integrated circuit [19]. The boundary scan analysis is a test methodology of
characterizing I/O and is also helpful in debugging. It monitors the states of the integrated
circuit pins to measure the voltage or analysis of the sub-blocks in an integrated circuit
[20]. Boundary scan test is a standalone testing of Input and Output, but it lacks some of
the implementations like validating the characteristics of IO and interoperability. Despite
limitations associated with boundary scan test, analog bench validation research is
motivated from boundary scan testing usefulness in post-silicon validation flow stage.
Testing of high-speed I/Os has been a potential challenge in the past for device testers.
However, cost and the quality is still a restriction for I/O testing. To overcome these
challenges, a number of DFT methods are available in literatures [21], [22]. The eminent
and frequent approach to testing serial transceivers hinges on the loopback principle (details
given section IV). With this we can avoid the expensive high-speed and high pincount
device, while testing the transceiver functionality [23]. Challenges are greater and

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formidable for conventional scan testing method [32]. That stems from speed and non-
determinism of serializer and de-serializer (SerDes), [33].

In the design of the SoC, hardware Emulation Testing is the process of mimicking the
behavior of the DUT hardware with another hardware model. The emulation model exploits
hardware description language source code, e.g. Verilog, which is compiled in the format
supported by the emulation system. The goal is usually a designed debugging and a
functional review of the system [24]. Hardware emulation combines the programming
flexibility of the simulators with the performance and system integration advantages of a
hardware model. The hardware emulation makes it possible to run ASIC designs in a
complete system environment that operates at reduced frequencies. Thus, we can debug the
design before it is released on silicon and start the software development on the overall
system much earlier in the development cycle [25].

As discussed above, the emulation testing section in validation flow only checks the
functionality of digital logic in which no analog logic/block is used. Verilog/VHDL are
imported in hardware, which contains only digital section of SOC. Software initialization
and configuration of analog logic portion can be checked only to the extent that digital
connectivity & analog digital interface functionality are correct (that too at lower
frequency). This greatly helps in the bring up of analog bench validation setup since
configuring an IP in complex SoC can be a time-consuming task.

Digital Validation measures logic functionality through Register Information in RM

(Reference Manual document). RM is treated as the golden reference for register
information. The tests followed are specific to register memory map i.e. register reset test,
register Read/Write test, functional test etc. In digital level testing, generally FPGA-based
and logic analyzer-based testing are performed. The read/write on register content is also
performed. The status of pins is checked for verifying the functionality or electrical
characteristics of SoC. Digital functional validation is done on a special design test board,
which can be used to replicate end user application by using scripting environment i.e.
python, tcl running on hardware and most likely in application type scenario. This is,
however, one step below (Fig.2.2) the level of testing done in software bring-up.

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Digital validation cannot be the only criteria for signing off the design bugs left after
pre-silicon design verification. Digital validation is one step above emulation as it is
working on actual customer board (Fig. 2.2). Digital validation is useful for detecting the
bugs for SoCs having pure digital component. The primary scope of digital validation is to
test the FSM (Finite State Machine) in data path. In many test scenarios, analog portion is
bypassed in digital validation, thereby limiting the coverage of validation. Moreover, all
the chips interacting with other chips happen through high speed I/Os (USB, DDR, SATA,
PCIe etc.) and through data converters and amplifiers. In a complete test setup, both analog
and digital components need to be used together.

Despite the limitations of digital validation, analog bench validation research is derived
from digital validation. If we account for the journey from a theoretical concept to industrial
practice, digital validation concepts, e.g. bug detection, localization and root causing have
become more in-depth. More development in the direction of failure reproduction and
techniques to recreate failures are given in [26], [27]. Further development for error
detection is done in [28]. IFRA (Instruction Footprint Recording and Analysis) technique
is most efficient with 90 percent accuracy to handle bugs for processor cores. Real time
response data can be used for efficient failure intimation and root cause analysis. This offers
the enhancement of observability in digital validation. In the digital validation, one of the
common approaches to debug is on-chip trace buffers [29]. Even the formal assertions from
the simulation traces can be used in scalable manner [30]. This can effectively be used to
locate errors (because of bugs) at module boundaries.

For detecting a problem using assertions, authors in [31]have proposed an in-system

hardware validation and debugging. To filter out state deviation from post-silicon digital
validation, a well-known technique called the latch divergence analysis is popular.
Information stemming from these filtered out states can be processed using modified back
trace procedure for root cause identification. Number of updates have been done in quick
error detection with fast runtime for effective pre-silicon and post-silicon digital validation.
Once, a bug is localized, analyzed, and root caused, one can attempt to patch the problem
in the design itself without re-spin. Microcode patches or special design techniques such as
field repairable control logic is commonly used for microprocessor [32]. Another approach

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called FogClear enables post-silicon metal fixes allowed by engineering change order
(ECO) routing or spare cell insertion.

Traditionally semiconductor industry was dependent upon ATE testing and Digital
Validation for electrical testing of hardware bugs. However, it is seen that such validation
cannot capture high performance analog issues due to setup limitation. Analog bench
validation supplements this and provides better way of encountering these analog issues.

Notably, System Level Testing is one of the important parts of validation flow.
Software or hardware system testing is performed on a complete integrated system that
verifies compliance with specific system requirements. The Test System is in the black box
testing range with no knowledge of the internal design of the code [33]. Halder et al. [34]
have reported efficient manufacturing test methods of transceiver systems at system level.
System level testing is done on the application level board. Generally, software compliance
tests are run at operating system and application levels (windows HQL testing, File zone
testing etc.). The debug challenge in system level testing is that if anything fails at this
stage, then it could go to any of the software or digital or analog bench validation for
debug. The debug may percolate to analog bench validation [35-38].

Failure Analysis involves collecting and analyzing data that determine the cause of the
error, often to determine the corrective action or responsibility [39]. Its relies on physical
technique to alter the material characteristic of DUT to analyze change in performance, i.e.
LADA technique [40], where the speed of transistor can be increased or decreased to see if
the failure is modulated with the altered device. This technique scans all the transistors of
the chip to find the failure impacting device. Failure analysis is generally done on a good
and bad/marginal sample. This is done to establish the root cause.

A sequence of methods applied to failure analysis in a millimeter-wave system-in-

package [41] presents an interesting perspective for analog validation. The association of
failure analysis with other validation domains can be seen in Fig. 2.2. Failure analysis
attempts to establish the root cause at transistor and interconnect level.

This section has so far described the different domains of SoC silicon validation, along
with opportunities for analog bench validation. Hereafter, few validation scenarios are
presented, which are done exclusively using analog bench validation.

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The high speed serial interface controller and PHY are used in the communication
system, that is, DDR, SATA, PCIe, USB, Ethernet, MIPI, HDMI, etc., which use super
high speed data transfer rate with external devices..

Legacy testing on ATE is to follow the internal and external loopback testing. However,
these loopback/BIST methodologies may have limitations in ATE environment. To create
ISI type jitter [42], printed circuit board (PCB) traces [43] are used in loopback. But that
does not account for a proof of clock and data recovery (CDR) stress test. The PCB traces,
equivalent filters of the cable to stress the receiver, have also proven useful. In PCB trace
method, it is hard to control and quantify the ISI jitter[44]. Even layout restriction will play
a vital role. At CDR test coverage, only loopback functional testing is not sufficient. As a
result of this, the devices with marginal performance could escape production test. This
causes system level failures at the customer end. Thus, debugging in customer system and
the supplementary cost are obviously very high.

Therefore, analog bench validation is extensively used to qualify the silicon samples on
real application boards as well as some internal engineering boards for signal integrity
related concerns. Potential problems that can be debugged through analog bench validation
over other form of silicon validation:

• Power supply fluctuation impacting the design (chip power supply pins tend to
have ripple and noise constraints in frequency domain).
• Impact of clock jitter on phase lock loop (PLL), Digital logic.
• Clock pulse-position modulation (PPM) [45] causing failures.
• Crosstalk between signals.
• Clean reference voltages and currents for chip operation i.e. bandgap voltage
[46], bias current [47] etc.
• Analog IP’s malfunctioning may lead to digital/software malfunction.

The above discussion reveals that basic research fueled considerable advances in the
structured methods for Automatic Test Engineering (ATE) testing and digital validation.
With the increasing complexity of SoC silicon validations, it is envisaged that new ideas
will transform the analog bench validation with novel structured validation methods and

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design automation. Above mentioned new techniques have a much wider influence in
different areas associated with analog bench validation.

Analog quantification is a costly affair as equipment required to measure the parameters

are available from limited vendors with a high cost and is largely dependent upon functional
software stack for that interface. As of today, none of the vendors nor the interface
consortium provide end to end automatic solution for carrying out analog bench validation
and characterization. There is ample opportunity in this space to go for unification,
automation and low-cost solution. For example, spectral analysis support is missing in
USB2.0 compliance test suit.

2.2 Analog Bench Validation: Overview & Major Challenges

This section provides an overview of analog bench validation flow and describes various
challenges. Part A of this section describes the collateral involving analog bench validation
in terms of document, equipment and IPs, while part B of this section describes the
challenges which come from semiconductor technology (device corner), use cases, PCB
environment (signal integrity), and test setup limitations.

2.2.1. Analog Bench Validation Flow: An Overview

Analog bench validation and characterization is the process of quantifying the electrical
capabilities and characteristics of a given device through data captured by a series of tests
carried under different conditions such as process, voltage, temperature and frequency,
which are required for analog IPs.

Analog bench validation characterizes the device to ensure that the actual electrical
performance is as per the device specification (e.g. datasheet). The parameters
characterized are Rise/Fall Timing, differential O/P voltage swing, common mode voltage
for differential pads, output skew between clock and data, VOH, VOL, VIH, VIL, pull
up/down current, Jitter measurement for clocks, FM performance, relock timing, min/max
voltage-controlled oscillator (VCO) range, in case of phase lock loop, low voltage
differential (LVD) I/O [48], power on reset (POR) [49], Low power current measurements,
etc.

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Analog bench validation involves the testing of circuit characteristics using various
equipments i.e. arbitrary waveform generator (AWG), oscilloscope, BERTscope, time-
domain reflectometer (TDR), spectrum analyzer (based on differential analyzer [50]) and
multimeter in the testing laboratory environment. This activity has some level of
automation for test and measurement. However, there are always some manual steps. This
testing is also done on high-speed signal integrity boards or customer boards. Analog bench
validation is flow used by test engineer, researcher and design engineers.

The new generation SoCs have large number of analog IPs, that requires extensive
analog bench validation due to stringent performance requirement. A representative list of
the IP includes analog to digital converter (ADC), digital frequency Synthesizer (DFS),
IRC oscillator, PLL, Crystal Oscillator, Voltage regulator, parametric measurement unit
(PMU), frequency lock loop (FLL), double data rate synchronous dynamic random-access
memory (DDR-II SDRAM), DDR-III and DDR-IV, universal serial bus (USB 2.0), super
speed USB3.x, Peripheral Component Interconnect Express (PCIe), Serial Advanced
Technology Attachment (SATA). This includes temperature sensors, Pulse Width
Modulator (PWM), Digital to Analog Converter (DAC), Power Management Controller
(PMC), input outputs (IOs) (LVCMOS, LVDS, HCSL, GPIO etc.), Controller Area
Network (CAN) interface, Mobile Industry Processor Interface (MIPI) and Ethernet.

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Silicon qualification of the analog IP is the availability of the tested product at the end
of the analog bench validation as per product output reference point (PRQ) notation [78].
A complete diagram from SoC/IP design to analog validation & characterizations is given
in Fig. 2.3.

Fig. 2.3: Analog Validation Debug Flow [Curtsy to NXP Semiconductor]

Analog validation & characterization involves three major activities for functional and
parametric testing of any complex SoC.

1. Test programs are used at bench setup with test environment for finding issues as
per analog data sheet. These test programs start with random test instruction and
goes to end user application until failure occurs [7].
2. Localizing the problem in the neighborhood and thenroot-cause analysis. i.e., a bug
may arise due to power-supply noise, slowing down other circuit rails that affects
the output of some design blocks for a particular input sequence [7].

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Fig. 2.4. SoC/IP Design to Analog Validation & Characterization Lifecycle

3. These bugs can be resolved using the micro code patcheswith workarounds, some
board level reworks and trace level editing (Focused Ion Beam edit). If possible,
sometimes one can sidestep with the logic level workarounds. Otherwise, it is
needed to go with the silicon re-spin as a last solution [7].

Detailed flow of analog bench validation is given in Fig. 2.4. For developing the
compressive test plan for analog bench validation, data sheet, reference manual (RM) along
with protocol specification are taken as inputs. Digital validation takes RM and some
scenarios from protocol as primary input. Digital validation setup requires evaluation board
(EVB), compiler, debugger and protocol analyzer for executing the scenario (validating of

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functionality), whereas analog bench validation requires special designed board i.e. high-
speed signal integrity (HSSI) and equipment such as oscilloscope, BERT scope, arbitrary
waveform generator (AWG) etc. for validating the electrical parameters specified in data-
sheet.

2.2.2 Major Challenges Of Analog Bench Validation

Complex performance requirements of the product and the shrinking time-to-market

keeps enormous pressure on the analog bench validation. Even the higher circuit gate count
also adds to it. Because of all of the above, analog bench validation engineer needs
continuous update on methodologies and equipments to meet the adaptive validation tasks.
This helps to provide the economical and swift validation solutions to the issues faced. In
analog bench validation, generally problems/bugs are hidden and unknown. There are many
challenges in analog bench validation. In this section, we will highlight some these
important elements.

1) Identify Worst Corner For Finding Problem or Bugs::

Each silicon has various device types viz. PMOS, NMOS, BJT, resistor, diode, etc.
Further the PMOS, NMOS devices can have different voltage ratings on the same chip.
These voltage rating can be classified as core voltage, which includes LVT (Low Voltage
Threshold), SVT (Standard Voltage Threshold), HVT (High Voltage Threshold), and IO
voltage devices (1.35V/1.5V/1.8V/3.3V/5.0V). Each device type has numerous process
corners, e.g. SS, TT, FF, FS etc. Model selection also adds significant inaccuracy, for
example digital corner models are used for analog circuits. The details are given for dos &
donts for corner models in [51]that shows their inapplicability for analog circuits.

The sensitive corner information primarily comes from design. Moreover, the outlier
devices seen in wafer testing/ATE are also a candidate for analog bench validation. The
challenge for validation is to have list of process corners. These samples should be tested
across temperature and device operating voltage ranges. This leads to increase in number
of combinations to be tested. Hence, identifying the worst corners for finding maximum
bugs is always a challenge as analog bench validation is limited to small number of devices
(20-50 devices). This small sample is supposed to represent all devices that can be seen in
the entire life cycle of the product.

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2) Use Case List Scenario::

The method creating test cases/scenarios that adequately exercise the functionality of
smaller analog blocks of SoC has been widely used. But, deciding use case list scenarios
of a SoC in its entirety remains a difficult and challenging problem.

Many a times, new use case of silicon pops up which is different form original use cases.
Analog bench validation is expected to stress the design matching the use case for operation
at system level. This is always a challenge and analog bench validation has to go through
reverse engineering to identify the use case and to derive a test case in analog bench. The
interaction between various components sourced from open market creates unique
scenarios which cannot be predicted upfront. There is always an expectation beyond legacy
compliance testing requirement, which ensures interoperability in the field. The open
challenge is to ensure that DUT will work with any third-party vendor device.

3) Signal Integrity/Crosstalk::

Signal integrity analysis corresponds to analysis of effects produced by analog behavior

of digital circuits. The process of detecting and debugging issues that arise from such
analog behavior is termed as electrical characterization and comes under purview of analog
bench validation. Some of the electrical characterization features are cross talk, power
supply noise and thermal effects. They can be caused because of the interference
occurrence of design and electrical state on that particular moment. Often in functional
validation, these issues are seen under specific operating conditions as PVT conditions
(Process, Voltage and Temperature) or frequency.

For complex SoCs, there is requirement of complex board for testing the analog features
and parameters and hence, many issues related to boards have been observed i.e. power
ground connection error, power sequence for different voltage supply, signal and power
integrity issues and incorrect footprint & contact issues. These come under signal integrity
issues, which are quite difficult to debug.

High speed digital design focus on the behavior of active and passive circuit elements
that influence the signal propagation. This study involves many topics including signal
ringing, reflections, skew time, jitter, cross-talk and EMI (electromagnetic Interference).

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Example for the active components are I/O Buffers, OP-Amp and PLL. Similarly, passive
components are like PCB [52], IC packaging and connectors used in the circuit. These
passive components affect the circuit electrical performance at lower frequency directly
acting as transmission lines [53]. In board signal propagates through multiple sub
components i.e. interposer, socket, test fixture and multiplexer electrostatic discharge
(ESD) devices on board. All of this impact signal propagation.

An interposer is an electrical interface between a socket or a connector. An interposer

uses additional routing to bridge different physical connectors, which is a major reason for
signal degradation [54]. So, performing the validation for analog block in such a scenario
may create additional interposer specific signal integrity issues. In analog bench validation
during debug or parameter characterization, probing is another challenge. Shrinking size of
the integrated circuit due to sub nanotechnology is one of the major hurdles in signal
probing. Even with this small size, the number of probe points are increasing in order to
have more observability of the design. Both of these become challenging in the signal
probing. Apart from these, the probe also adds to the capacitive loading of the device, which
causes its malfunctioning. The probing solutions [55] should have a reduced amount of
capacitive loading on the design and have easy access to probe points.

For validation of different signals coming out of the SoC, the test fixtures [56] (device
or setup designed to hold the device under test in place) are used. Again, probing the high-
speed signals via test fixture is a challenge in case of HSSI. Similarly, multiplexers and
ESD devices which are used on board, degrade the quality of signal. So, designing/choosing
right multiplexers and ESD devices according to the data rate of signals is very challenging.

4) Technique To Overcome Limitations Of Equipment::

The test equipment limitation can be put in two categories, first, equipment lacks the
ability to measure the specification. Second, although the equipment has capabilities to
measure the specification, it lacks methodologies to shorten the debug cycle. When
performance requirement on the test equipment does not match the specification, circuit
technique and signal processing methodologies come to aid of test engineer. For example,
as the data rate of high-speed serial interface goes up, it is possible that the available
equipment does not match the capacity. Validation tends to rely on specific design tweaks

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for such tests or indirect measurement or assessment by inference. For cases where test
equipment has the capability to measure the specification, lack of efficient methodology to
localize bugs in a short time is very common. As such, one must perform expensive bench
level characterization. It requires extensive external setups, i.e. oscilloscope, BERT scope,
Data generator etc. to record and analyze all analog signal values & parameters that enters
and exits the system through external pin. In validation system, many times hardware and
software are combined as a system. So, detecting and troubleshooting, and root-causing of
a specific problem is a major concern. For example, we can view the bus level signal using
the scope or analyzer of a serial bus protocol. This signal information represents the
electrical characteristics of bus. But these instruments need to capture the electrical
parameters of the signal without deforming and analyze the state of same to display.

The analog bench validation system will be having many test equipment components
which will perform specific tasks together. All these components need to be tightly coupled
and synchronized to provide the accurate results. This can be performed well with the
system level knowledge of the validation engineer.

Execution of specific tasks accounts for many hardware components and system level
view of DUT is a must for validation engineers to measure the interaction arising in these
components. These interactions make it a challenge to synchronize the operations of these
components such that they provide accurate information with respect to timing
performance. Existing equipment tend to be lacking in connecting the dots. So, these test
equipments have an ever-increasing need to catch up with debug requirements of newly
evolving systems. However, there are cases when inference has to be made by indirect
measurement for a particular specification.

2.3 Recant Development and Future Research Direction

In this section, we compile recent developments of analog bench validation. Our aim is
to focus on latest results and provide problems for further research direction. We abandon
our claim for the completeness of the compilation. Mostly all complex SoCs have serial
interfaces with very high data rate. Therefore, we mostly focus on high-speed serial
interface validation & characterization. The complex design of high data rate serial
interfaces makes it the most challenging area for analog bench validation.

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2.3.1 High Speed Serial Interface (HSSI) Validation

High-speed serial interfaces are used in almost all silicon products. The quality of the
signal transmission is a critical factor in the design of high-speed applications. Gigabit
speed requires high-speed serial interconnection with high-speed serial devices (i.e. SATA,
PCIe, USB etc.). Serial interface is the complete path that connects a device (e.g. CPU,
chipset, memory etc.) to another device. Due to the increasing demand of clean signal
transmission, good signal quality in high-speed interface is crucial.

Sophisticated techniques including equalization and precompensation can achieve high

data rates, which are prevailing in high-speed serial interfaces (HSSI). Increasing
complexity and decreasing time budget in SoC leads to critical debugging and testing of
HSSIs. Jitter injection scheme and Bit Error Rate Tester (BERT) are used in validation and
testing HSSIs that eliminate the need of high-speed automatic test equipment and design
for-test (DFT) features. These schemes are used to compensate existing limitations of
instruments.

A lot of active research work has been done in the area of jitter testing, frequency, phase
noise, spectrum, etc. [57]. Zhu et el [58] carried out a clock testing method based on the
analysis of instantaneous phase to extract the jitter, frequency, phase noise spectrum of
phase-locked loop output clock. This method converts the signal of PLL output, the
modulator output, into an analytic signal. In [59], the authors report a method to measure
the frequency of on-chip test clock using the reference clock. This is done by counting the
pulses of both test and reference clock in a defined manner.

Apart from clock testing, many advances have been done in the transmitter, which
include measurement of equalization, eye diagram, drive strength, impedance, data rate,
etc. In the context of the receiver, measurement of data rate, equalization, signal swing, bit
error rate (BER), signal noise ratio (SNR), with and without loopback testing (external and
internal loopback) in HSSI validation are important measures.

Analog bench validation is affected by many factors like growing complexity, reduction
in time to market and substantial performance requirements. So, validation team always
explores new methodologies to produce faster and cost-effective solutions. In [60], the
authors provide an optimized approach in industrial post silicon validation for receiver

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analog circuitry knob. This approach merges system margining and jitter tolerance
measure.

Further, robustness of signal integrity (SI) on the highspeed channel in graphic design
unit (GDU) system SoC is an important factor. To identify the SI risk of channels (PCIe),
end to end simulation as well as marginal validation and functional stress test (BER testing)
are carried out to investigate the challenges on such high-speed channel designs.

Characterizing a standalone design (i.e. DDR etc.) is normally hindered by various

irregularities such as reflections, crosstalk, EMI etc. impacting the signal propagation from
DUT to the test board fixture. The work discussed in [61] offers a unique approach to the
cause of jitter variation on the characterization board, using simulations. Validation &
characterization of Analog bench can provide more comprehensive to testing of standalone
bench setup for a SoC.

A mixed-signal oscilloscope is generally used for analog signal characterization. This is

equipped with digital bus event and timing analysis. Fig. 2.5 represents bench level setup
with its components for system debugging tool.

2.3.2 Controllability and Observability

In SoC, many a times, hardware and software are combined as a system. So, debugging
the root cause of a specific problem is done through analog bench level validation &
characterization [36], [62]. For this type of bench level testing, setup is designed as
standalone as per the scenario in [37]. The respective implementers forum (i.e. USB-IF,
PCISIG) describes the method and approach for validating these characteristics. Legacy
compliance approach requires SoC dependent software device driver and tools from
respective specification bodies. The device driver generally requires customization for such
debug in analog bench validation and as such, the device driver is hard to get working

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Fig. 2.5. Analog Bench Test-setup for PHY Characterization [57]

immediately. There is no methodology to debug the bugs in these kinds of setups and there
is no observability and controllability for root causing the bugs at low level.

The software device drivers have debug and diagnostic features for software related
issues. There is a critical gap for hardware related debug features in software. The software
device drivers can be modified to support hardware diagnostic in a more streamlined
approach. This is an area of opportunity for hardware software co-design.

Although [35] and [3] discuss and provide a method for low level debugging, they have
used u-boot as low level debugging, which is not used as firmware. So, these solutions are
case specific and cant be generalized. The difficulties seen with software driver is that these
are not meant for debug and diagnostics of hardware. Common practice is to tweak the
device driver for use in case specific debug requirements. It could be alternate initialization
of hardware, diagnostic dump of data structure and read/write of debug features. However,
these methods are knee-jerk reactions to specific issues. Tweaking device driver in software
environment is a complex activity. There is a scope for holistic software approach to
hardware debug for serial interface. Open source driver developers, generally do not prefer
a software code that is depend on SoC specific hardware fixes. This impacts product release
schedule. To address these limitations, there is research scope to develop methodology and
apparatus as an alternative and better approach for analog bench validation and
characterization of serial interfaces.

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Further Pandey et al. [38] carried out an electrical (analog) compliance testing of serial
interface on a complete embedded product. The product encompasses three entities (i)
software/firmware, (ii) controller (iii) physical layer (PHY). The compliance testing is
performed for isolating above entities. Testing also includes sufficient debug capabilities
to circumvent the issues. The analog validation has been done by using JTAG-based
approach. This approach enhances the debugging skills, particularly at low levels.
However, this is not prescribed methodology as per respective forums. Moreover other
problems with this approach is that for single IP, different test fixtures for different
scenarios make the job complex. Manual intervention while creating setups often causes
failure in measurement, which leads debug in the wrong direction. Management of large
number of test fixtures is a difficult job. And with available fixtures used in analog bench
validation of serial interface, automation is almost impossible. So, by using these fixtures,
much time and efforts are required, which leads to less productivity and high cost.

The above problem requires research for a unique method and test fixture, which could
handle all the scenarios for single IP. It should solve the problem of making different setups,
which are prone to manual errors. Time and effort can be saved by developing such a
framework. Speed of SOC/IP needs to be considered for confining the unification of such
methodology and test fixture i.e. separate framework for speeds < 1Gbps and for multi
Gbps (> 1Gbps). Again, research in these domains will enhance the controllability.

2.3.3 Loopback Testing

A low-cost solution for testing HSSI was developed in [63], which alleviated the need
for high performance equipment. During the external loopback testing, the DUT is
configured into several configurations [64], that routes the output of one component of the
pair (transmitter), to the input of the other component of the pair (receiver), as shown in
Fig. 2.6.

The above-mentioned approach embeds testing of the buffer circuitry, which is closer
to customer application and helps correlate with the customer failure faster and more
effectively. On-die DFT requirement is simplified as well. Besides, this simplifies the on-
die DFT requirement and the parameter-based testing usage is also minimized. Test cost

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Fig. 2.6. HSSI Testing with Loopback Method (External Loopback)

can be kept down as the dependency on ATE testers power management usage will
significantly reduce.

Fig. 2.7 shows the Loopback configuration including Internal and external loopback
which are widely accepted due to their cost-effective testing nature for various
specifications of both transmitter and receiver. For high speed serial link (HSSL), external
loopback is often necessary because internal loopback does not test input output pads and
external channel degradation, which are the primary jitter contributors during the system
operation. Meixner et al. [65], Trawka et al. [66] and Keezer et al. [67] has discussed several
variations in external loopback. The above-mentioned jitters are fully characterized and can
be introduced into the design of loopback elements to mimic the channel effects. The
amount of jitters is adjusted in order to improve the validation and characterization quality.
Using either internal or external loopback, the transceivers or converter pairs are tested as
a single, end-to-end system (while the system is artificially created and is different from
the system configuration used for normal operations). In addition, the loop-back approach
is not effective for debugging because fault localization is inherently difficult in a loopback
setup.

Cai et al. [68], in their seminal work explain the effectiveness of enhanced Spread
Spectrum Clocking (SSC)-based jitter tolerance test in loopback mode for serial interface.
This can be a lucrative procedure for robust jitter tolerance test. The important notable

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Fig. 2.7. HSSI Testing with Loopback Method (Internal)

advantages for this technique are that this eliminates the need of external instruments as
well as extensive calibration schemes. But the limitation of this technique is that it allows
the use of a jitter called Period Jitter that stresses the clock data recovery (CDR). Even
though it is very efficient in stressing the receiver but it will be difficult to emulate the
different jitter types when compared to the combination of real application environment.
The sources of these jitters vary in the system, for example bandwidth limited transmission
medium can cause the Inter Symbol Interference (ISI) jitter that can stress the receiver CDR
differently. These limitations are again indicators for more research directions. The
research will answer whether random jitter (RJ), deterministic jitter (DJ) can be used for
stressing the CDR.

Above mentioned tests are done through specifications and marginal based. It requires
mainly for measurement of system margins and jitter tolerance (JTOL) using knob tuning
process in post-silicon validation. These tests are done on high-speed serial interface, where
we test through loopback or with BIST method. In BIST method, as shown in Fig. 2.8, we
give data pattern with jitter through Rx and check in BIST checker for long data inside SoC

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Fig. 2.8: HSSI Validation of Transmitter and Receiver with Hybrid Approach

and see how many times it fails. Similarly, for transmitter testing, BIST pattern generator
will generate the transmitter signal inside SoC, which is analyzed in oscilloscope.

At low speed, IP can be configured to run at-speed loopback and pass/fail status can be
read from a register or monitored at lower rate. Different flavors of loopback, when used
in combination, help in bug localization. Internal loopback eliminates board inferences and
provide indication of performance due to on-chip transistors. External loopback is impacted
by PCB traces and gives an indication of performance change due to board.

2.3.4 Emanating Trend in High Speed Serial Interface

With the increasing demand for higher bandwidth computing devices, high-speed
interfaces such as PCI express, serial ATA, etc., have been rapidly adopted in various
applications. In the present telecommunication world, the cellular data usage increases very
drastically. This increases the need of data processing at interface edge, where the data
computing rises. Because of these advanced computing demands in emerging applications,
designs are rapidly accepting the high-speed interface protocols like PCI Express, Serial
ATA etc, in the devices. In the early era, these communication chips used to have lesser
speed of operation and minimum IOs with smaller number of lanes in their applications.

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However, the current chip designs are reaching GHz of operational frequency with
numerous IOs.

As per ITRS 2015 roadmap [69], high frequency (multiple Gbps/GHz) I/O technology
continues to rise significantly in terms of speed. Similar growth is expected in other
application fields like Computing, Networking and Consumer electronics. For example,
port count has increased quickly in networking, remote connectivity and access increased
in consumer applications. The cost of setting up the lab for 5Gps data rate analog testing,
as shown in Fig. 2.5 can be enormously high. This setup expects constant supervision of
skilled engineers for a limited sample sized characterization (as discussed in Fig. 2.2) due
to the involvement of expensive test equipments. When we move to testing of 10Gbps serial
interface, the cost goes above $1 million. Currently, industries are moving to 28Gbps.
However, the ITRS roadmap continuously encourages much higher I/O frequencies for the
future. Testing of very high-speed serial interface has become a very costly affair. This will
lead to future research opportunities. Development of methodology or setup for validation
of high-speed serial interface need to be done without further increasing the cost of setup.

2.3.5 Extended Debug & Root Causing Real Life Cases

There are many real-time issues observed in post silicon validation, which may become
the reason for development in the field of analog bench validation. In this subsection, we
will discuss a couple of real-life silicon cases.

1) Case-1: USB Received Data Path Marginality Debug:: At analog bench validation,
it is observed that the validated and characterized silicon showed random failures during
data read as read timeout was a failure. The prior validation methodology during timeout
failure consisted of using fixed input clock to high-speed serial interface during data
transfer with multiple devices, varying data packets (packet content, packet size) and cable
length. It was found during debug that fixed frequency method does not necessarily cover
all jitter scenarios. Thus, there is a need for a reliable method using some other test
methodology to ensure that the design marginality is captured at the earliest. Searching for
design marginality with prior method (constant Input frequency to input receiver) is very
difficult, since failures are random and identifying a failing configuration using any of the
unknown external devices makes the problem more challenging.

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2) Case-2: Initialization Failure Debug of Serial Interfaces:: At serial interface with

high-speed host & devices, device connection and data transfer failure issues are always a
challenge for designers and validation researchers. Case study of device connection issues
and their debug have been discussed in [3] at high speed serial interface (USB2.0). Similar
scenarios exist in other serial interfaces i.e. USB3.0, PCIe etc. In serial interface,it might
be desirable to have a host dynamically power down an attached device as part of its power
management scheme. Authors in [70], found problem that the USB 2.0/3.x specification
does not provide for a discharge mechanism on the host/device side for VBUS power.
Authors have modeled the VBUS power discharge So for the same, dual resister model
estimation has been provided for this limitation. But dual register model is limited to
representation of USB device as resistors. So, there are opportunities for validation to find
novel ways to prevent debug and root cause these kind of limitations for USB as well as
for other serial interfaces i.e. SATA, SD Card, PCIe etc.

3) Case-3: USB Performance Testing Methodology:: Apart from controllability,

observability, debugging and root causing of serial interface, data throughput performance
available to end application is quite important. High-speed serial interfaces i.e. SATA 3.0,
PCIe Gen3 and USB3.0, promise a significant performance improvement over previous
generations because they use more than 5-Gigabit-per-second signaling rate. Low
performance can be easily observed while performing the data transfer with host to device
through serial interface.

Performance of low data rate serial interfaces (USB2.0) can be improved using
technique given in [71]. Authors in [72] discuss performance improvement strategies for
high data rate (up to 5Gbps) at controller EZ-USB FX3 . This demonstrate a research
avenue in improving the throughput of serial interfaces.

4) Case-4: Implication of PLLs on High-Speed Serial Interfaces:: PLLs having very

crucial role in the case of high speed serial interface performance. There are many
implication of PLLs on HSSI in terms of design, bench validation and signal quality
analysis. In [73] authors discussed the impact of PLL (on-chip single source clocking).
Authors introduce the issues observed in an ARM based 28nm networking SoC with
multiple high-speed serial interfaces. This SoC uses a nontraditional common clocking
solution sourced from an off-chip crystal. The issues and challenges observed during

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validation and debug (high jitter values observed during characterization of PCIe, SATA
and SerDes transmitter clock). So, above discussed real life case lead to further research
opportunity regarding impact of PLL in serial interface.

2.3.6 Emerging Trends in industry

Emerging technologies have always presented various opportunities and challenges for
validation. Some the developments in industry are millimeter-wave [74], mobile molecular
communication, radio frequency (RF), 5G technology, automotive radar sensor,
automotive self-driving cars, in vehicle electronics and communication (automotive
ethernet).Thus, exciting times are ahead for analog bench validation research.

Electronics content in vehicular (automotive) applications is exponentially increasing

with the arrival of self-driving cars. Sensor nodes and local processing of sensor data will
be key in future self-driven battery-operated cars. Demand for higher data-rate serial
communication links is ever increasing. Wireline communication is preferred over wireless
because of security, reliability and speed. Full-duplex communication over single coax
cable reduces the number of interconnects to minimum, thereby reducing cost and weight.
Coaxial cable is also suited over twisted pair based solution for higher data rates. This may
also find applications in other areas (e.g. space application, harsh industrial environment,
etc.) due to lower cable weight. Single ended coaxial cable based duplex serial link poses
future opportunities for significant design and validation challenges.

RF application are increasingly reliant on data converter (analog to digital converter-

ADC/digital to analog converter-DAC) for newer applications. So, validation
methodologies for data converter as well as RF data converter are some exciting
opportunities for analog bench validation research. In article [75], authors have discussed
some non-trivial pitfalls in ADC characterization and have suggested methods to increase
test efficiency for eg. robust calibration and spur removal. It is expected that in next
generation 5G/ millimeter wave MIMO RF configurations, new validation scenarios will
emerge.

As such, legacy analog bench validation coupled with Op-Amp, bandgap, low-dropout
(LDO) regulator, switching regulator etc. will sow the seeds for novel validation

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approaches in complex systems. These research areas have numerous recent advancements.
These domains of analog bench validation could be taken as separate research field.

2.4 Summary

This chapter provides a comprehensive review of overall silicon validation ecosystem

typically existing inside a semiconductor company with emphasis on evolution of analog
bench validation. The post silicon validation development model is presented. The work,
thus, describes the flow and importance of Analog bench validation of silicon in context of
overall silicon validation flow. It has been explained that the factors contributing to growth
of analog bench validation would continue to evolve in other forms of validation, emerging
industry specifications and gaps in existing validation methodology. These factors reveal
that the analog bench validation is an emerging research field with several unanswered
questions. Several outstanding challenges and addressing them can be regarded as potential
research problems in the validation and related fields. Additionally, validation
methodologies for high-speed serial interfaces are discussed to illustrate state of the art
methodologies and current gaps. The challenges in analog bench validation are identified
for serial interfaces. It is expected that future validation methodologies would emerge based
on factors identified in this work.

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