PIPELINE HAZARDS
DEMONSTRATION
SUBJECT: COMPUTER ORGANIZATION AND
ARCHITECTURE
GROUP NUMBER:4
GROUP MEMBERS
[Link].B
[Link].M
[Link] Muthalib
[Link] Naveen T
[Link] P.P
INTRODUCTION
Pipeline Hazard Demonstration is a software project that simulates how a
pipelined processor executes multiple instructions simultaneously to improve
performance.
A typical 5-stage pipeline includes:
=> Instruction Fetch (IF)
=>Instruction Decode (ID)
=>Execute (EX)
=>Memory Access (MEM)
=> Write Back(WB)
Although pipelining increases speed, it can cause pipeline hazards, which reduce
efficiency
Hazard:
A hazard is a condition in a pipelined processor that delays an instruction from
executing in its scheduled clock cycle. Hazards reduce performance and may require
techniques like stalling or forwarding to resolve them.
OBJECTIVES
• To study the concept of pipelining in a RISC processor.
• To demonstrate Data Hazards and Control Hazards using simulation tools.
• To analyze how these hazards affect pipeline performance.
• To observe pipeline stalls and flushing caused by hazards.
METHODOLOGY
Language used:
RISC-V Assembly Language
Used to write instruction sequences that intentionally create
=>Data Hazards
=>ControlHazards
Tools Used:
Ripes – RISC-V Simulator
Features use:
=>5-stage pipeline visualization
=>Cycle-by-cycle execution
=>Hazard detection display
Processor Used:
=>5-Stage Processor
=>5-stage processor w/o forwarding or hazard detection
Pipeline Stages:
=>IF (Instruction Fetch)
=>ID (Instruction Decode)
=>EX (Execute)
=>MEM (Memory Access)
=>WB (Write Back)
• Simulation Steps:
=>Open Ripes simulator.
=>Select 5-Stage Pipelined Processor model.
=>Write or load RISC-V assembly code.
=>Assemble the program.
=>Run the program cycle-by-cycle.
Types of Pipeline Hazards
In this project, we focus on:
=>Data Hazard
=>Control Hazard
DATA HAZARDS
A Read-After-Write (RAW) hazard, or true dependency, occurs in computer
pipelines when an instruction requires data from a previous instruction that has
not yet completed writing it, causing the reading of stale or incorrect data
CONTROL HAZARDS
A control hazard occurs when the decision of what instruction to be fetch
next has not been made by the time the fetch take place.
RESULT
DATA HAZARD
CONTROL HAZARD
RESULT
The simulation was successfully performed using the Ripes tool.
Different instruction sequences were executed to demonstrate data hazards and control
hazards in a pipelined processor.
The pipeline stages (IF, ID, EX, MEM, WB) were clearly observed during program
execution.
Data hazards caused pipeline stalls when an instruction depended on the result of a previous
instruction.
Control hazards occurred during branch instructions, which caused pipeline flushing or
delay.
The number of clock cycles increased when hazards occurred, showing a reduction in
pipeline efficiency.
The simulation successfully demonstrated how hazards affect instruction execution and
processor performance
CONCLUSION
Pipelining improves processor performance by executing multiple instructions
simultaneously in different stages.
During the project, we observed that pipeline hazards interrupt smooth instruction
execution and reduce efficiency.
Using the RISC-V based Ripes simulator, we demonstrated data hazards and control
hazards.
These hazards cause pipeline stalls, delays, or instruction flushing, which increases the
number of clock cycles.
By running different instruction sequences, we clearly observed how hazards affect pipeline
performance.
FUTURE SCOPE
Extend the project to include structural hazards along with data and control hazards.
Implement and demonstrate hazard handling techniques such as forwarding, pipeline
stalling, and branch prediction.
Compare the performance of different processor pipeline models using the simulator.
Analyze how hazards affect execution time, clock cycles, and overall processor
efficiency.
Enhance the simulation by using more complex instruction sequences for deeper
analysis.
Apply the concept to study modern processor architectures and their pipeline
optimization techniques.
REFERENCES
Computer Organization and Design RISC-V Edition – David A. Patterson and John L.
Hennessy.
Ripes Official Documentation.
RISC-V International – RISC-V Architecture Documentation.
COA (Computer Organization and Architecture) lecture notes and class materials.
Online tutorials and educational resources on pipelining and pipeline hazards.