Precision Micropower, Low Dropout

Voltage References
REF19x Series
FEATURES TEST PINS
Initial accuracy: ±2 mV maximum Test Pin 1 and Test Pin 5 are reserved for in-package Zener zap.
Temperature coefficient: 5 ppm/°C maximum To achieve the highest level of accuracy at the output, the Zener
Low supply current: 45 μA maximum zapping technique is used to trim the output voltage. Since each
Sleep mode: 15 μA maximum unit may require a different amount of adjustment, the resistance
Low dropout voltage value at the test pins varies widely from pin to pin and from
Load regulation: 4 ppm/mA part to part. The user should leave Pin 1 and Pin 5
Line regulation: 4 ppm/V
unconnected.
High output current: 30 mA
Short-circuit protection TP 1
REF19x 8 NC
VS 2 7 NC
SERIES
APPLICATIONS SLEEP 3 TOP VIEW 6 OUTPUT

Portable instruments GND 4 (Not to Scale) 5 TP

ADCs and DACs NOTES

Smart sensors 1. NC = NO CONNECT.

00371-001
2. TP PINS ARE FACTORY TEST
Solar-powered applications POINTS, NO USER CONNECTION.
Loop current-powered instruments Figure 1. 8-Lead SOIC_N and TSSOP Pin Configuration
(S Suffix and RU Suffix)
GENERAL DESCRIPTION
TP 1 8 NC
The REF19x series precision band gap voltage references use a REF19x
VS 2 7 NC
patented temperature drift curvature correction circuit and SERIES
SLEEP 3 6 OUTPUT
TOP VIEW
laser trimming of highly stable, thin-film resistors to achieve a GND 4 (Not to Scale) 5 TP
very low temperature coefficient and high initial accuracy.
NOTES
1. NC = NO CONNECT.
The REF19x series is made up of micropower, low dropout

00371-002
2. TP PINS ARE FACTORY TEST
voltage (LDV) devices, providing stable output voltage from POINTS, NO USER CONNECTION.

supplies as low as 100 mV above the output voltage and Figure 2. 8-Lead PDIP Pin Configuration
consuming less than 45 μA of supply current. In sleep mode, (P Suffix)
which is enabled by applying a low TTL or CMOS level to the
SLEEP pin, the output is turned off, and supply current is Table 1. Nominal Output Voltage
further reduced to less than 15 μA. Part Number Nominal Output Voltage (V)
The REF19x series references are specified over the extended REF191 2.048
industrial temperature range (−40°C to +85°C), with typical REF192 2.50
performance specifications over −40°C to +125°C for REF193 3.00
applications such as automotive. REF194 4.50
REF195 5.00
All electrical grades are available in an 8-lead SOIC_N package; REF196 3.30
the PDIP and TSSOP packages are available only in the lowest REF198 4.096
electrical grade. Products are also available in die form.

Rev. I
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 [Link]
Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
REF19x Series

TABLE OF CONTENTS
Specifications..................................................................................... 3 Wafer Test Limits........................................................................ 14
Electrical Characteristics—REF191 @ TA = 25°C .................... 3 Absolute Maximum Ratings ......................................................... 15
Electrical Characteristics—REF191 @ −40°C ≤ TA ≤ +85°C .. 4 Thermal Resistance .................................................................... 15
Electrical Characteristics—REF191 @ −40°C ≤ TA ≤+125°C. 5 ESD Caution................................................................................ 15
Electrical Characteristics—REF192 @ TA = 25°C .................... 5 Typical Performance Characteristics ........................................... 16
Electrical Characteristics—REF192 @ −40°C ≤ TA ≤ +85°C.. 6 Applications..................................................................................... 19
Electrical Characteristics—REF192 @ −40°C ≤ TA ≤ +125°C 6 Output Short-Circuit Behavior ................................................ 19
Electrical Characteristics—REF193 @ TA = 25°C .................... 7 Device Power Dissipation Considerations.............................. 19
Electrical Characteristics—REF193 @ −40°C ≤ TA ≤ +85°C.. 7 Output Voltage Bypassing ......................................................... 19
Electrical Characteristics—REF193 @ TA ≤ −40°C ≤ +125°C 8 Sleep Mode Operation............................................................... 19
Electrical Characteristics—REF194 @ Ta = 25°C..................... 8 Basic Voltage Reference Connections ..................................... 19
Electrical Characteristics—REF194 @ −40°C ≤ TA ≤ +85°C.. 9 Membrane Switch-Controlled Power Supply ......................... 19
Electrical Characteristics—REF194 @ −40°C ≤ TA ≤ +125°C 9 Current-Boosted References with Current Limiting............. 20
Electrical Characteristics—REF195 @ TA = 25°C .................. 10 Negative Precision Reference without Precision Resistors ... 20
Electrical Characteristics—REF195 @ −40°C ≤ TA ≤ +85°C 10 Stacking Reference ICs for Arbitrary Outputs ....................... 21
Electrical Characteristics—REF195 @ −40°C ≤ TA ≤ +125°C Precision Current Source .......................................................... 21
....................................................................................................... 11 Switched Output 5 V/3.3 V Reference..................................... 22
Electrical Characteristics—REF196 @ TA = 25°C .................. 11 Kelvin Connections.................................................................... 22
Electrical Characteristics—REF196 @ −40°C ≤ TA ≤ +85°C 12 Fail-Safe 5 V Reference.............................................................. 23
Electrical Characteristics—REF196 @ −40°C ≤ TA ≤ +125°C Low Power, Strain Gage Circuit ............................................... 24
....................................................................................................... 12
Outline Dimensions ....................................................................... 25
Electrical Characteristics—REF198 @ TA = 25°C .................. 13
Ordering Guide .......................................................................... 26
Electrical Characteristics—REF198 @ −40°C ≤ TA ≤ +85°C 13
Electrical Characteristics—REF198 @ −40°C ≤ TA ≤ +125°C
....................................................................................................... 14

REVISION HISTORY
9/06—Rev. H to Rev. I 7/04—Rev. F to Rev. G
Updated Format..................................................................Universal Changes to Ordering Guide .............................................................4
Changes to Table 25 ....................................................................... 15 3/04—Rev. E to Rev. F
Changes to Figure 6........................................................................ 16 Updated Absolute Maximum Rating ..............................................4
Changes to Figure 10, Figure 12, Figure 14, and Figure 16....... 17 Changes to Ordering Guide .......................................................... 14
Changes to Figure 18...................................................................... 18 Updated Outline Dimensions....................................................... 24
Changes to Figure 20...................................................................... 19
1/03—Rev. D to Rev. E
Changes to Figure 23...................................................................... 20
Changes to Figure 3 and Figure 4................................................. 15
Changes to Figure 25...................................................................... 21
Changes to Output Short Circuit Behavior................................. 17
Updated Outline Dimensions ....................................................... 25
Changes to Figure 20...................................................................... 17
Changes to Ordering Guide .......................................................... 26
Changes to Figure 24...................................................................... 19
6/05—Rev. G to Rev. H Updated Outline Dimensions....................................................... 23
Updated Format..................................................................Universal
1/96—Revision 0: Initial Version
Changes to Caption in Figure 7 .................................................... 16
Updated Outline Dimensions ....................................................... 25
Changes to Ordering Guide .......................................................... 26

Rev. I | Page 2 of 28
 REF19x Series

SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—REF191 @ TA = 25°C
@ VS = 3.3 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter Mnemonic Condition Min Typ Max Unit
INITIAL ACCURACY 1
E Grade VO IOUT = 0 mA 2.046 2.048 2.050 V
F Grade 2.043 2.053 V
G Grade 2.038 2.058 V
LINE REGULATION 2
E Grade ΔVO/ΔVIN 3.0 V ≤ VS ≤ 15 V, IOUT = 0 mA 2 4 ppm/V
F and G Grades 4 8 ppm/V
LOAD REGULATION2
E Grade ΔVO/ΔVLOAD VS = 5.0 V, 0 mA ≤ IOUT ≤ 30 mA 4 10 ppm/mA
F and G Grades 6 15 ppm/mA
DROPOUT VOLTAGE V S − VO VS = 3.15 V, ILOAD = 2 mA 0.95 V
VS = 3.3 V, ILOAD = 10 mA 1.25 V
VS = 3.6 V, ILOAD = 30 mA 1.55 V
LONG-TERM STABILITY 3 DVO 1000 hours @ 125°C 1.2 mV
NOISE VOLTAGE eN 0.1 Hz to 10 Hz 20 μV p-p
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term stability specification is noncumulative. The drift in subsequent 1000-hour periods is significantly lower than in the first 1000-hour period.

Rev. I | Page 3 of 28
REF19x Series
ELECTRICAL CHARACTERISTICS—REF191 @ −40°C ≤ TA ≤ +85°C
@ VS = 3.3 V, −40°C ≤ TA ≤ +85°C, unless otherwise noted.
Table 3.
Parameter Mnemonic Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT 1, 2
E Grade TCVO/°C IOUT = 0 mA 2 5 ppm/°C
F Grade 5 10 ppm/°C
G Grade 3 10 25 ppm/°C
LINE REGULATION 4
E Grade ΔVO/ΔVIN 3.0 V ≤ VS ≤ 15 V, IOUT = 0 mA 5 10 ppm/V
F and G Grades 10 20 ppm/V
LOAD REGULATION4
E Grade ΔVO/ΔVLOAD VS = 5.0 V, 0 mA ≤ IOUT ≤ 25°C 5 15 ppm/mA
F and G Grades 10 20 ppm/mA
DROPOUT VOLTAGE V S − VO VS = 3.15 V, ILOAD = 2 mA 0.95 V
VS = 3.3 V, ILOAD = 10 mA 1.25 V
VS = 3.6 V, ILOAD = 25 mA 1.55 V
SLEEP PIN
Logic High Input Voltage VH 2.4 V
Logic High Input Current IH −8 μA
Logic Low Input Voltage VL 0.8 V
Logic Low Input Current IL −8 μA
SUPPLY CURRENT No load 45 μA
Sleep Mode No load 15 μA
1
For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.
TCVO = (VMAX − VMIN)/VO(TMAX − TMIN)
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.

Rev. I | Page 4 of 28
 REF19x Series
ELECTRICAL CHARACTERISTICS—REF191 @ −40°C ≤ TA ≤+125°C
@ VS = 3.3 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 4.
Parameter Mnemonic Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT 1, 2
E Grade TCVO/°C IOUT = 0 mA 2 ppm/°C
F Grade 5 ppm/°C
G Grade 3 10 ppm/°C
LINE REGULATION 4
E Grade ΔVO/ΔVIN 3.0 V ≤ VS ≤ 15 V, IOUT = 0 mA 10 ppm/V
F and G Grades 20 ppm/V
LOAD REGULATION4
E Grade ΔVO/ΔVLOAD VS = 5.0 V, 0 mA ≤ IOUT ≤ 20 mA 10 ppm/mA
F and G Grades 20 ppm/mA
DROPOUT VOLTAGE V S − VO VS = 3.3 V, ILOAD = 10 mA 1.25 V
VS = 3.6 V, ILOAD = 20 mA 1.55 V
1
For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.
TCVO = (VMAX − VMIN)/VO(TMAX − TMIN)
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.

ELECTRICAL CHARACTERISTICS—REF192 @ TA = 25°C

@ VS = 3.3 V, TA = 25°C, unless otherwise noted.
Table 5.
Parameter Mnemonic Condition Min Typ Max Unit
INITIAL ACCURACY 1
E Grade VO IOUT = 0 mA 2.498 2.500 2.502 V
F Grade 2.495 2.505 V
G Grade 2.490 2.510 V
LINE REGULATION 2
E Grade ΔVO/ΔVIN 3.0 V ≤ VS ≤ 15 V, IOUT = 0 mA 2 4 ppm/V
F and G Grades 4 8 ppm/V
LOAD REGULATION2
E Grade ΔVO/ΔVLOAD VS = 5.0 V, 0 mA ≤ IOUT ≤ 30 mA 4 10 ppm/mA
F and G Grades 6 15 ppm/mA
DROPOUT VOLTAGE V S − VO VS = 3.5 V, ILOAD = 10 mA 1.00 V
VS = 3.9 V, ILOAD = 30 mA 1.40 V
LONG-TERM STABILITY 3 DVO 1000 hours @ 125°C 1.2 mV
NOISE VOLTAGE eN 0.1 Hz to 10 Hz 25 μV p-p
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term stability specification is noncumulative. The drift in subsequent 1000-hour periods is significantly lower than in the first 1000-hour period.

Rev. I | Page 5 of 28
REF19x Series
ELECTRICAL CHARACTERISTICS—REF192 @ −40°C ≤ TA ≤ +85°C
@ VS = 3.3 V, −40°C ≤ TA ≤ +85°C, unless otherwise noted.
Table 6.
Parameter Mnemonic Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT 1, 2
E Grade TCVO/°C IOUT = 0 mA 2 5 ppm/°C
F Grade 5 10 ppm/°C
G Grade 3 10 25 ppm/°C
LINE REGULATION 4
E Grade ΔVO/ΔVIN 3.0 V ≤ VS ≤ 15 V, IOUT = 0 mA 5 10 ppm/V
F and G Grades 10 20 ppm/V
LOAD REGULATION4
E Grade ΔVO/ΔVLOAD VS = 5.0 V, 0 mA ≤ IOUT ≤ 25 mA 5 15 ppm/mA
F and G Grades 10 20 ppm/mA
DROPOUT VOLTAGE V S − VO VS = 3.5 V, ILOAD = 10 mA 1.00 V
VS = 4.0 V, ILOAD = 25 mA 1.50 V
SLEEP PIN
Logic High Input Voltage VH 2.4 V
Logic High Input Current IH −8 μA
Logic Low Input Voltage VL 0.8 V
Logic Low Input Current IL −8 μA
SUPPLY CURRENT No load 45 μA
Sleep Mode No load 15 μA
1
For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.
TCVO = (VMAX − VMIN)/VO(TMAX − TMIN)
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.

ELECTRICAL CHARACTERISTICS—REF192 @ −40°C ≤ TA ≤ +125°C

@ VS = 3.3 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 7.
Parameter Mnemonic Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT 1, 2
E Grade TCVO/°C IOUT = 0 mA 2 ppm/°C
F Grade 5 ppm/°C
G Grade 3 10 ppm/°C
LINE REGULATION 4
E Grade ΔVO/ΔVIN 3.0 V ≤ VS ≤ 15 V, IOUT = 0 mA 10 ppm/V
F and G Grades 20 ppm/V
LOAD REGULATION4
E Grade ΔVO/ΔVLOAD VS = 5.0 V, 0 mA ≤ IOUT ≤ 20 mA 10 ppm/mA
F and G Grades 20 ppm/mA
DROPOUT VOLTAGE V S − VO VS = 3.5 V, ILOAD = 10 mA 1.00 V
VS = 4.0 V, ILOAD = 20 mA 1.50 V
1
For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.
TCVO = (VMAX − VMIN)/VO(TMAX − TMIN)
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.

Rev. I | Page 6 of 28
 REF19x Series
ELECTRICAL CHARACTERISTICS—REF193 @ TA = 25°C
@ VS = 3.3 V, TA = 25°C, unless otherwise noted.
Table 8.
Parameter Mnemonic Condition Min Typ Max Unit
INITIAL ACCURACY 1
G Grade VO IOUT = 0 mA 2.990 3.0 3.010 V
LINE REGULATION 2
G Grade ΔVO/ΔVIN 3.3 V, ≤ VS ≤ 15 V, IOUT = 0 mA 4 8 ppm/V
LOAD REGULATION2
G Grade ΔVO/ΔVLOAD VS = 5.0 V, 0 mA ≤ IOUT ≤ 30 mA 6 15 ppm/mA
DROPOUT VOLTAGE V S − VO VS = 3.8 V, ILOAD = 10 mA 0.80 V
VS = 4.0 V, ILOAD = 30 mA 1.00 V
LONG-TERM STABILITY 3 DVO 1000 hours @ 125°C 1.2 mV
NOISE VOLTAGE eN 0.1 Hz to 10 Hz 30 μV p-p
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term stability specification is noncumulative. The drift in subsequent 1000-hour periods is significantly lower than in the first 1000-hour period.

ELECTRICAL CHARACTERISTICS—REF193 @ −40°C ≤ TA ≤ +85°C

@ VS = 3.3 V, −40°C ≤ TA ≤ +85°C, unless otherwise noted.
Table 9.
Parameter Mnemonic Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT 1, 2
G Grade 3 TCVO/°C IOUT = 0 mA 10 25 ppm/°C
LINE REGULATION 4
G Grade ΔVO/ΔVIN 3.3 V ≤ VS ≤ 15 V, IOUT = 0 mA 10 20 ppm/V
LOAD REGULATION4
G Grade ΔVO/ΔVLOAD VS = 5.0 V, 0 mA ≤ IOUT ≤ 25 mA 10 20 ppm/mA
DROPOUT VOLTAGE V S − VO VS = 3.8 V, ILOAD = 10 mA 0.80 V
VS = 4.1 V, ILOAD = 30 mA 1.10 V
SLEEP PIN
Logic High Input Voltage VH 2.4 V
Logic High Input Current IH −8 μA
Logic Low Input Voltage VL 0.8 V
Logic Low Input Current IL −8 μA
SUPPLY CURRENT No load 45 μA
Sleep Mode No load 15 μA
1
For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.
TCVO = (VMAX − VMIN)/VO(TMAX − TMIN)
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.

Rev. I | Page 7 of 28
REF19x Series
ELECTRICAL CHARACTERISTICS—REF193 @ TA ≤ −40°C ≤ +125°C
@ VS = 3.3 V, –40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 10.
Parameter Mnemonic Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT 1 ,2
G Grade 3 TCVO/°C IOUT = 0 mA 10 ppm/°C
LINE REGULATION 4
G Grade ΔVO/ΔVIN 3.3 V ≤ VS ≤ 15 V, IOUT = 0 mA 20 ppm/V
LOAD REGULATION4
G Grade ΔVO/ΔVLOAD VS = 5.0 V, 0 mA ≤ IOUT ≤ 20 mA 10 ppm/mA
DROPOUT VOLTAGE V S − VO VS = 3.8 V, ILOAD = 10 mA 0.80 V
VS = 4.1 V, ILOAD = 20 mA 1.10 V
1
For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.
TCVO = (VMAX − VMIN)/VO(TMAX − TMIN)
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.

ELECTRICAL CHARACTERISTICS—REF194 @ TA = 25°C

@ VS = 5.0 V, TA = 25°C, unless otherwise noted.
Table 11.
Parameter Mnemonic Condition Min Typ Max Unit
INITIAL ACCURACY 1
E Grade VO IOUT = 0 mA 4.498 4.5 4.502 V
F Grade 4.495 4.505 V
G Grade 4.490 4.510 V
LINE REGULATION 2
E Grade ∆VO/∆VIN 4.75 V ≤ VS ≤ 15 V, IOUT = 0 mA 2 4 ppm/V
F and G Grades 4 8 ppm/V
LOAD REGULATION2
E Grade ∆VO/∆VLOAD VS = 5.8 V, 0 mA ≤ IOUT ≤ 30 mA 2 4 ppm/mA
F and G Grades 4 8 ppm/mA
DROPOUT VOLTAGE V S − VO VS = 5.00 V, ILOAD = 10 mA 0.50 V
VS = 5.8 V, ILOAD = 30 mA 1.30 V
LONG-TERM STABILITY 3 DVO 1000 hours @ 125°C 2 mV
NOISE VOLTAGE eN 0.1 Hz to 10 Hz 45 μV p-p
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term stability specification is noncumulative. The drift in subsequent 1000-hour periods is significantly lower than in the first 1000-hour period.

Rev. I | Page 8 of 28
 REF19x Series
ELECTRICAL CHARACTERISTICS—REF194 @ −40°C ≤ TA ≤ +85°C
@ VS = 5.0 V, −40°C ≤ TA ≤ +85°C, unless otherwise noted.
Table 12.
Parameter Mnemonic Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT 1, 2
E Grade TCVO/°C IOUT = 0 mA 2 5 ppm/°C
F Grade 5 10 ppm/°C
G Grade 3 10 25 ppm/°C
LINE REGULATION 4
E Grade ∆VO/∆VIN 4.75 V ≤ VS ≤ 15 V, IOUT = 0 mA 5 10 ppm/V
F and G Grades 10 20 ppm/V
LOAD REGULATION4
E Grade ∆VO/∆VLOAD VS = 5.80 V, 0 mA ≤ IOUT ≤ 25 mA 5 15 ppm/mA
F and G Grades 10 20 ppm/mA
DROPOUT VOLTAGE V S − VO VS = 5.00 V, ILOAD = 10 mA 0.5 V
VS = 5.80 V, ILOAD = 25 mA 1.30 V
SLEEP PIN
Logic High Input Voltage VH 2.4 V
Logic High Input Current IH −8 μA
Logic Low Input Voltage VL 0.8 V
Logic Low Input Current IL −8 μA
SUPPLY CURRENT No load 45 μA
Sleep Mode No load 15 μA
1
For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.
TCVO = (VMAX − VMIN)/VO(TMAX − TMIN)
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.

ELECTRICAL CHARACTERISTICS—REF194 @ −40°C ≤ TA ≤ +125°C

@ VS = 5.0 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 13.
Parameter Mnemonic Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT 1, 2
E Grade TCVO/°C IOUT = 0 mA 2 ppm/°C
F Grade 5 ppm/°C
G Grade 3 10 ppm/°C
LINE REGULATION 4
E Grade ΔVO/ΔVIN 4.75 V ≤ VS ≤ 15 V, IOUT = 0 mA 5 ppm/V
F and G Grades 10 ppm/V
LOAD REGULATION
E Grade ΔVO/ΔVLOAD VS = 5.80 V, 0 mA ≤ IOUT ≤ 20 mA 5 ppm/mA
F and G Grades 10 ppm/mA
DROPOUT VOLTAGE V S − VO VS = 5.10 V, ILOAD = 10 mA 0.60 V
VS = 5.95 V, ILOAD = 20 mA 1.45 V
1
For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.
TCVO = (VMAX − VMIN)/VO(TMAX − TMIN)
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.

Rev. I | Page 9 of 28
REF19x Series
ELECTRICAL CHARACTERISTICS—REF195 @ TA = 25°C
@ VS = 5.10 V, TA = 25°C, unless otherwise noted.
Table 14.
Parameter Mnemonic Condition Min Typ Max Unit
INITIAL ACCURACY 1
E Grade VO IOUT = 0 mA 4.998 5.0 5.002 V
F Grade 4.995 5.005 V
G Grade 4.990 5.010 V
LINE REGULATION 2
E Grade ΔVO/ΔVIN 5.10 V ≤ VS ≤ 15 V, IOUT = 0 mA 2 4 ppm/V
F and G Grades 4 8 ppm/V
LOAD REGULATION2
E Grade ΔVO/ΔVLOAD VS = 6.30 V, 0 mA ≤ IOUT ≤ 30 mA 2 4 ppm/mA
F and G Grades 4 8 ppm/mA
DROPOUT VOLTAGE V S − VO VS = 5.50 V, ILOAD = 10 mA 0.50 V
VS = 6.30 V, ILOAD = 30 mA 1.30 V
LONG-TERM STABILITY 3 DVO 1000 hours @ 125°C 1.2 mV
NOISE VOLTAGE eN 0.1 Hz to 10 Hz 50 μV p-p
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term stability specification is noncumulative. The drift in subsequent 1000-hour periods is significantly lower than in the first 1000-hour period.

ELECTRICAL CHARACTERISTICS—REF195 @ −40°C ≤ TA ≤ +85°C

@ VS = 5.15 V, −40°C ≤ TA ≤ +85°C, unless otherwise noted.
Table 15.
Parameter Mnemonic Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT 1,2
E Grade TCVO/°C IOUT = 0 mA 2 5 ppm/°C
F Grade 5 10 ppm/°C
G Grade 3 10 25 ppm/°C
LINE REGULATION 4
E Grade ΔVO/ΔVIN 5.15 V ≤ VS ≤ 15 V, IOUT = 0 mA 5 10 ppm/V
F and G Grades 10 20 ppm/V
LOAD REGULATION4
E Grade ΔVO/ΔVLOAD VS = 6.30 V, 0 mA ≤ IOUT ≤ 25 mA 5 10 ppm/mA
F and G Grades 10 20 ppm/mA
DROPOUT VOLTAGE V S − VO VS = 5.50 V, ILOAD = 10 mA 0.50 V
VS = 6.30 V, ILOAD = 25 mA 1.30 V
SLEEP PIN
Logic High Input Voltage VH 2.4 V
Logic High Input Current IH −8 μA
Logic Low Input Voltage VL 0.8 V
Logic Low Input Current IL −8 μA
SUPPLY CURRENT No load 45 μA
Sleep Mode No load 15 μA
1
For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.
TCVO = (VMAX − VMIN)/VO(TMAX − TMIN)
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.

Rev. I | Page 10 of 28
 REF19x Series

ELECTRICAL CHARACTERISTICS—REF195 @ −40°C ≤ TA ≤ +125°C

@ VS = 5.20 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 16.
Parameter Mnemonic Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT 1, 2
E Grade TCVO/°C IOUT = 0 mA 2 ppm/°C
F Grade 5 ppm/°C
G Grade 3 10 ppm/°C
LINE REGULATION 4
E Grade ΔVO/ΔVIN 5.20 V ≤ VS ≤ 15 V, IOUT = 0 mA 5 ppm/V
F and G Grades 10 ppm/V
LOAD REGULATION4
E Grade ΔVO/ΔVLOAD VS = 6.45 V, 0 mA ≤ IOUT ≤ 20 mA 5 ppm/mA
F and G Grades 10 ppm/mA
DROPOUT VOLTAGE VS − VO VS = 5.60 V, ILOAD = 10 mA 0.60 V
VS = 6.45 V, ILOAD = 20 mA 1.45 V
1
For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.
TCVO = (VMAX − VMIN)/VO(TMAX − TMIN)
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.

ELECTRICAL CHARACTERISTICS—REF196 @ TA = 25°C

@ VS = 3.5 V, TA = 25°C, unless otherwise noted.
Table 17.
Parameter Mnemonic Condition Min Typ Max Unit
INITIAL ACCURACY 1
G Grade VO IOUT = 0 mA 3.290 3.3 3.310 V
LINE REGULATION 2
G Grade ΔVO/ΔVIN 3.50 V ≤ VS ≤ 15 V, IOUT = 0 mA 4 8 ppm/V
LOAD REGULATION2
G Grade ΔVO/ΔVLOAD VS = 5.0 V, 0 mA ≤ IOUT ≤ 30 mA 6 15 ppm/mA
DROPOUT VOLTAGE V S − VO VS = 4.1 V, ILOAD = 10 mA 0.80 V
VS = 4.3 V, ILOAD = 30 mA 1.00 V
LONG-TERM STABILITY 3 DVO 1000 hours @ 125°C 1.2 mV
NOISE VOLTAGE eN 0.1 Hz to 10 Hz 33 μV p-p
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term stability specification is noncumulative. The drift in subsequent 1000-hour periods is significantly lower than in the first 1000-hour period.

Rev. I | Page 11 of 28
REF19x Series
ELECTRICAL CHARACTERISTICS—REF196 @ −40°C ≤ TA ≤ +85°C
@ VS = 3.5 V, –40°C ≤ TA ≤ +85°C, unless otherwise noted.
Table 18.
Parameter Mnemonic Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT 1, 2
G Grade 3 TCVO/°C IOUT = 0 mA 10 25 ppm/°C
LINE REGULATION 4
G Grade ΔVO/ΔVIN 3.5 V ≤ VS ≤ 15 V, IOUT = 0 mA 10 20 ppm/V
LOAD REGULATION4
G Grade ΔVO/ΔVLOAD VS = 5.0 V, 0 mA ≤ IOUT ≤ 25 mA 10 20 ppm/mA
DROPOUT VOLTAGE V S − VO VS = 4.1 V, ILOAD = 10 mA 0.80 V
VS = 4.3 V, ILOAD = 25 mA 1.00 V
SLEEP PIN
Logic High Input Voltage VH 2.4 V
Logic High Input Current IH −8 μA
Logic Low Input Voltage VL 0.8 V
Logic Low Input Current IL −8 μA
SUPPLY CURRENT No load 45 μA
Sleep Mode No load 15 μA
1
For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.
TCVO = (VMAX − VMIN)/VO(TMAX − TMIN)
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.

ELECTRICAL CHARACTERISTICS—REF196 @ −40°C ≤ TA ≤ +125°C

@ VS = 3.50 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 19.
Parameter Mnemonic Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT 1, 2
G Grade 3 TCVO/°C IOUT = 0 mA 10 ppm/°C
LINE REGULATION 4
G Grade ΔVO/ΔVIN 3.50 V ≤ VS ≤ 15 V, IOUT = 0 mA 20 ppm/V
LOAD REGULATION4
G Grade ΔVO/ΔVLOAD VS = 5.0 V, 0 mA ≤ IOUT ≤ 20 mA 20 ppm/mA
DROPOUT VOLTAGE V S − VO VS = 4.1 V, ILOAD = 10 mA 0.80 V
VS = 4.4 V, ILOAD = 20 mA 1.10 V
1
For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.
TCVO = (VMAX − VMIN)/VO(TMAX − TMIN)
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.

Rev. I | Page 12 of 28
 REF19x Series
ELECTRICAL CHARACTERISTICS—REF198 @ TA = 25°C
@ VS = 5.0 V, TA = 25°C, unless otherwise noted.
Table 20.
Parameter Mnemonic Condition Min Typ Max Unit
INITIAL ACCURACY 1
E Grade VO IOUT = 0 mA 4.094 4.096 4.098 V
F Grade 4.091 4.101 V
G Grade 4.086 4.106 V
LINE REGULATION 2
E Grade ΔVO/ΔVIN 4.5 V ≤ VS ≤ 15 V, IOUT = 0 mA 2 4 ppm/V
F and G Grades 4 8 ppm/V
LOAD REGULATION2
E Grade ΔVO/ΔVLOAD VS = 5.4 V, 0 mA ≤ IOUT ≤ 30 mA 2 4 ppm/mA
F and G Grades 4 8 ppm/mA
DROPOUT VOLTAGE V S − VO VS = 4.6 V, ILOAD = 10 mA 0.502 V
VS = 5.4 V, ILOAD = 30 mA 1.30 V
LONG-TERM STABILITY 3 DVO 1000 hours @ 125°C 1.2 mV
NOISE VOLTAGE eN 0.1 Hz to 10 Hz 40 μV p-p
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term stability specification is noncumulative. The drift in subsequent 1000-hour periods is significantly lower than in the first 1000-hour period.

ELECTRICAL CHARACTERISTICS—REF198 @ −40°C ≤ TA ≤ +85°C

@ VS = 5.0 V, −40°C ≤ TA ≤ +85°C, unless otherwise noted.
Table 21.
Parameter Mnemonic Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT 1, 2
E Grade TCVO/°C IOUT = 0 mA 2 5 ppm/°C
F Grade 5 10 ppm/°C
G Grade 3 10 25 ppm/°C
LINE REGULATION 4
E Grade ΔVO/ΔVIN 4.5 V ≤ VS ≤ 15 V, IOUT = 0 mA 5 10 ppm/V
F and G Grades 10 20 ppm/V
LOAD REGULATION4
E Grade ΔVO/ΔVLOAD VS = 5.4 V, 0 mA ≤ IOUT ≤ 25 mA 5 10 ppm/mA
F and G Grades 10 20 ppm/mA
DROPOUT VOLTAGE V S − VO VS = 4.6 V, ILOAD = 10 mA 0.502 V
VS = 5.4 V, ILOAD = 25 mA 1.30 V
SLEEP PIN
Logic High Input Voltage VH 2.4 V
Logic High Input Current IH −8 μA
Logic Low Input Voltage VL 0.8 V
Logic Low Input Current IL −8 μA
SUPPLY CURRENT No load 45 μA
Sleep Mode No load 15 μA
1
For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.
TCVO = (VMAX − VMIN)/VO(TMAX − TMIN)
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.

Rev. I | Page 13 of 28
REF19x Series
ELECTRICAL CHARACTERISTICS—REF198 @ −40°C ≤ TA ≤ +125°C
@ VS = 5.0 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 22.
Parameter Mnemonic Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT 1, 2
E Grade TCVO/°C IOUT = 0 mA 2 ppm/°C
F Grade 5 ppm/°C
G Grade 3 10 ppm/°C
LINE REGULATION 4
E Grade ΔVO/ΔVIN 4.5 V ≤ VS ≤ 15 V, IOUT = 0 mA 5 ppm/V
F and G Grades 10 ppm/V
LOAD REGULATION4
E Grade ΔVO/ΔVLOAD VS = 5.6 V, 0 mA ≤ IOUT ≤ 20 mA 5 ppm/mA
F and G Grades 10 ppm/mA
DROPOUT VOLTAGE V S − VO VS = 4.7 V, ILOAD = 10 mA 0.60 V
VS = 5.6 V, ILOAD = 20 mA 1.50 V
1
For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.
TCVO = (VMAX − VMIN)/VO(TMAX − TMIN)
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.

WAFER TEST LIMITS

For proper operation, a 1 μF capacitor is required between the output pins and the GND pin of the REF19x. Electrical tests and wafer
probe to the limits are shown in
Table 23. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice.
Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
@ ILOAD = 0 mA, TA = 25°C, unless otherwise noted.
Table 23.
Parameter Mnemonic Condition Limit Unit
INITIAL ACCURACY
REF191 VO 2.043/2.053 V
REF192 2.495/2.505 V
REF193 2.990/3.010 V
REF194 4.495/4.505 V
REF195 4.995/5.005 V
REF196 3.290/3.310 V
REF198 4.091/4.101 V
LINE REGULATION ΔVO/ΔVIN (VO + 0.5 V) < VIN < 15 V, IOUT = 0 mA 15 ppm/V
LOAD REGULATION ΔVO/ΔILOAD 0 mA < ILOAD < 30 mA, VIN = (VO + 1.3 V) 15 ppm/mA
DROPOUT VOLTAGE VO − V+ ILOAD = 10 mA 1.25 V
ILOAD = 30 mA 1.55 V
SLEEP MODE INPUT
Logic Input High VIH 2.4 V
Logic Input Low VIL 0.8 V
SUPPLY CURRENT VIN = 15 V No load 45 μA
Sleep Mode No load 15 μA

Rev. I | Page 14 of 28
 REF19x Series

ABSOLUTE MAXIMUM RATINGS

Table 24.
Parameter 1 Rating THERMAL RESISTANCE
Supply Voltage −0.3 V, +18 V
θJA is specified for the worst-case conditions, that is, a device
Output to GND −0.3 V, VS + 0.3 V
soldered in a circuit board for surface-mount packages.
Output to GND Short-Circuit Duration Indefinite
Storage Temperature Range Table 25. Thermal Resistance
PDIP, SOIC_N Package −65°C to +150°C Package Type θJA 1 θJC Unit
Operating Temperature Range 8-Lead PDIP 103 43 °C/W
REF19x −40°C to +85°C 8-Lead SOIC_N 158 43 °C/W
Junction Temperature Range
1
PDIP, SOIC_N Package −65°C to +150°C θJA is specified for worst-case conditions; that is, θJA is specified for the device
in socket for PDIP and is specified for the device soldered in the circuit board
Lead Temperature Range (Soldering 60 sec) 300°C for the SOIC package.
1
Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Rev. I | Page 15 of 28
REF19x Series

TYPICAL PERFORMANCE CHARACTERISTICS

5.004 50
3 TYPICAL PARTS BASED ON 600
5.15V < VIN < 15V 45 UNITS, 4 RUNS
5.003
–40°C ≤ TA ≤ +85°C
40
5.002

PERCENTAGE OF PARTS
35
OUTPUT VOLTAGE (V)

5.001
30

5.000 25

20
4.999
15
4.998
10
4.997
5

4.996 0

00371-003

00371-006
–50 –25 0 25 50 75 100 20 15 10 5 0 5 10 15 20
TEMPERATURE (°C) TC—VOUT (ppm/°C)

Figure 3. REF195 Output Voltage vs. Temperature Figure 6. TC—VOUT Distribution

32 40
5.15V ≤ VS ≤ 15V

28 35
NORMAL MODE
24 30
LOAD REGULATION (ppm/V)

SUPPLY CURRENT (µA)

–40°C
20 25

16 20
+25°C
12 15
+85°C

8 10

4 5
SLEEP MODE
0 0

00371-007
00371-004

0 5 10 15 20 25 30 –50 –25 0 25 50 75 100

ILOAD (mA) TEMPERATURE (°C)

Figure 4. REF195 Load Regulator vs. ILOAD Figure 7. Supply Current vs. Temperature

20 –6
0mA ≤ IOUT ≤ 25mA

+85°C –5
16
LINE REGULATION (ppm/mA)

SLEEP PIN CURRENT (µA)

+25°C –4
12
–40°C
–3

8
–2
VL
4
–1 VH

0 0
00371-008
00371-005

4 6 8 10 12 14 16 –50 –25 0 25 50 75 100

VIN (V) TEMPERATURE (°C)

Figure 5. REF195 Line Regulator vs. VIN Figure 8. SLEEP Pin Current vs. Temperature

Rev. I | Page 16 of 28
 REF19x Series
REF19x
VIN = 15V 2
0 6
4 10mA

00371-013
1µF
–20 0
RIPPLE REJECTION (dB)

–40 Figure 13. Load Transient Response Measurement Circuit

–60

–80
2V
100%
–100
90%
–120

00371-009
10 100 1k 10k 100k 1M
FREQUENCY (Hz)

Figure 9. Ripple Rejection vs. Frequency

1mA
LOAD
10µF
30mA
LOAD
10%
1kΩ REF19x 10µF
0%
VIN = 15V 2 6 OUTPUT

00371-014
4 2V 100µs
10µF 1µF 1kΩ
00371-010

REF

Figure 10. Ripple Rejection vs. Frequency Measurement Circuit Figure 14. Power-On Response Time

VIN = 7V REF19x 200V

2 6
REF19x
2
4 VG = 2V p-p 6
VIN = 7V 4

00371-015
1µF 1µF VS = 4V 1µF
Z

Figure 15. Power-On Response Time Measurement Circuit

ZO (Ω)

3 5V
ON 100%
2
90%
1 OFF

0
00371-011

10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 11. Output Impedance vs. Frequency

IL = 1mA
VOUT
IL = 10mA
5V
OFF 100% 10%

90% 0%
ON
1V 2ms
00371-016

Figure 16. SLEEP Response Time

VIN = 15V REF19x

2 VOUT
6
10% 3
1µF
00371-017

4
0%
00371-012

20mV 100µs

Figure 12. Load Transient Response Figure 17. SLEEP Response Time Measurement Circuit

Rev. I | Page 17 of 28
REF19x Series
35
5V
100% 30
90%

25

LOAD CURRENT (mA)

20

15

10

10%
5
0%

00371-018
200mV 200µs
0

00371-019
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
REF195 DROPOUT VOLTAGE (V)

Figure 18. Line Transient Response Figure 19. Load Current vs. Dropout Voltage

Rev. I | Page 18 of 28
 REF19x Series

APPLICATIONS
OUTPUT SHORT-CIRCUIT BEHAVIOR SLEEP MODE OPERATION
The REF19x family of devices is completely protected from All REF19x devices include a sleep capability that is
damage due to accidental output shorts to GND or to V+. In the TTL/CMOS-level compatible. Internally, a pull-up current
event of an accidental short-circuit condition, the reference source to VIN is connected at the SLEEP pin. This permits the
device shuts down and limits its supply current to 40 mA. SLEEP pin to be driven from an open collector/drain driver. A
V+ logic low or a 0 V condition on the SLEEP pin is required to
turn off the output stage. During sleep, the output of the
references becomes a high impedance state where its potential
VOUT would then be determined by external circuitry. If the sleep
feature is not used, it is recommended that the SLEEP pin be
connected to VIN (Pin 2).
SLEEP (SHUTDOWN)
BASIC VOLTAGE REFERENCE CONNECTIONS
The circuit in Figure 21 illustrates the basic configuration for
the REF19x family of references. Note the 10 μF/0.1 μF bypass
network on the input and the 1 μF/0.1 μF bypass network on
00371-020

GND the output. It is recommended that no connections be made to

Figure 20. Simplified Schematic Pin 1, Pin 5, Pin 7, and Pin 8. If the sleep feature is not required,
Pin 3 should be connected to VIN.
DEVICE POWER DISSIPATION CONSIDERATIONS
REF19x
The REF19x family of references is capable of delivering load NC 1 8 NC
currents to 30 mA with an input voltage that ranges from VIN
2 7 NC
3.3 V to 5 V. When these devices are used in applications with 10µF 0.1µF
SLEEP 3 6
OUTPUT
+
large input voltages, exercise care to avoid exceeding the 4 5 NC
1µF 0.1µF

00371-021
TANT
maximum internal power dissipation of these devices.
NC = NO CONNECT
Exceeding the published specifications for maximum power
Figure 21. Basic Voltage Reference Configuration
dissipation or junction temperature can result in premature
device failure. The following formula should be used to MEMBRANE SWITCH-CONTROLLED POWER
calculate a device’s maximum junction temperature or SUPPLY
dissipation:
With output load currents in the tens of mA, the REF19x family
TJ − TA of references can operate as a low dropout power supply in
PD =
θ JA hand-held instrument applications. In the circuit shown in
Figure 22, a membrane on/off switch is used to control the
In this equation, TJ and TA are the junction and ambient operation of the reference. During an initial power-on condition,
temperatures, respectively; PD is the device power dissipation; the SLEEP pin is held to GND by the 10 kΩ resistor. Recall that
and θJA is the device package thermal resistance.
this condition (read: three-state) disables the REF19x output.
OUTPUT VOLTAGE BYPASSING When the membrane on switch is pressed, the SLEEP pin is
For stable operation, low dropout voltage regulators and momentarily pulled to VIN, enabling the REF19x output. At this
references generally require a bypass capacitor connected from point, current through the 10 kΩ resistor is reduced, and the
their VOUT pins to their GND pins. Although the REF19x family internal current source connected to the SLEEP pin takes
of references is capable of stable operation with capacitive loads control. Pin 3 assumes and remains at the same potential as VIN.
exceeding 100 μF, a 1 μF capacitor is sufficient to guarantee When the membrane off switch is pressed, the SLEEP pin is
rated performance. The addition of a 0.1 μF ceramic capacitor momentarily connected to GND, which once again disables the
in parallel with the bypass capacitor improves load current REF19x output.
transient performance. For best line voltage transient
performance, it is recommended that the voltage inputs of these
devices be bypassed with a 10 μF electrolytic capacitor in
parallel with a 0.1 μF ceramic capacitor.

Rev. I | Page 19 of 28
REF19x Series
REF19x The requirement for a heat sink on Q1 depends on the maximum
NC 1 8 NC input voltage and short-circuit current. With VS = 5 V and a 300
VIN
2 7 NC mA current limit, the worst-case dissipation of Q1 is 1.5 W, less
1kΩ OUTPUT
5%
3 6
+1µF
than the TO-220 package 2 W limit. However, if smaller TO-39
ON
4 5 NC TANT or TO-5 packaged devices, such as the 2N4033, are used, the
current limit should be reduced to keep maximum dissipation
10kΩ
below the package rating. This is accomplished by simply

00371-022
OFF
NC = NO CONNECT raising R4.
Figure 22. Membrane Switch-Controlled Power Supply A tantalum output capacitor is used at C1 for its low equivalent
series resistance (ESR), and the higher value is required for
CURRENT-BOOSTED REFERENCES WITH stability. Capacitor C2 provides input bypassing and can be an
CURRENT LIMITING ordinary electrolytic.
While the 30 mA rated output current of the REF19x series is Shutdown control of the booster stage is an option, and when
higher than is typical of other reference ICs, it can be boosted to used, some cautions are needed. Due to the additional active
higher levels, if desired, with the addition of a simple external devices in the VS line to U1, a direct drive to Pin 3 does not
PNP transistor, as shown in Figure 23. Full-time current work as with an unbuffered REF19x device. To enable shutdown
limiting is used to protect the pass transistor against shorts. control, the connection from U1 to U2 is broken at the X, and
+VS = 6V Q1 OUTPUT TABLE
TO 9V R4
Diode D1 then allows a CMOS control source, VC, to drive U1
TIP32A
(SEE TEXT) U1 VOUT (V)
2Ω (SEE TEXT) to U3 for on/off operation. Startup from shutdown is not as
REF192 2.5
R1 clean under heavy load as it is in basic REF19x series, and can
REF193 3.0
Q2 1kΩ
REF196 3.3
2N3906 REF194 4.5
require several milliseconds under load. Nevertheless, it is still
C2 + R2
100µF 1.5kΩ REF195 5.0 effective and can fully control 150 mA loads. When shutdown
25V
control is used, heavy capacitive loads should be minimized.
2 C3 F
D1 U1 0.1µF +VOUT
VC 3 REF196 6
S
3.3V
NEGATIVE PRECISION REFERENCE WITHOUT
1N4148 (SEE TABLE)
C1
@ 150mA PRECISION RESISTORS
(SEE TEXT 4
10µF/25V
R3 +
ON SLEEP)
1.82kΩ (TANTALUM) R1 In many current-output CMOS DAC applications where the
S output signal voltage must be the same polarity as the reference
VOUT voltage, it is often necessary to reconfigure a current-switching
00371-023

VS F COMMON
COMMON DAC into a voltage-switching DAC using a 1.25 V reference, an
Figure 23. Boosted 3.3 V Referenced with Current Limiting op amp, and a pair of resistors. Using a current-switching DAC
directly requires an additional operational amplifier at the
In this circuit, the power supply current of reference U1 flowing
output to reinvert the signal. A negative voltage reference is
through R1 to R2 develops a base drive for Q1, whose collector
then desirable, because an additional operational amplifier is
provides the bulk of the output current. With a typical gain of
not required for either reinversion (current-switching mode) or
100 in Q1 for 100 mA to 200 mA loads, U1 is never required to
amplification (voltage-switching mode) of the DAC output
furnish more than a few mA, so this factor minimizes tempera-
voltage. In general, any positive voltage reference can be
ture-related drift. Short-circuit protection is provided by Q2,
converted into a negative voltage reference using an operational
which clamps the drive to Q1 at about 300 mA of load current,
amplifier and a pair of matched resistors in an inverting
with values as shown in Figure 23. With this separation of
configuration. The disadvantage to this approach is that the
control and power functions, dc stability is optimum, allowing
largest single source of error in the circuit is the relative
most advantageous use of premium grade REF19x devices for
matching of the resistors used.
U1. Of course, load management should still be exercised. A
short, heavy, low dc resistance (DCR) conductor should be used The circuit illustrated in Figure 24 avoids the need for tightly
from U1 to U6 to the VOUT Sense Point S, where the collector of matched resistors by using an active integrator circuit. In this
Q1 connects to the load, Point F. circuit, the output of the voltage reference provides the input
drive for the integrator. To maintain circuit equilibrium, the
Because of the current limiting configuration, the dropout
integrator adjusts its output to establish the proper relationship
voltage circuit is raised about 1.1 V over that of the REF19x
between the reference’s VOUT and GND. Thus, any desired
devices, due to the VBE of Q1 and the drop across Current Sense
negative output voltage can be selected by substituting for the
Resistor R4. However, overall dropout is typically still low
appropriate reference IC. The sleep feature is maintained in the
enough to allow operation of a 5 V to 3.3 V regulator/reference
circuit with the simple addition of a PNP transistor and a 10 kΩ
using the REF196 for U1 as noted, with a VS as low as 4.5 V and
resistor.
a load current of 150 mA.

Rev. I | Page 20 of 28
 REF19x Series
One caveat to this approach is that although rail-to-rail output While this concept is simple, some cautions are needed. Since
amplifiers work best in the application, these operational amplifiers the lower reference circuit must sink a small bias current from
require a finite amount (mV) of headroom when required to U2 (50 μA to 100 μA), plus the base current from the series
provide any load current. The choice for the circuit’s negative PNP output transistor in U2, either the external load of U1 or
supply should take this issue into account. R1 must provide a path for this current. If the U1 minimum
VIN load is not well defined, Resistor R1 should be used, set to a
10kΩ
value that conservatively passes 600 μA of current with the
2N3906 applicable VOUT1 across it. Note that the two U1 and U2
SLEEP
2
TTL/CMOS reference circuits are locally treated as macrocells, each having
VIN
1µF its own bypasses at input and output for best stability. Both U1
1kΩ
3 SLEEP VOUT 6 and U2 in this circuit can source dc currents up to their full
+5V
REF19x rating. The minimum input voltage, VS, is determined by the
GND 100Ω
4 1µF A1 –VREF sum of the outputs, VOUT2, plus the dropout voltage of U2.
10kΩ 100kΩ
–5V A related variation on stacking two 3-terminal references is

00371-024
A1 = 1/2 OP295, shown in Figure 26, where U1, a REF192, is stacked with a
1/2 OP291
2-terminal reference diode, such as the AD589. Like the
Figure 24. Negative Precision Voltage Reference Uses No Precision Resistors 3-terminal stacked reference above, this circuit provides two
STACKING REFERENCE ICS FOR outputs, VOUT1 and VOUT2, which are the individual terminal
ARBITRARY OUTPUTS voltages of D1 and U1, respectively. Here this is 1.235 V and 2.5 V,
which provides a VOUT2 of 3.735 V. When using 2-terminal
Some applications may require two reference voltage sources
reference diodes, such as D1, the rated minimum and maximum
that are a combined sum of standard outputs. The circuit shown
device currents must be observed, and the maximum load
in Figure 25 shows how this stacked output reference can be
current from VOUT1 can be no greater than the current setup by
implemented.
R1 and VO (U1). When VO (U1) is equal to 2.5 V, R1 provides a
OUTPUT TABLE
U1/U2 VOUT1 (V) VOUT2 (V)
500 μA bias to D1, so the maximum load current available at
+VS REF192/REF192 2.5 5.0
VOUT1 is 450 μA or less.
VS > VOUT2 + 0.15V REF192/REF194 2.5 7.0 +VS
REF192/REF195 2.5 7.5 VS > VOUT2 + 0.15V
2
U2 2
C1
0.1µF
3 REF19x 6 +VOUT2
(SEE TABLE)
+ C1 U1
VO (U2) 3 6 +VOUT2
4 C2 0.1µF REF192 R1 3.735V
1µF +
4
VO (U1) C2 4.99kΩ
1µF (SEE TEXT)

2 +VOUT1
U1 + C3 1.235V
C3 D1 VO (D1)
0.1µF
3 REF19x 6 +VOUT1 AD589 1µF
(SEE TABLE) + C4 R1 VIN
4 VO (U1) 3.9kΩ COMMON

00371-026
1µF (SEE TEXT)
VIN VOUT
COMMON COMMON
00371-025

VOUT
COMMON
Figure 26. Stacking Voltage References with the REF192
Figure 25. Stacking Voltage References with the REF19x PRECISION CURRENT SOURCE
Two reference ICs are used, fed from a common unregulated In low power applications, the need often arises for a precision
input, VS. The outputs of the individual ICs are connected in current source that can operate on low supply voltages. As shown
series, as shown in Figure 25, which provide two output in Figure 27, any one of the devices in the REF19x family of
voltages, VOUT1 and VOUT2. VOUT1 is the terminal voltage of U1, references can be configured as a precision current source.
while VOUT2 is the sum of this voltage and the terminal voltage The circuit configuration illustrated is a floating current source
of U2. U1 and U2 are chosen for the two voltages that supply with a grounded load. The output voltage of the reference is
the required outputs (see Output Table in Figure 25). If, for bootstrapped across RSET, which sets the output current into the
example, both U1 and U2 are REF192s, the two outputs are 2.5 V load. With this configuration, circuit precision is maintained for
and 5.0 V. load currents in the range from the reference’s supply current
(typically 30 μA) to approximately 30 mA. The low dropout
voltage of these devices maximizes the current source’s output
voltage compliance without excess headroom.

Rev. I | Page 21 of 28
REF19x Series
VIN OUTPUT TABLE
U1/U2 VC* VOUT (V)
REF195/ HI 5.0
2 REF196 LO 3.3
VIN REF194/ HI 4.5
REF195 LO 5.0
REF19x +VS = 6V

3 SLEEP
2 *CMOS LOGIC LEVELS
VREF 6
U1
1µF R1 1 2 3 4
GND VC 3 REF19x 6
4
RSET (SEE TABLE)
ISY U3A U3B
ADJUST P1 4
74HC04 74HC04
+VOUT
VIN ≥ IOUT × RL (MAX) + VSY (MIN) IOUT

VOUT RL 2
IOUT = + ISY (REF19x)
RSET U2 + C2
VOUT E.G., REF195: VOUT = 5V 3 REF19x 6 1µF
>> ISY IOUT = 5mA (SEE TABLE)
RSET

00371-027
R1 = 953Ω C1 4
P1 = 100Ω, 10-TURN 0.1µF
VIN

00371-028
Figure 27. A Low Dropout, Precision Current Source VOUT
COMMON
COMMON
The governing equations for the circuit are Figure 28. Switched Output Reference
VIN = IOUT × RL ( Max ) + VSY (Min, REF 19x ) Using dissimilar REF19x series devices with this configuration
VOUT allows logic selection between the U1/U2-specified terminal
I OUT = + I SY (REF 19x ) voltages. For example, with U1 (a REF195) and U2 (a REF196),
RSET
as noted in the table in Figure 28, changing the CMOS-
VOUT
〉〉 I SY (REF 19x ) compatible VC logic control voltage from HI to LO selects
RSET between a nominal output of 5 V and 3.3 V, and vice versa.
Other REF19x family units can also be used for U1/U2, with
SWITCHED OUTPUT 5 V/3.3 V REFERENCE
similar operation in a logic sense, but with outputs as per the
Applications often require digital control of reference voltages, individual paired devices (see the table in Figure 28). Of course,
selecting between one stable voltage and a second. With the the exact output voltage tolerance, drift, and overall quality of
sleep feature inherent to the REF19x series, switched output the reference voltage is consistent with the grade of individual
reference configurations are easily implemented with little U1 and U2 devices.
additional hardware.
Due to the nature of the wire-OR, one application caveat should
The circuit in Figure 28 illustrates the general technique, which be understood about this circuit. Since U1 and U2 can only
takes advantage of the output wire-OR capability of the REF19x source current effectively, negative going output voltage
device family. When off, a REF19x device is effectively an open changes, which require the sinking of current, necessarily takes
circuit at the output node with respect to the power supply. longer than positive going changes. In practice, this means that
When on, a REF19x device can source current up to its current the circuit is quite fast when undergoing a transition from 3.3 V
rating, but sink only a few μA (essentially, just the relatively low to 5 V, but the transition from 5 V to 3.3 V takes longer. Exactly
current of the internal output scaling divider). Consequently, how much longer is a function of the load resistance, RL, seen at
when two devices are wired together at their common outputs, the output and the typical 1 μF value of C2. In general, a
the output voltage is the same as the output voltage for the on conservative transition time is approximately several milliseconds
device. The off state device draws a small standby current of for load resistances in the range of 100 Ω to 1 kΩ. Note that for
15 μA (max), but otherwise does not interfere with operation of highest accuracy at the new output voltage, several time
the on device, which can operate to its full current rating. Note constants should be allowed (>7.6 time constants for <1/2 LSB
that the two devices in the circuit conveniently share both input error @ 10 bits, for example).
and output capacitors, and with CMOS logic drive, it is power
efficient. KELVIN CONNECTIONS
In many portable applications where the PC board cost and area
go hand-in-hand, circuit interconnects are very often narrow.
These narrow lines can cause large voltage drops if the voltage
reference is required to provide load currents to various
functions. The interconnections of a circuit can exhibit a typical
line resistance of 0.45 mΩ/square (1 oz. Cu, for example).

Rev. I | Page 22 of 28
 REF19x Series
In applications where these devices are configured as low The circuit in Figure 30 illustrates this concept, which borrows
dropout voltage regulators, these wiring voltage drops can from the switched output idea of Figure 28, again using the
become a large source of error. To circumvent this problem, REF19x device family output wire-OR capability. In this case,
force and sense connections can be made to the reference since a constant 5 V reference voltage is desired for all
through the use of an operational amplifier, as shown in Figure 29. conditions, two REF195 devices are used for U1 and U2, with
This method provides a means by which the effects of wiring their on/off switching controlled by the presence or absence of
resistance voltage drops can be eliminated. Load currents flowing the primary dc supply source, VS. VBAT is a 6 V battery backup
through wiring resistance produce an I-R error (ILOAD × RWIRE) at source that supplies power to the load only when VS fails. For
the load. However, the Kelvin connection overcomes the problem normal (VS present) power conditions, VBAT sees only the 15 μA
by including the wiring resistance within the forcing loop of the (maximum) standby current drain of U1 in its off state.
op amp. Because the op amp senses the load voltage, op amp In operation, it is assumed that for all conditions, either U1 or
loop control forces the output to compensate for the wiring U2 is on, and a 5 V reference output is available. With this
error and to produce the correct voltage at the load. Depending voltage constant, a scaled down version is applied to the
on the reference device chosen, operational amplifiers that can Comparator IC U3, providing a fixed 0.5 V input to the negative
be used in this application are the OP295, OP292, and OP183. input for all power conditions. The R1 to R2 divider provides
VIN VIN a signal to the U3 positive input proportionally to VS, which
RLW
2
+VOUT switches U3 and U1/U2, dependent upon the absolute level of
SENSE
VIN 2
RLW VS. In Figure 30, Op Amp U3 is configured as a comparator
1 +VOUT
A1
SLEEP 3 VOUT 6
3 FORCE with hysteresis, which provides clean, noise-free output
REF19x switching. This hysteresis is important to eliminate rapid
GND A1 = 1/2 OP295
switching at the threshold due to VS ripple. Furthermore, the
00371-029

4 1µF 100kΩ 1/2 OP292 RL

OP183 device chosen is the AD820, a rail-to-rail output device. This
Figure 29. A Low Dropout, Kelvin-Connected Voltage Reference device provides HI and LO output states within a few mV of VS,
ground for accurate thresholds, and compatible drive for U2 for
FAIL-SAFE 5 V REFERENCE
all VS conditions. R3 provides positive feedback for circuit
Some critical applications require a reference voltage to be hysteresis, changing the threshold at the positive input as
maintained at a constant voltage, even with a loss of primary a function of the output of U3.
power. The low standby power of the REF19x series and the
switched output capability allow a fail-safe reference
configuration to be implemented rather easily. This reference
maintains a tight output voltage tolerance for either a primary
power source (ac line derived) or a standby (battery derived)
power source, automatically switching between the two as the
power conditions change.
+VBAT
2
+VS C2
0.1µF U1
R1
1.1MΩ R3 R6 3 REF195 6
10MΩ 100Ω Q1 (SEE TABLE)
2N3904 5.000V
4
C1
3 + 7 0.1µF
6
2 – 4 U3 2
AD820 + C3
U2
R2
3 REF195 6 1µF
(SEE TABLE)
100kΩ
R4 4
900kΩ
C4 R5
VS, VBAT 0.1µF 100kΩ
00371-030

VOUT
COMMON COMMON

Figure 30. A Fail-Safe 5 V Reference

Rev. I | Page 23 of 28
REF19x Series
100Ω
For VS levels lower than the lower threshold, U3 output is low;
thus, U2 and Q1 are off while U1 is on. For VS levels higher REF195 10µF
than the upper threshold, the situation reverses, with U1 off and 2 6

both U2 and Q1 on. In the interest of battery power +

4
+
10µF 1µF
conservation, all of the comparison switching circuitry is
powered from VS and is arranged so that when VS fails, the 57kΩ
0.1µF
1%
default output comes from U1.
For the R1 to R3 values, as shown in Figure 30, lower/upper VS 3 + 4

switching thresholds are approximately 5.5 V and 6 V, respectively. 1/4 1 2N2222

OP492
These can be changed to suit other VS supplies, as can the REF19x 0.1µF
10kΩ 2 – 11
1%
devices used for U1 and U2, over a range of 2.5 V to5 V of output.
U3 can operate down to a VS of 3.3 V, which is generally 500Ω
compatible with all REF19x family devices. 0.1%

LOW POWER, STRAIN GAGE CIRCUIT

10kΩ
As shown in Figure 31, the REF19x family of references can be 1% 0.01µF

used in conjunction with low supply voltage operational amplifiers, 20kΩ

1%
such as the OP492 or the OP283, in a self-contained strain gage 20kΩ
13 –
circuit in which the REF195 is used as the core. Other 1/4
14
1%
6 –
OP492 1/4
references can be easily accommodated by changing circuit 12 + 7 OUTPUT
OP492
element values. The references play a dual role, first as the 2.21kΩ 10kΩ 5 +
1%
voltage regulator to provide the supply voltage requirements of
the strain gage and the operational amplifiers, and second as
9 – 20kΩ
a precision voltage reference for the current source used to 1/4 1%
8
stimulate the bridge. A distinct feature of the circuit is that it OP492 20kΩ

00371-031
10 + 1%
can be remotely controlled on or off by digital means via
the SLEEP pin. Figure 31. A Low Power, Strain Gage Circuit

Rev. I | Page 24 of 28
 REF19x Series

OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)

8 5 0.280 (7.11) 5.00 (0.1968)

0.250 (6.35)
1 4.80 (0.1890)
4 0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.100 (2.54) 0.300 (7.62) 8 5
BSC 0.060 (1.52) 0.195 (4.95) 4.00 (0.1574) 6.20 (0.2440)
0.210 (5.33) MAX 3.80 (0.1497) 1 5.80 (0.2284)
0.130 (3.30) 4
MAX 0.115 (2.92)
0.015
0.150 (3.81) (0.38) 0.015 (0.38)
0.130 (3.30) MIN GAUGE
0.115 (2.92) PLANE 0.014 (0.36) 1.27 (0.0500) 0.50 (0.0196)
SEATING BSC 45°
PLANE 0.010 (0.25) 1.75 (0.0688) 0.25 (0.0099)
0.022 (0.56) 0.008 (0.20)
0.25 (0.0098) 1.35 (0.0532)
0.005 (0.13) 0.430 (10.92) 8°
0.018 (0.46) MIN MAX 0.10 (0.0040) 0°
0.014 (0.36)
COPLANARITY 0.51 (0.0201)
0.070 (1.78)
0.10 1.27 (0.0500)
0.31 (0.0122) 0.25 (0.0098)
0.060 (1.52) SEATING 0.40 (0.0157)
0.045 (1.14) PLANE 0.17 (0.0067)

COMPLIANT TO JEDEC STANDARDS MS-001 COMPLIANT TO JEDEC STANDARDS MS-012-A A

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

060506-A
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

070606-A
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 32. 8-Lead Plastic Dual In-Line Package [PDIP] Figure 34. 8-Lead Standard Small Outline Package [SOIC_N]
(N-8) Narrow Body
P-Suffix (R-8)
Dimensions shown in inches and (millimeters) S-Suffix
Dimensions shown in millimeters and (inches)
3.10
3.00
2.90

8 5

4.50
4.40 6.40 BSC
4.30

1 4

PIN 1
0.65 BSC
0.15
1.20
0.05 MAX
8°
0.30 0° 0.75
COPLANARITY SEATING 0.20
0.10 0.19 PLANE 0.60
0.09
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AA

Figure 33. 8-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-8)
Dimensions shown in millimeters

Rev. I | Page 25 of 28
REF19x Series
ORDERING GUIDE
Model Temperature Range Package Description Package Option Minimum Quantities/Reel
REF191ES −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF191ES-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2500
REF191ESZ 1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF191ESZ-REEL1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2500
REF191GP −40°C to +85°C 8-Lead PDIP P-Suffix (N-8)
REF191GPZ1 −40°C to +85°C 8-Lead PDIP P-Suffix (N-8)
REF191GS −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF191GS-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2500
REF191GSZ1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF191GSZ-REEL1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2500
REF192ES −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF192ES-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2500
REF192ES-REEL7 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 1000
REF192ESZ1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF192ESZ-REEL1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2500
REF192ESZ-REEL71 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 1000
REF192FS −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF192FS-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2500
REF192FS-REEL7 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 1000
REF192FSZ1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF192FSZ-REEL1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2500
REF192FSZ-REEL71 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 1000
REF192GP −40°C to +85°C 8-Lead PDIP P-Suffix (N-8)
REF192GPZ1 −40°C to +85°C 8-Lead PDIP P-Suffix (N-8)
REF192GRU −40°C to +85°C 8-Lead TSSOP RU-8
REF192GRU-REEL7 −40°C to +85°C 8-Lead TSSOP RU-8 1000
REF192GRUZ1 −40°C to +85°C 8-Lead TSSOP RU-8
REF192GRUZ-REEL71 −40°C to +85°C 8-Lead TSSOP RU-8 1000
REF192GS −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF192GS-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2500
REF192GS-REEL7 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 1000
REF192GSZ1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF192GSZ-REEL1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2500
REF192GSZ-REEL71 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 1000
REF193GS −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF193GS-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2500
REF193GSZ1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF193GSZ-REEL1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2500
REF194ES −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF194ES-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2500
REF194ESZ1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF194ESZ-REEL1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2500
REF194FS −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF194FSZ1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF194GP −40°C to +85°C 8-Lead PDIP P-Suffix (N-8)
REF194GPZ1 −40°C to +85°C 8-Lead PDIP P-Suffix (N-8)
REF194GS −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF194GS-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2500
REF194GS-REEL7 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 1000
REF194GSZ1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF194GSZ-REEL1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2500

Rev. I | Page 26 of 28
 REF19x Series
Model Temperature Range Package Description Package Option Minimum Quantities/Reel
REF194GSZ-REEL71 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 1000
REF195ES −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF195ES-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2500
REF195ESZ1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF195ESZ-REEL1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2500
REF195FS −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF195FS-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2500
REF195FSZ1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF195FSZ-REEL1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2500
REF195GP −40°C to +85°C 8-Lead PDIP P-Suffix (N-8)
REF195GPZ1 −40°C to +85°C 8-Lead PDIP P-Suffix (N-8)
REF195GRU −40°C to +85°C 8-Lead TSSOP RU-8
REF195GRU-REEL7 −40°C to +85°C 8-Lead TSSOP RU-8 1000
REF195GRUZ1 −40°C to +85°C 8-Lead TSSOP RU-8
REF195GRUZ-REEL71 −40°C to +85°C 8-Lead TSSOP RU-8 1000
REF195GS −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF195GS-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2500
REF195GS-REEL7 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 1000
REF195GSZ1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF195GSZ-REEL1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2500
REF195GSZ-REEL71 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 1000
REF196GRU-REEL7 −40°C to +85°C 8-Lead TSSOP RU-8 1000
REF196GRUZ-REEL71 −40°C to +85°C 8-Lead TSSOP RU-8 1000
REF196GS −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF196GS-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2500
REF196GSZ1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF196GSZ-REEL1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2500
REF196GSZ-REEL71 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 1000
REF198ES −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF198ES-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2500
REF198ESZ1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF198ESZ-REEL1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2500
REF198ESZ-REEL71 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 1000
REF198FS −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF198FS-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2500
REF198FSZ1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF198FSZ-REEL1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2500
REF198GP −40°C to +85°C 8-Lead PDIP P-Suffix (N-8)
REF198GPZ1 −40°C to +85°C 8-Lead PDIP P-Suffix (N-8)
REF198GRU −40°C to +85°C 8-Lead TSSOP RU-8
REF198GRU-REEL7 −40°C to +85°C 8-Lead TSSOP RU-8 1000
REF198GRUZ1 −40°C to +85°C 8-Lead TSSOP RU-8
REF198GRUZ-REEL71 −40°C to +85°C 8-Lead TSSOP RU-8 2500
REF198GS −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF198GS-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2500
REF198GSZ1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF198GSZ-REEL1 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2500
1
Z = Pb-free part.

Rev. I | Page 27 of 28
REF19x Series

NOTES

©2006 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners
C00371-0-10/06(I)

Rev. I | Page 28 of 28