ROUTING

in VLSI Physical Design

A Complete, Beginner-Friendly, In-Depth Guide

From fundamentals to industry terminology — every concept explained from first principles
Table of Contents
1. Where Routing Fits in Chip Design
2. Introduction to Routing
3. Goals of Routing
4. Checks Before Routing
5. Inputs for Routing
6. Routing Methodologies
7. Routing Constraints
8. Intermediate Steps of Routing
9. Types of Routing
10. Filler Cells
11. Outputs of Routing
12. Checks After Routing
13. Timing Violations: Setup and Hold
14. Glossary of Key Terms
15. Closing Summary
How to Read This Guide
This guide explains the Routing stage of VLSI physical design (backend chip design) from the ground up. If
you are new to chip design, read Chapters 1 and 2 first — they build the mental model everything else
depends on. If you already understand placement and clock tree synthesis (CTS), you can jump straight to
Chapter 3.

Every technical term is introduced with a plain-language explanation before it is used formally. A full
Glossary is provided at the end for quick reference.

1. Where Routing Fits in Chip Design

Before we can understand routing, we need to understand what happens before it. Building a chip is a bit
like building a city: you don't just start laying roads — you first decide what buildings exist, where they go,
and how the city's power grid works. Chip design follows a similar sequence, called the physical design (or
"PnR" — Place and Route) flow.

1.1 The Journey from Idea to Silicon (Simplified)

• RTL (Register Transfer Level): Engineers describe the chip's behavior in a hardware description
language (like Verilog). This is like an architect's functional brief — "this block should add two numbers
and store the result."
• Synthesis: A tool translates that RTL description into a netlist — a list of logic gates (called standard
cells) and the wires that should connect them, based on a specific manufacturing technology.
• Floorplanning: The chip's overall area is defined, and large blocks (macros, like memories) are given
rough positions — similar to deciding which city blocks are parks, which are residential, and which are
commercial.
• Placement: Every individual standard cell (a single logic gate, like an AND gate or a flip-flop) is given an
exact (x, y) position inside the floorplan — like assigning every building its own street address.
• Clock Tree Synthesis (CTS): The clock signal — the "heartbeat" that keeps every flip-flop in the chip
synchronized — is distributed to every sequential cell through a carefully balanced tree of wires and
buffers, so the clock arrives at (almost) the same time everywhere.
• Routing: This is our topic. Now that every cell has a fixed location, the physical wires that connect
them — exactly as described in the netlist — are drawn on the chip using metal layers and vias.
• Signoff: Final checks confirm the chip will work correctly, meet timing, and can be manufactured
without defects.

Think of it this way:

Placement decides where every house sits on a plot of land. Routing decides exactly how the roads, water
pipes, and power lines connect every house together, following the city planner's wiring diagram (the netlist)
to the letter.
2. Introduction to Routing

2.1 What Exactly Is Routing?

Routing is the physical design stage where the exact paths for interconnecting standard cells, macros, and
I/O (input/output) pins are determined and physically drawn onto the chip layout.

In simpler terms: the netlist (produced back in synthesis) is a logical wiring list — it says "output pin A of cell
1 must connect to input pin B of cell 2," but it says nothing about how that connection should physically
look. Placement already told us where cell 1 and cell 2 physically sit on the chip. Routing's job is to draw the
actual wire between them.

2.2 Metals and Vias: The Physical Building Blocks

A chip is built in layers, like a multi-story parking garage stacked on top of the silicon where the transistors
live. Each "floor" above the transistors is a metal layer — a sheet of conductive metal (typically copper or
aluminum) where wires can be drawn.

• Metal layers: Modern chips have anywhere from 5 to 15+ metal layers, numbered M1 (closest to the
transistors) upward. Lower layers are thin and narrow, used for tight local connections; higher layers
are thicker and wider, used for longer-distance or power connections.
• Vias: A via is a small vertical connector — like an elevator shaft — that connects a wire on one metal
layer to a wire on the layer directly above or below it. Whenever a signal needs to change floors
(layers), it must pass through a via.
So, physically, a "wire" connecting two cells is rarely a single straight line. It is usually a sequence of
horizontal and vertical metal segments on different layers, stitched together by vias, forming a path from
the source pin to the destination pin(s).

2.3 Why This Is Hard

A modern chip can have tens of millions of individual nets (a net = one logical connection point that may fan
out to several destinations) that all need to be routed simultaneously, in a finite amount of physical space,
without any two independent wires ever touching (a "short"), while also satisfying timing, power, and
manufacturing rules. This is why routing is handled by specialized software (the "router") using multiple
structured stages, which we will walk through in this guide.
3. Goals of Routing
A router doesn't just need to "connect the dots." It needs to do so while balancing several competing
objectives. Here is what it is optimizing for, and why each goal matters.

• Minimize total interconnect/wire length: Shorter wires use less metal (cheaper, less congestion), have
lower resistance and capacitance, and therefore switch faster and use less power. Every unnecessary
inch of wire is a small tax on speed, power, and area.
• Minimize the critical path delay: The critical path is the single slowest chain of logic and wiring in the
whole chip — it determines the maximum speed (clock frequency) the chip can run at. Even if every
other path is fast, the chip is only as fast as its slowest path, so routing pays special attention to the
wires on this path.
• Make connections with minimum detours: A detour is when a wire has to zig-zag around an obstacle
instead of taking a direct path. Detours add length, delay, and congestion — so the router tries to
route as directly as possible.
• Route with minimum antenna violations: During manufacturing, a long isolated metal wire connected
to a transistor's gate (but not yet to its final protective diode) can act like a tiny antenna. It collects
stray electrical charge from plasma-based manufacturing processes, and if that charge has nowhere to
go, it can build up and physically damage the delicate transistor gate oxide before the chip is even
finished. Antenna-aware routing avoids creating such exposed long wires (or adds protection diodes /
uses jumpers to break up long single-layer runs).
• Route with power awareness: Routing decisions affect how much current a wire carries and how
much voltage drop occurs along it (IR drop), as well as electromigration (EM) risk — the gradual
physical wearing away of a wire from carrying too much current for too long, similar to water erosion
in a pipe. Power-aware routing avoids overloading thin wires.
• Meet the Timing DRCs and obtain a good Timing QoR: DRC stands for Design Rule Check — the set of
manufacturing-driven geometric rules a layout must obey (minimum spacing, minimum width, etc.).
"Timing DRCs" here refers to electrical/timing-related rules such as maximum transition time and
maximum capacitance a wire/pin is allowed to have. QoR (Quality of Results) is a general term for how
good the final numbers look — timing slack, power, area. Good routing directly improves timing QoR.
• Minimize congestion hotspots: Congestion is what happens when too many wires need to pass
through too small a physical area — like a traffic jam. A congestion hotspot can force the router into
long detours, or worse, leave some connections unroutable. Good routing spreads wiring demand
evenly.
• SI driven — reduction in cross-talk noise: SI stands for Signal Integrity. When two wires run close and
parallel to each other for a long distance, the switching signal on one wire can electrically "leak" onto
its neighbor through coupling capacitance — this is called crosstalk. Crosstalk can cause a quiet wire to
glitch, or can slow down/speed up a switching wire unpredictably. SI-driven routing actively avoids
long parallel-wire situations.
4. Checks Before Routing
Routing is one of the most sensitive stages in the flow — if the design isn't in a healthy state before routing
starts, the router can produce a poor-quality or even broken layout. So, before routing begins, engineers run
a checklist to confirm the design is ready.

4.1 Design and Data Readiness

• Design rules are defined in the technology file: The technology file (from the foundry that
manufactures the chip) encodes every manufacturing rule — minimum wire width, minimum spacing
between wires, via rules, and so on. The router cannot legally route anything without this file loaded
and correct.
• Placement and optimization must be complete; CTS and optimization should be complete: Every cell
must already have a final, legal (x, y) location, and the clock tree (see Chapter 1) must already be built
and optimized. Routing assumes cell positions and the clock structure are stable — routing before this
is finished would be like paving roads before all the houses are built.
• PG nets must be pre-routed and physically connected: PG stands for Power and Ground. Every
standard cell and macro needs a reliable connection to the power supply and ground before signal
routing starts, because power routing is planned very differently (thick, low-resistance wires in a grid
pattern) and must not be disturbed by signal routing later.
• Timing DRC violations and timing QoR estimated after CTS must be acceptable: After CTS, the tool re-
estimates timing. If there are already large timing problems at this point, they should usually be fixed
before routing, since post-route fixing is more expensive and time-consuming.
• Congestion should be tolerable: If the placement is already extremely congested (too many wires
needed in too little space), the router will struggle. Congestion should be estimated and kept within
reasonable limits before routing starts.
• Don't-touch and don't-use lists should be applied properly: A "don't-touch" instruction protects a
specific cell or net from being modified by the tool (often because an engineer manually tuned it). A
"don't-use" instruction tells the tool never to use certain cells from the library at all (perhaps they are
known to be problematic, or reserved). These lists must be correctly configured so
routing/optimization doesn't undo intentional decisions.
• There should not be any ideal nets: An "ideal" net is one the tool is still treating as having zero
delay/zero resistance, as a placeholder — usually true early in the flow, but by the time routing starts
almost everything should be modeled realistically. Leftover ideal nets mean the tool's timing picture is
unrealistic.

4.2 Design Integrity Checks

• Check for any optimization needed to fix errors: A final pass to catch and resolve any lingering errors
before committing to routing.
• Check if the pins of the standard cells are accessible: A pin can become "blocked" if a neighboring cell,
blockage, or obstruction sits right on top of it, leaving the router no legal way to connect a wire to it.
Every pin must have a clear, reachable access point.
• Check for overlapping cells: Two cells should never physically overlap. If they do, their pins can end up
short-circuited together, and the router will be forced to create illegal, DRC-violating metal shapes
trying to route around the mess.
• Check for ports outside the design boundary: "Out of boundary" pins are I/O ports that fall outside
the chip's defined area — these are unroutable by definition and must be fixed.
• Check for frozen nets or PG nets blocking ports: A "frozen" net is one whose routing is locked and
cannot be changed. If a frozen net or a power/ground net happens to physically sit on top of an I/O
port, it blocks access to that port.
• Check that all pins/ports are on the routing tracks: As we'll see in Chapter 8, most routing follows a
fixed grid of tracks. A pin that doesn't align with this grid can be difficult or impossible for the router to
connect to cleanly.
5. Inputs for Routing
A router needs several different files to do its job — logical information (what to connect), physical
information (what the cells and layers look like), electrical information (how fast things switch), and
constraint information (what deadlines to hit). Here is what each file provides:

• Netlist (.v): A Verilog file listing every standard cell instance in the design and the logical connections
(nets) between their pins. This is the "wiring instruction list" routing must obey exactly.
• Timing library (.lib): A Liberty-format file describing the electrical behavior of every standard cell —
how much delay it introduces, how much it slows down or speeds up under different loads, and how
much power it consumes. Routing/optimization tools use this to predict timing on the wires it draws.
• Physical library (.lef): Library Exchange Format — an abstract physical description of each standard
cell: its exact size, and the precise location of each pin on its boundary, plus any areas that are
"blocked" (cannot be routed over). This tells the router exactly where it may legally land a wire on a
cell.
• Technology library (.techlef): The technology LEF describes the manufacturing technology itself —
how many metal layers exist, their thickness, minimum width/spacing rules, and via definitions.
Combined with the standard .lef files, this gives the router the complete "map" of what is physically
possible.
• Timing constraint (.sdc): Synopsys Design Constraints — specifies the clock frequency (period),
input/output delays, and other timing requirements the design must meet. This tells the router which
paths are timing-critical and therefore deserve extra care.
• CTS DEF: A Design Exchange Format file capturing the design's state right after Clock Tree Synthesis —
every cell's exact placement, plus the newly built clock tree structure. This is the physical starting point
routing builds on top of.
• Parasitics information (tlu+/qrctech): Technology-specific files (TLU+ or QRC tech files) that tell
extraction tools how to estimate the resistance and capacitance ("parasitics") of a wire based on its
width, length, layer, and spacing to neighbors. Since resistance and capacitance directly determine
wire delay, the router relies on these files (indirectly, via the optimization engine) to make timing-
aware decisions.
6. Routing Methodologies
A router can be told to prioritize different things while it works. Two of the most important "modes" it can
run in are Timing Driven routing and SI Driven routing. These are not mutually exclusive — modern flows
typically run both together.

6.1 Timing Driven Routing

Timing slack is the fundamental concept here: for any given path in the chip, slack = (time allowed by the
clock) minus (time actually taken by the signal). Positive slack means the path is fast enough; negative slack
means it's a timing violation. Timing-driven routing focuses its effort on paths with the least (or negative)
slack.

• Analyzes timing slack for each path: Rather than treating every net equally, the router calculates how
much slack each path has and prioritizes accordingly.
• Routes the most critical sink first on multi-pin nets: A single net can fan out to multiple destination
pins (sinks). If some of those destinations are on timing-critical paths and others aren't, the router
(using an engine often called "NanoRoute" in some tools) connects the most critical sink with the most
direct, low-delay path first, before worrying about the less critical ones.
• Performs wire optimization: It continually adjusts detouring and reduces resistance and coupling
capacitance along critical wires — for example, by choosing a wider wire or a better layer for a critical
net, since resistance and capacitance are the two physical properties that directly create wire delay
(this is the RC delay concept: more resistance-capacitance product means a slower signal).
• Generates a timing information file (.[Link]): The router automatically writes this file into the
working directory during the process, and reuses it to keep making consistent timing-aware decisions
as timing-driven routing proceeds.

6.2 SI Driven Routing (Signal-Integrity Driven)

Recall from Chapter 3 that crosstalk happens when two parallel wires are close enough for their signals to
interfere with each other through coupling capacitance. In this context, the wire that causes the disturbance
is called the aggressor, and the wire that suffers the disturbance is called the victim.

• Uses a signal integrity engine to minimize crosstalk: It actively works to prevent or reduce situations
where wires run long and parallel to each other, since that geometry is exactly what maximizes
coupling capacitance between them.
• Works together with timing-driven routing: Crosstalk isn't just a "noise" problem — it also affects
timing (a victim net can appear to switch earlier or later than expected because of an aggressor). So SI-
driven and timing-driven routing are usually run in conjunction.
• Techniques used to reduce crosstalk: Once timing-driven routing identifies victim nets, SI-driven
routing applies fixes such as wire spacing (increasing the physical gap between aggressor and victim),
layer hopping (moving one of the wires to a different metal layer so they are no longer directly
adjacent), net ordering (deciding which nets get priority access to less-congested tracks), and simply
minimizing the use of long parallel wire segments in the first place.
7. Routing Constraints
Beyond simply asking the router to "connect everything well," engineers can give it explicit rules to follow —
routing constraints. These act like traffic laws that shape how the router is allowed to behave.

• Constraints on the number of layers used: An engineer can restrict routing to only use a certain range
of metal layers for a given net or region — useful for reserving certain layers for power routing or for
keeping some layers free for later ECOs (engineering change orders — late-stage fixes, explained in
Chapter 10).
• Preferred routing direction per layer: Metal layers typically alternate between a preferred horizontal
direction and a preferred vertical direction (for example, M2 horizontal, M3 vertical, M4 horizontal...).
This isn't arbitrary — routing each layer predominantly in one direction dramatically reduces the
number of layer-to-layer vias needed and makes the routing grid predictable and efficient, similar to
how a city grid with clearly separated avenues (one direction) and streets (perpendicular direction) is
easier to navigate than random diagonal roads.
• Blocking routing in specific regions: Certain areas can be marked off-limits to the router — for
example, above sensitive analog circuitry, or in regions reserved for future changes.
• Setting precedence to routing signals: Some nets can be given priority — for example, clock nets or
highly critical timing paths might be allowed to claim the best (most direct, least congested) routing
resources first, before ordinary signals compete for what's left.
• Constraining the routing density: A maximum allowed wire density can be set for a region, forcing the
router to spread wiring out rather than overloading one area — this helps prevent congestion hotspots
(see Chapter 3) and leaves room for future ECO changes.
8. Intermediate Steps of Routing
Routing an entire chip in one single pass would be far too complex a problem to solve efficiently or
accurately. Instead, the router breaks the problem down into four progressively more detailed stages, each
refining the work of the one before it:

• 1. Global routing — the coarse, big-picture plan.

• 2. Track assignment — assigning the plan to real physical tracks.
• 3. Detailed routing — drawing the exact final wire geometry.
• 4. Search and repair — hunting down and fixing whatever violations remain.

Analogy for this whole chapter:

Think of routing a chip like planning a country's transportation network. Global routing is choosing which
highways connect which cities, without yet deciding the exact lanes. Track assignment is assigning traffic to
specific lanes on those highways. Detailed routing is the actual construction crew paving each lane exactly,
avoiding every obstacle. Search and repair is the inspection team that drives every road afterward, finding
and fixing potholes and collisions.

8.1 Global Routing

Global routing is a coarse-grain assignment of routes — a planning stage that decides the general path each
net should take, without yet creating the exact physical wires.

• Gcells: The router first partitions the entire routing region into a grid of tiles, called global routing cells
or gcells. By default, a gcell's width equals the height of a standard cell row, and the gcell grid is
aligned with the standard cell rows themselves — so each gcell behaves like one "city block" in our
analogy.
• Tile-to-tile paths: For every net, global routing decides which sequence of gcells the wire should pass
through, attempting to optimize overall goals like total wire length and timing QoR — but it does not
decide the exact x,y coordinates or which specific track within a gcell to use. No actual metal is drawn
yet; this is purely a plan.

8.1.1 The Two Stages of Global Routing

• Initial routing stage: All currently unconnected nets are routed for the first time at this coarse level,
and the tool calculates "overflow" for each gcell — overflow means more wires want to pass through a
gcell than that gcell has physical capacity for, similar to more cars wanting to use a road than it has
lanes for.
• Rerouting stage(s): Wherever overflow was detected, the tool reduces congestion by ripping up
(removing) the offending net's route and rerouting it through a less congested path. This may repeat
over several iterations until overflow is minimized.
8.1.2 Reporting and Types of Global Routing
After the initial stage and after each rerouting stage, the tool reports design statistics and congestion data,
plus a summary of total wire length and via count at the end of the global routing stage overall. There are
three types of global routing, each optimizing for a different priority:

• Time Driven Global Routing: Net delays are estimated and factored into the global routing decisions,
so timing-critical nets get better (shorter/more direct) global paths.
• Cross Talk Driven Global Routing: Actively avoids creating long tile-to-tile paths that would run parallel
to each other on adjacent tracks — since (as we learned in Chapters 3 and 6) long parallel runs are
exactly what causes crosstalk.
• Incremental Global Routing: Rather than starting from scratch, this reuses the existing global route
information and only updates the parts of the design that changed — much faster when only a small
part of the design has been modified (for example, after an ECO).

8.2 Track Assignment

Track assignment is the stage where the router assigns actual routing tracks — the predefined horizontal or
vertical lines on each metal layer where wires are legally allowed to sit — to each global route produced in
the previous stage.

• Assigning tracks in horizontal and vertical partitions: Each gcell-to-gcell path from global routing is
converted into a specific track assignment, in both the horizontal and vertical directions needed to
complete the path.
• Rerouting overlapped wires: If two different nets end up assigned to the same track at the same
location, one of them is rerouted to a different track to resolve the conflict.
• Replacing global routes with actual metal layers: The abstract gcell-to-gcell plan is now converted into
wires on specific, real metal layers — a much more concrete version of the routing than what global
routing produced, though still not perfectly final.
Important nuance: even though every net now technically has a route after track assignment, there will
typically still be many DRC, SI, and timing-related violations at this stage — remember, tracks were assigned
somewhat greedily to resolve conflicts, without full attention to every design rule. These violations are fixed
in the next stages.

8.3 Detailed Routing

Detailed routing takes the routing plan laid out by global routing and track assignment and turns it into the
final, exact, DRC-clean metal geometry — every wire's precise width, exact position, and every via, fully
legalized against the manufacturing rules.

• Fixing violations through iterations: The violations left behind by track assignment are resolved here,
over multiple iterations, as the detailed router carefully nudges and re-shapes wires to satisfy every
design rule while preserving connectivity.

8.3.1 Switch Boxes (sbox)

To make this fine-grained problem manageable, the detailed router further divides the block into small
areas called switch boxes, or sboxes, which are expressed in terms of gcells and align exactly with gcell
boundaries. For example, a "3×3 sbox" is one switch box that encompasses a 3-by-3 grid of 9 gcells. The goal
of detailed routing within each sbox is to complete every required interconnect while minimizing shorts and
other DRC violations, working at a much finer resolution than global routing did.

8.4 Search and Repair

Search and repair is a focused clean-up stage performed during detailed routing, after its first iteration has
completed.

• Search: The tool scans the routed design to locate remaining shorts (two different nets accidentally
touching) and DRC violations (spacing, width, or other manufacturing rule breaks).
• Repair: The tool then attempts to fix each violation it found by rerouting the affected nets — nudging
wires apart, changing layers, or adjusting geometry — and this search-then-repair cycle can run for
multiple iterations until the design is (ideally) completely clean.
9. Types of Routing
Beyond the staged process above, there are two fundamentally different philosophies a router can follow
for how wires are allowed to be positioned: grid-based and grid-less.

9.1 Grid-Based Routing

• Centered on grid points: Metal traces (wires) are built along, and centered upon, a fixed routing grid of
tracks — much like buildings placed only at fixed addresses on a city grid, never in between.
• Layer switching only at intersections: A wire is only allowed to move from one metal layer to another
(via a via) at the intersection points of vertical and horizontal gridlines — never at an arbitrary point
along its length.
• Automatically satisfies design rules: Because the grid spacing itself is designed around the minimum-
width, minimum-spacing wire that the technology allows, simply following the grid with minimum-
width wires automatically keeps the layout legal — the grid does the hard work of DRC compliance for
you.
• Efficiency: This predictability makes grid-based routing much more efficient and easier to implement,
which is why the vast majority of modern digital chip routing uses this approach.

9.2 Grid-less Routing

• No fixed grid: Grid-less routing does not follow a routing grid, and so it is free to use different (non-
uniform) wire widths and spacing wherever needed.
• Greater flexibility: Its main advantage lies in this flexibility — wires can be exactly the width and
spacing needed for a specific electrical or physical requirement, rather than being forced onto a fixed
grid.
• Slower and more complex: That same flexibility is also its downside — because there's no simplifying
grid to lean on, grid-less routing is generally much slower than grid-based routing, since maintaining
design rule correctness now requires far more computation for every possible wire position and width
combination.
10. Filler Cells
After placement and routing, standard cell rows almost never end up perfectly "full" — there are usually
small empty gaps left between cells within a row. Certain layers in the manufacturing process (like the N-
well, a doped silicon region used to build PMOS transistors) are expected to run continuously along an entire
row. An empty gap creates a break in that continuity, which manufacturing design rules generally forbid.
Filler cells solve this.

10.1 What Filler Cells Are

• Physical-only cells: Filler cells have no logic function at all — they don't compute anything. Their sole
job is to physically fill empty gaps in a standard cell row.
• N-well continuity: By filling gaps, they provide continuous N-well material along the row and avoid N-
well spacing DRC violations that would otherwise occur if the well region was interrupted.
• When they're inserted: Filler cells are inserted at the last stage of place-and-route (PnR) — after the
cell layout is essentially finalized — since inserting them too early would just create more gaps to
manage as cells continue to move during optimization and routing.
• Poly density, not metal density: Filler cells help meet the poly density rule (a manufacturing
requirement that a minimum percentage of a region contain polysilicon material, for uniform
manufacturing/etching results), but they are not intended to help meet metal density requirements —
that is a separate concern handled separately (sometimes by dedicated metal fill shapes).

10.2 Commands for Adding Filler Cells

In a typical commercial PnR tool, filler cells are added with commands similar to:
setFillerMode –preserveOrder true –core {fill6 fill4 fill1}
addFiller

setFillerMode configures which filler cells (from a preferred list, here fill6, fill4, fill1 — different widths)
should be used and in what order preference, and addFiller then executes the actual insertion across the
design.

10.3 Types of Filler Cells

• Non-metal filler: The most basic type, used purely for N-well continuity. These cells contain multiple
parallel poly structures but have no contact connections to poly or active silicon layers — they are
physically present but electrically inert. They are typically designed in a range of width multiples (e.g.,
x, 2x, 4x, 8x, 16x, 48x the base unit width) so that different-sized gaps can be filled efficiently with the
fewest cells — note that this "x" numbering refers only to physical width, not to drive strength the way
it would for a real logic gate.
• Metal filler: A filler type focused on adding metal shapes to help meet metal density requirements (as
distinct from the poly density that non-metal fillers address).
 • De-cap filler (decoupling capacitor filler): These cells share the same FEOL (Front End Of Line — the
lower, transistor-level manufacturing layers) footprint as the corresponding non-metal filler, but
additionally realize a de-cap by connecting source/drain terminals to VDD/VSS. A decoupling capacitor
acts like a tiny local reservoir of charge sitting right next to the power grid — when a nearby circuit
suddenly needs a burst of current, the de-cap can supply it instantly rather than waiting for it to travel
from a distant power source, which improves the stability of the power supply and reduces voltage
noise (IR drop and ground bounce).
• Programmable filler: These include a wide variety of combinational and sequential elements at
multiple drive strengths, all realized using the same family of width multiples as the non-metal filler.
Critically, a real functional cell (an actual logic gate) is designed to have the exact same FEOL footprint
as its corresponding programmable filler. For example, the smallest functional gate available and its
matching programmable filler share layout — the only difference is the programmable filler uses the
non-metal-filler-style layout (no contact connections), whereas the real functional cell adds contact
connections to poly/active to actually realize the logic function.

10.4 Why Programmable Fillers Matter: Metal-Only ECOs

An ECO (Engineering Change Order) is a late-stage design fix — for example, correcting a logic bug
discovered after most of the physical design work is already done. Redoing the transistor-level (base) layers
of a chip is extremely expensive and slow, so engineers strongly prefer a metal-only ECO: a fix that only
changes the metal/via layers, leaving the expensive base (transistor) layers untouched.

Programmable fillers make this possible. Because a programmable filler cell already has the identical FEOL
footprint as several possible real logic gates, a metal-only ECO can simply swap the metal-layer connections
at that location — turning what was an inert filler into a working AND gate, for instance — without touching
the base silicon layers at all.

• How the tool decides: For example, if an AND gate needs to be added, the tool looks at which of the
available gate-array-style filler cells at that location can be swapped in for the AND gate without
requiring any base layer change.
The command used to perform this swap is:
ecoPlace -useGAFillerCells

This instructs the tool to search the design for compatible programmable (gate-array-style) filler cells and
swap them with the required functional cells during the ECO.
11. Outputs of Routing
Once routing (and all its intermediate stages) is complete, the tool produces a set of output files that carry
the fully-wired design forward to the next stages of the flow (signoff, and ultimately manufacturing):

• Netlist (.v): An updated Verilog netlist, reflecting any changes made by optimization or ECOs during
and after routing.
• Routing DEF: A Design Exchange Format file that now includes the full, exact physical routing geometry
— every wire segment and via, on every layer, for every net — in addition to the cell placement and
clock tree information it already carried.
• Timing constraints (.sdc): The (possibly updated) timing constraints, carried forward so downstream
tools continue to check the design against the same requirements.
• Parasitic information (.spef): Standard Parasitic Exchange Format — this is the crucial output that
captures the actual resistance and capacitance of every real, physically-routed wire (as opposed to the
earlier estimates used during optimization). This file is what allows Static Timing Analysis (STA) after
routing to be highly accurate, since it reflects real wire geometry rather than a prediction.
• Layout information (.gds / .oas): GDSII or OASIS — the final geometric layout file format that describes
every physical shape on every layer of the chip. This is the file that is ultimately sent to the
semiconductor foundry to manufacture ("tape out") the physical chip.
12. Checks After Routing
Just as there was a checklist before routing began, there is a checklist to confirm the routed design is healthy
before moving on:

• Check for legalization: Legalization confirms every cell sits on a legal, non-overlapping, grid-aligned
position — routing itself shouldn't have caused any cell to become illegally placed, but this is verified
regardless.
• There should not be any high timing violations: Large (severe) setup or hold violations after routing
are a red flag that the design isn't ready to proceed — these are discussed in depth in Chapter 13.
• Minimal logical DRCs: Logical design rule issues — such as unconnected pins or floating logic — should
be minimal to none.
• Minimal physical DRCs: Physical (geometric) design rule violations — spacing, width, via rules —
should likewise be minimal to none, ideally fully resolved by search-and-repair.
• There should not be any opens: An "open" is a connection from the netlist that failed to be physically
completed — effectively a missing wire. This is a critical, must-fix defect, since it means the chip will
not function as designed.
• Check whether any don't-use cells were used: Confirms the router/optimizer respected the don't-use
list established before routing (see Chapter 4).
• All don't-touch nets and cells should be preserved: Confirms nothing marked as protected was
accidentally modified during routing.
• Check for logical equivalence: Logical Equivalence Checking (LEC) formally proves that the final gate-
level netlist is functionally identical to the original, intended design — ensuring that none of the
automated optimizations, ECOs, or fixes applied throughout the flow accidentally changed what the
chip actually does.
13. Timing Violations: Setup and Hold

13.1 Fundamentals: What Are Setup and Hold Violations?

Every synchronous chip is full of flip-flops — tiny memory elements that capture ("latch") the value on their
input the instant the clock signal ticks (a clock edge). Data travels from one flip-flop (the launch flop)
through some combinational logic (gates) and wires, arriving at the input of the next flip-flop (the capture
flop). For the chip to work correctly, that data must arrive at the capture flop within a specific timing
window relative to the clock edge.

• Setup violation: Every flip-flop needs its input data to become stable a minimum amount of time (the
setup time) before the clock edge arrives, or it may capture the wrong value. A setup violation means
the data arrived too late — the logic path between the two flops was too slow to finish before the next
clock edge. This is a "the path is too slow" problem, and it gets worse at higher clock frequencies.
• Hold violation: Every flip-flop also needs its input data to remain stable for a minimum amount of time
(the hold time) after the clock edge. A hold violation means new data arrived too quickly — so fast that
it overwrote the data before the flip-flop finished safely capturing the previous value. This is a "the
path is too fast" problem, and unlike setup, it has nothing to do with clock frequency — a hold
violation exists (or doesn't) regardless of how slow you run the clock.

Simple mental model:

Setup = "don't be late." Hold = "don't be early." A path can violate one, the other, both, or neither.

13.2 Reasons for Setup Violations

• High logic-depth: The more gates a signal must pass through, the more delay accumulates — a deep
chain of logic between two flops is inherently slow.
• Detouring (logic spread out): If the cells along a path are physically far apart (spread across the chip),
the wires connecting them are longer, and longer wires mean more delay.
• High fanout startpoints: If a single gate's output must drive many downstream loads (high fanout), it
has to work harder to charge/discharge all those connections, which slows down its output transition.
• Worst slew/cap: Slew is how quickly a signal transitions between logic 0 and logic 1 — a slow ("lazy")
transition delays everything downstream. This is often caused by driving too much capacitance (cap)
for the driving gate's strength — too much load for too small a driver.
• Due to constraint issues: Sometimes the .sdc constraints themselves are overly aggressive, unrealistic,
or simply incorrect, creating violations that aren't really about physical design quality but about
mismatched expectations.
• Worst skew and insertion delay: Clock skew is the difference in arrival time of the clock signal at two
different flip-flops; insertion delay is how long the clock takes to reach a flop from its source. If the
clock tree (Chapter 1) isn't well balanced, this eats directly into the time budget available for the data
path.
 • Due to crosstalk: As discussed in Chapters 3 and 6, a switching aggressor net can slow down (or speed
up) a victim net's transition, adding unpredictable delay.
• Unoptimized cells due to density constraint: Sometimes the optimizer wants to upsize a cell (use a
stronger, faster version) to fix a slow path, but the local area is too physically congested/dense to fit a
larger cell there, so the fix can't be applied.
• High memory setup/access time: Large memory macros (like SRAM blocks) are often inherently slow
to access compared to standard logic gates, and if a path runs through or ends at a memory, that
memory's own access time can dominate the path delay.
• RC correlation issue between subsequent PnR stages: Different stages of the flow (placement, CTS,
routing) each make their own estimate of a wire's resistance and capacitance before the real geometry
exists. If these estimates don't correlate well with reality once the wire is actually routed, timing can
look fine at one stage and suddenly appear to violate at the next.

13.3 Setup Fixing Techniques

• Path grouping with weighting: Group unoptimized violating paths into their own "path group" and, if
needed, assign extra weight so the optimization engine spends more effort fixing that specific group of
paths.
• Bounding to club spread logic: Create a physical bound (a region constraint) that pulls the cells of a
spread-out logic path closer together, directly attacking the "detouring" root cause.
• Timing driven optimization / routing: Re-run optimization and routing with an explicit timing-driven
focus (see Chapter 6) so critical paths get priority treatment.
• SI driven routing: Reduce crosstalk-induced delay by applying the SI-driven techniques from Chapter 6
(wire spacing, layer hopping, etc.).
• Reroute the detoured net: Directly force a problematic net to be re-routed along a more direct path.
• Spread the logic (for density-limited paths): Counter-intuitively, sometimes the fix for a density-
blocked upsize is to spread cells apart slightly to make room for a bigger, faster cell — a deliberate
trade-off between wire length and cell drive strength.
• Useful skew: Rather than treating clock skew as purely something to minimize, useful skew
deliberately introduces a small, controlled amount of skew to "borrow" extra time for a specific
violating path, effectively shifting the capture flop's clock edge slightly later to give the data path more
time to arrive.
• Fine-tune the RC correlation: Adjust the RC factor (a scaling/correction factor applied to parasitic
estimates) so that a stage's timing predictions better match what routing will actually deliver,
addressing the RC correlation root cause directly.

13.4 Reasons for Hold Violations

• High local density: In a densely packed region, cells sit extremely close together, so a path can have
very little logic and wire delay — sometimes too little, making it vulnerable to a hold violation.
• High memory hold time: Memory macros can have inherently large hold time requirements, making
paths that involve them more prone to hold violations.
 • Insufficient or over-utilized macro channel for hold-critical memory: The routing channel (open
space) around a macro may be too small, or already overloaded with other routing, limiting the
router's ability to add delay where needed to fix a hold violation near that macro.
• Due to constraint issues: As with setup, incorrect or unrealistic constraints can also create false or
exaggerated hold violations.
• Worst skew and insertion delay: Just as poor clock tree balance can hurt setup, it can also directly
cause hold violations if the capture flop's clock arrives too early relative to the launch flop's clock.
• Due to crosstalk: Crosstalk can also make a signal arrive earlier than expected, contributing to a hold
violation.
• Shortest path (e.g., scan path): Some paths are inherently very short by design — a classic example is
a scan chain (a special test-mode wiring used to shift test patterns through flip-flops), where the
launch and capture flops may be directly adjacent with almost no logic between them, making hold
violations especially likely.

13.5 Hold Fixing Techniques

• Reduce local density: By creating partial blockages (marking areas as off-limits to placement), adding
padding (extra empty space) around cells, or logic spreading — all of which push cells further apart,
increasing the natural delay of a too-fast path.
• Timing driven routing: Applying timing-driven routing techniques can also help balance out hold-
critical paths.
• SI driven routing: Reduces crosstalk that could otherwise be making a path too fast (an early-arriving
aggressor effect).
• Detour the net: Unlike setup fixing (which tries to shorten/straighten paths), hold fixing sometimes
deliberately routes a net less directly, adding wire length and therefore delay on purpose, to push a
too-fast path back into its legal timing window.
• Useful skew: Just as with setup, a deliberate, controlled clock skew can also be used to fix hold
violations — this time shifting the capture flop's clock edge in the opposite direction needed to create
more margin.
14. Glossary of Key Terms
A quick-reference summary of the acronyms and terms used throughout this guide.

Term Meaning

Netlist A logical list of standard cell instances and the connections (nets) between their pins,
produced by synthesis.

Standard cell A pre-designed, pre-characterized basic logic gate (AND, OR, flip-flop, etc.) used as a
building block for the chip.

Macro A large, pre-designed physical block, such as a memory (SRAM) or a pre-built IP core.

Net One logical connection point, which may fan out to one or more destination pins.

Metal layer / Via A metal layer is a horizontal sheet of conductive wiring; a via is a vertical connector linking
two adjacent metal layers.

DRC (Design Rule A manufacturing-driven geometric rule (minimum width, spacing, etc.) that a layout must
Check) satisfy.

QoR (Quality of A general measure of how good the design's key metrics (timing, power, area) are.
Results)

CTS (Clock Tree The stage that builds a balanced tree of wires/buffers to distribute the clock signal to
Synthesis) every flip-flop.

PG nets Power and Ground nets — the nets that deliver electrical power to every cell.

SI (Signal Integrity) The study/management of unwanted electrical interactions between signals, primarily
crosstalk.

Crosstalk Unwanted electrical coupling between two nearby parallel wires (an aggressor disturbing
a victim).

Antenna violation Manufacturing-process damage risk from a long, isolated metal wire accumulating charge
before being fully connected.

Gcell Global routing cell — a tile used to coarsely partition the chip during global routing.

Sbox (switch box) A finer-grained group of gcells used to organize detailed routing.

LEF / techLEF Library Exchange Format files describing, respectively, standard cell physical shapes/pins
and the manufacturing technology's layers and rules.

DEF Design Exchange Format — a file capturing a design's physical state (placement, routing,
etc.) at a point in the flow.

SDC Synopsys Design Constraints — the file specifying timing (and related) requirements for
the design.

SPEF Standard Parasitic Exchange Format — a file capturing extracted resistance/capacitance of

real, routed wires.

GDSII / OASIS The final layout file formats sent to a foundry to manufacture the chip.
Term Meaning

STA (Static Timing Timing analysis that checks every path in the design against setup/hold requirements
Analysis) without needing simulation vectors.

Setup / Hold violation Setup: data arrived too late before a clock edge. Hold: data arrived too early after a clock
edge.

Slack The difference between the time allowed and the time actually taken by a path; negative
slack is a violation.

Skew / Insertion delay Skew: difference in clock arrival time between two flops. Insertion delay: time for the
clock to travel from its source to a flop.

ECO (Engineering A late-stage design fix, ideally limited to metal-only changes to avoid costly base-layer
Change Order) (transistor) rework.

Filler cell A physical-only, non-functional cell inserted to fill gaps in a standard cell row for
manufacturing continuity.

De-cap (decoupling A small local capacitor connected to power/ground that stabilizes the power supply
capacitor) against sudden current demand.

Legalization The process of confirming/adjusting every cell to sit on a legal, non-overlapping, grid-
aligned position.

LEC (Logical A formal check proving the final netlist is functionally identical to the original design
Equivalence Check) intent.
15. Closing Summary
Routing sits at a pivotal point in physical design: everything before it (synthesis, floorplanning, placement,
CTS) exists to set the stage, and everything after it (signoff, timing closure, tape-out) depends on routing
having done its job correctly. The core idea, however, is simple: take a logical wiring list (the netlist) and
every cell's fixed position, and turn that into legal, manufacturable metal geometry that connects everything
correctly — while balancing wire length, timing, power, congestion, and signal integrity along the way.

The staged approach — global routing, track assignment, detailed routing, and search-and-repair — exists
purely to make this enormous optimization problem tractable, moving from a coarse plan to exact, DRC-
clean geometry step by step. And the checks before and after routing exist to make sure the process starts
from a healthy design and ends with one that is truly ready to be manufactured.