8086 Pins & Signals
Chapter 2
8086 Pinout
GND --- 1 40 --- VCC
AD15-AD0: Multiplexed address(ALE=1)/data AD14 <-> 2 39 <-> AD15
bus(ALE=0).
AD13 <-> 3 38 --> A16/S3
AD12 <-> 4 37 --> A17/S4
A19/S6-A16/S3 (multiplexed): High order 4 bits AD11 <-> 5 36 --> A18/S5
of the 20-bit address OR status bits S6-S3.
AD10 <-> 6 35 --> A19/S6
AD9 <-> 7 34 --> !BHE/S7
AD8 <-> 8 33 <-- MN/!MX
M/IO’: Indicates if address is a Memory or IO
address. AD7 <-> 9 32 --> RD
!RQ/!GT0,HO
AD6 <-> 10 31 <->
8086 LD
!RQ/!GT1,HO
RD’: When 0, data bus is driven by memory or AD5 <-> 11 30 <->
LA
an I/O device.
AD4 <-> 12 29 --> !LOCK,!WR
AD3 <-> 13 28 --> !S2,M/!IO
WR: Microprocessor is driving data bus to AD2 <-> 14 27 --> !S1,DT/!R
memory or an I/O device. When 0, data bus AD1 <-> 15 26 --> !S0,!DEN
contains valid data. AD0 <-> 16 25 --> QS0,ALE
NMI --> 17 24 --> QS1,!INTA
INTR --> 18 23 <-- !TEST
ALE (Address latch enable): When 1, address
data bus contains a memory or I/O address. CLK --> 19 22 <-- READY
8086 GND --- 20 21 <-- RESET
8086 Pinout
GND --- 1 40 --- VCC
DT/R’ (Data Transmit/Receive): Data bus is AD14 <-> 2 39 <-> AD15
transmitting/receiving data. AD13 <-> 3 38 --> A16/S3
AD12 <-> 4 37 --> A17/S4
AD11 <-> 5 36 --> A18/S5
DEN (Data bus Enable): Activates external data
AD10 <-> 6 35 --> A19/S6
bus buffers.
AD9 <-> 7 34 --> !BHE/S7
AD8 <-> 8 33 <-- MN/!MX
AD7 <-> 9 32 --> RD
S7: Logic 1 !RQ/!GT0,HO
AD6 <-> 10 31 <->
8086 LD
!RQ/!GT1,HO
AD5 <-> 11 30 <->
LA
S6: Logic 0. AD4 <-> 12 29 --> !LOCK,!WR
AD3 <-> 13 28 --> !S2,M/!IO
AD2 <-> 14 27 --> !S1,DT/!R
S5: Indicates condition of IF flag bits. AD1 <-> 15 26 --> !S0,!DEN
AD0 <-> 16 25 --> QS0,ALE
NMI --> 17 24 --> QS1,!INTA
INTR --> 18 23 <-- !TEST
CLK --> 19 22 <-- READY
8086 GND --- 20 21 <-- RESET
8086 Pinout GND --- 1 40 --- VCC
S4-S3: Indicate which segment is accessed during AD14 <-> 2 39 <-> AD15
current bus cycle: AD13 <-> 3 38 --> A16/S3
AD12 <-> 4 37 --> A17/S4
AD11 <-> 5 36 --> A18/S5
AD10 <-> 6 35 --> A19/S6
AD9 <-> 7 34 --> !BHE/S7
AD8 <-> 8 33 <-- MN/!MX
AD7 <-> 9 32 --> RD
!RQ/!GT0,HO
S2’, S1’, S0’ : Indicate function of current bus AD6 <-> 10 31 <->
cycle (decoded by 8288 8086 LD
!RQ/!GT1,HO
AD5 <-> 11 30 <->
LA
AD4 <-> 12 29 --> !LOCK,!WR
AD3 <-> 13 28 --> !S2,M/!IO
AD2 <-> 14 27 --> !S1,DT/!R
AD1 <-> 15 26 --> !S0,!DEN
AD0 <-> 16 25 --> QS0,ALE
NMI --> 17 24 --> QS1,!INTA
INTR --> 18 23 <-- !TEST
CLK --> 19 22 <-- READY
8086 GND --- 20 21 <-- RESET
8086 Pinout
GND --- 1 40 --- VCC
INTR: When 1 and IF=1, microprocessor prepares AD14 <-> 2 39 <-> AD15
to service interrupt. INTA becomes active after AD13 <-> 3 38 --> A16/S3
current instruction completes.
AD12 <-> 4 37 --> A17/S4
AD11 <-> 5 36 --> A18/S5
AD10 <-> 6 35 --> A19/S6
INTA’: Interrupt Acknowledge generated by the
AD9 <-> 7 34 --> !BHE/S7
microprocessor in response to INTR. Causes the
AD8 <-> 8 33 <-- MN/!MX
interrupt vector to be put onto the data bus.
AD7 <-> 9 32 --> RD
!RQ/!GT0,HO
AD6 <-> 10 31 <->
NMI: Non-maskable interrupt. Similar to INTR
8086 LD
!RQ/!GT1,HO
AD5 <-> 11 30 <->
except IF flag bit is not consulted and interrupt is LA
vector 2. AD4 <-> 12 29 --> !LOCK,!WR
AD3 <-> 13 28 --> !S2,M/!IO
AD2 <-> 14 27 --> !S1,DT/!R
AD1 <-> 15 26 --> !S0,!DEN
CLK: Clock input must have a duty cycle of 33%
(high for 1/3 and low for 2/3s) AD0 <-> 16 25 --> QS0,ALE
NMI --> 17 24 --> QS1,!INTA
INTR --> 18 23 <-- !TEST
CLK --> 19 22 <-- READY
8086 GND --- 20 21 <-- RESET
8086 Pinout GND --- 1 40 --- VCC
MN/ MX’: Select minimum (5V) or maximum AD14 <-> 2 39 <-> AD15
mode (0V) of operation. AD13 <-> 3 38 --> A16/S3
AD12 <-> 4 37 --> A17/S4
AD11 <-> 5 36 --> A18/S5
BHE’: Bus High Enable. Enables the most
significant data bus bits (D15 -D8 ) during a read or AD10 <-> 6 35 --> A19/S6
write operation. AD9 <-> 7 34 --> !BHE/S7
AD8 <-> 8 33 <-- MN/!MX
AD7 <-> 9 32 --> RD
READY: Used to insert wait states (controlled by
memory and IO for reads/writes) into the !RQ/!GT0,HO
AD6 <-> 10 31 <->
microprocessor. 8086 LD
!RQ/!GT1,HO
AD5 <-> 11 30 <->
LA
AD4 <-> 12 29 --> !LOCK,!WR
RESET: Microprocessor resets if this pin is held
high for 4 clock periods. AD3 <-> 13 28 --> !S2,M/!IO
AD2 <-> 14 27 --> !S1,DT/!R
Instruction execution begins at FFFF0H and IF flag AD1 <-> 15 26 --> !S0,!DEN
is cleared.
AD0 <-> 16 25 --> QS0,ALE
NMI --> 17 24 --> QS1,!INTA
TEST’: An input that is tested by the WAIT INTR --> 18 23 <-- !TEST
instruction. Commonly connected to the 8087 CLK --> 19 22 <-- READY
coprocessor GND --- 20 21 <-- RESET
8086
8086 Pinout
GND --- 1 40 --- VCC
HOLD: Requests a direct memory access (DMA). AD14 <-> 2 39 <-> AD15
When 1, microprocessor stops and places address, AD13 <-> 3 38 --> A16/S3
data and control bus in high-impedance state.
AD12 <-> 4 37 --> A17/S4
AD11 <-> 5 36 --> A18/S5
AD10 <-> 6 35 --> A19/S6
HLDA (Hold Acknowledge): Indicates that the
microprocessor has entered the hold state. AD9 <-> 7 34 --> !BHE/S7
AD8 <-> 8 33 <-- MN/!MX
AD7 <-> 9 32 --> RD
RO’/GT1’ & RO’/GT0’: Request/grant pins AD6 <-> 10
8086 31 <-> !RQ/!GT0,HOLD
request/grant direct memory accesses (DMA) AD5 <-> 11 30 <-> !RQ/!GT1,HOLA
during maximum mode operation. AD4 <-> 12 29 --> !LOCK,!WR
AD3 <-> 13 28 --> !S2,M/!IO
AD2 <-> 14 27 --> !S1,DT/!R
LOCK’: Lock output is used to lock peripherals off AD1 <-> 15 26 --> !S0,!DEN
the system. Activated by using the LOCK: prefix on AD0 <-> 16 25 --> QS0,ALE
any instruction.
NMI --> 17 24 --> QS1,!INTA
INTR --> 18 23 <-- !TEST
CLK --> 19 22 <-- READY
GND --- 20 21 <-- RESET
8086
8086 Pinout
GND --- 1 40 --- VCC
AD14 <-> 2 39 <-> AD15
AD13 <-> 3 38 --> A16/S3
AD12 <-> 4 37 --> A17/S4
QS1 & QS0: The queue status bits show AD11 <-> 5 36 --> A18/S5
status of internal instruction queue. AD10 <-> 6 35 --> A19/S6
Provided for access by the numeric
AD9 <-> 7 34 --> !BHE/S7
coprocessor (8087).
AD8 <-> 8 33 <-- MN/!MX
AD7 <-> 9 32 --> RD
QS1 QS0 Function
AD6 <-> 10
8086 31 <-> !RQ/!GT0,HOLD
AD5 <-> 11 30 <-> !RQ/!GT1,HOLA
0 0 Queue is idle
AD4 <-> 12 29 --> !LOCK,!WR
0 1 First byte of opcode AD3 <-> 13 28 --> !S2,M/!IO
1 0 Queue is empty AD2 <-> 14 27 --> !S1,DT/!R
1 1 Subsequent byte of opcode AD1 <-> 15 26 --> !S0,!DEN
AD0 <-> 16 25 --> QS0,ALE
NMI --> 17 24 --> QS1,!INTA
INTR --> 18 23 <-- !TEST
CLK --> 19 22 <-- READY
GND --- 20 21 <-- RESET
8086
RESET# Signal
•The Active low RESET# signal puts the 8086 into a
defined state
•Clears the flags register, segment registers etc.
•Sets the effective program address to 0FFFF0h (CS=0F000h,
IP=0FFF0h)
•Microprocessor resets if this pin is held high for 4 clock
periods.
8086
8086 Microprocessor
MAXIMUM MINIMUM
MODE MODE
GND 1 40 Vcc
AD14 AD15 Minimum Mode:
AD13 A16,S3 ◦ 8086 is configured to support small, single
AD12 A17,S4
processor systems using a few devices that
AD11 A18,S5
AD10 A19,S6
use the system bus
AD9 /BHE,S7
AD8 MN,/MX
AD7 /RD
AD6
8086
/RQ,/GT0 HOLD Maximum Mode:
AD5 /RQ,/GT1 HLDA
AD4 /LOCK /WR
◦ 8086 is configured to support multi-
AD3 /S2 IO/M
processor systems.
AD2 /S1 DT/R ◦ 8086 needs at least the following:
AD1 /S0 /DEN
AD0 QS0 ALE
◦ 8288 Bus Controller,
NMI QS1 /INTA ◦ 8284A Clock Generator,
INTR /TEST
◦ 74HC373s and 74HC245s
CLK READY
GND 20 21 RESET
8086
DMA with 8086 in Minimum Mode
Two signals are used to request/ack a DMA transfer:
◦ HOLD is an input to the 8086 that requests a DMA action.
◦ HLDA’ is an output from the 8086 granting the DMA action.
The microprocessor responds by suspending the execution of the program and
by placing its address, data and control bus in high-impedance states.
8086
8086 Maximum Mode
For systems with more than one processor (multiprocessor systems)
◦ Processors can execute concurrently
◦ Increased performance
◦ Can have special-purpose processors (e.g., numeric coprocessor, I/O processor)
Some issues:
◦ Resource sharing
◦ Synchronization
◦ Bus contention
But processors synchronize activities
Communicate with each other (IPC)
Share resources with each other
Avoid interference (bus contention) with each other, so there must be more control signals
in Max mode
8086
Use of BHE#/A0(BLE#)
BHE# A0/BLE# Selection
0 0 Whole word (16-bits)
0 1 High byte to/from odd address
1 0 Low byte to/from even address
1 1 No selection
Byte-Wide addres s ing
ODD Addres s es (8086) EVEN Addres s es (8086)
(8088)
FFFFF FFFFF FFFFE
FFFFE FFFFD FFFFC
FFFFD FFFFB FFFFA
FFFFC FFFF9 FFFF8
A19..A1 A19..A1
00002 00005 00004
00001 00003 00002
00000 00001 00000
D15:D8 D7:D0
BHE# A0/BLE#
8086
ALE and Address/data Bus Multiplexing
8086 Multiplexes the Address and
Clock
Data signals onto the same set of Address/
Data
Bus
Address
Time
Data Time
pins
ALE
Output of
Microcomputer AddressBus
74HC373
Need off-chip logic to separate the 74HC373 or equivalent
signals
Address/ System Address Bus
In0:In7 Q0:Q7
Data Bus
Transparent latches designed just ALE
LE
for address demultiplexing OE#
TriState Control signal,
OE#, shown connected to
GND for simplicity
8086
Bus Cycle
Timing:
◦ Each BUS CYCLE on the 8086 equals four system clocking periods (T states).
◦ The clock rate is 5MHz , therefore one Bus Cycle is 800ns .
◦ The transfer rate is 1.25MHz .
Memory specs (memory access time) must match constraints of system timing.
For example,
◦ bus timing for a read operation shows almost 600ns are needed to read data.
◦ However, memory must access faster due to setup times, e.g. Address setup and
data setup.
◦ This subtracts off about 150ns .
◦ Therefore, memory must access in at least 450ns minus another 30-40ns guard
band for buffers and decoders
8086
Minimum Mode Pins
Minimum mode - READ
Hence the timing diagram can be categorized in two parts,
the timing diagram for read cycle
the timing diagram for write cycle.
The read cycle begins in T1 with the assertion of address
latch enable (ALE) signal and also M / IO signal.
During the negative going edge of this signal, the valid
address is latched on the local bus.
Minimum mode – READ continue…
The BHE and A0 signals address low, high or both bytes. From T1 toT4
, the M/IO signal indicates a memory or I/O operation.
At T2, the address is removed from the local bus and is sent to the
output. The bus is then tri-stated. The read (RD) control signal is also
activated in T2.
The read (RD) signal causes the address device to enable its data bus
drivers. After RD goes low, the valid data is available on the data bus.
The addressed device will drive the READY line high. When the
processor returns the read signal to high level, the addressed device will
again tri-state its bus drivers.
Minimum mode -Write
A write cycle also begins with the assertion of ALE and the emission of
the address. The M/IO signal is again asserted to indicate a memory or
I/O operation. In T2, after sending the address in T1, the processor
sends the data to be written to the addressed location.
The data remains on the bus until middle of T4 state. The WR
becomes active at the beginning of T2 (unlike RD is somewhat
delayed in T2 to provide time for floating).
The BHE and A0 signals are used to select the proper byte or bytes of
memory or I/O word to be read or write.
The M/IO, RD and WR signals indicate the type of data transfer as
specified in table below.
Maximum mode 8086 system continue…
In the maximum mode, the 8086 is operated by
strapping the MN/MX pin to ground.
In this mode, the processor derives the status signal S2, S1,
S0. Another chip called bus controller derives the control
signal using this status information .
In the maximum mode, there may be more than one
microprocessor in the system configuration.
The components in the system are same as in the
minimum mode system.
Maximum-Mode Interface(cont.)
8288 bus controller
S2 S1 S0 Function
0 0 0 Interrupt acknowledge
0 0 1 I/O read
0 1 0 I/O write
0 1 1 Halt
1 0 0 Opcode fetch
1 0 1 Memory read
1 1 0 Memory write
1 1 1 Passive
Bus status code
Maximum-mode memory control signals
MRDC – Memory Read Command
MWTC – Memory Write Command
AMWC – AdvancedMemory Write
Input/Output Bus Cycles (cont.)
Input/Output Bus Cycles (cont.)
Thank You