NAND Flash Memory:
Fundamentals & Technology
G P R Yasasvi
Staff Engineer, NVMQRA, Micron Technology
yasasvigpr@[Link] 1
About Myself
• Academics:
• B.E in EIE (College of Engineering, GITAM, Visakhapatnam)
• [Link] in Instrumentation Engineering (IISc, Bengaluru)
• Ph.D (CeNSE, IISc, Bengaluru)
• Professional Experience:
• Overall ~8 years of experience in the areas of
• Hardware design (at Eaton India Engineering Centre)
• NAND Flash reliability & qualification (at Western Digital)
• SSD qualification & reliability (at Micron)
• Publications:
• 7 Journal publications, 3 Patents, 1 Trade secret
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Outline
• Introduction
• NAND Fundamentals
• NAND Reliability Issues
• Flash Memory for AI/ML
• Future Trends
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Introduction
NAND Flash:
• A ‘non-volatile’ memory technology
– can store data even if its power is
removed
• Latencies are higher than that of
SRAM & DRAM - used primarily for
storage applications
• Cheaper than SRAM/DRAM
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Introduction
NAND Gate NAND Cell Array
Why is it called NAND Flash?
• NAND: The cell array is similar to a NAND gate’s pull down circuit.
• Flash: Because data in a ‘block’ is erased together – in a ‘flash’
Applications:
• Removable/Portable storage: USB, SD cards etc.
• Embedded Storage: MP3 player, mobile phones etc.
• Solid State Drives: Laptops, Data centres etc.
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Introduction
Evolution: Flash memory was invented by Dr. Fujio Masuoka of Toshiba in 1984
Yoon, “The Fundamentals of NAND Flash Memory”, IEEE Solid State Circuits Magazine, 2022
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Outline
• Introduction
• NAND Fundamentals
• NAND Reliability Issues
• Flash memory for AI/ML
• Future Trends
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Floating Gate Transistor
Schematic of a FG transistor
Shimeng Yu, “Semiconductor Memory Devices and Circuits”, CRC Press, 2022
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Capacitor Model
Assuming that VS = VD = VB = 0, the stored charges (QFG)
after the program can be written as:
Cg: tunnel oxide capacitance Gate coupling ratio:
Cs: coupling capacitance between the floating gate and the source • Determines how effectively the externally applied control
Cd: coupling capacitance between the floating gate and the drain
Ck: inter-poly dielectric capacitance. voltage could modulate the internal floating gate voltage.
• Degrades with scaling
Shimeng Yu, “Semiconductor Memory Devices and Circuits”, CRC Press, 2022
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NAND Array Organization
Shimeng Yu, “Semiconductor Memory Devices and Circuits”, CRC Press, 2022
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NAND Array Organization
• SSL/GSL: Select transistors on
source or drain side (regular
MOSFETs !!)
• Page: Cells sharing a common
WL constitute a page
• Block: Collection of pages which
share a common source line
Yoon, “The Fundamentals of NAND Flash Memory”, IEEE Solid State Circuits Magazine, 2022
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Program
JFN: current density,
Eox: electric field in the oxide
ΦB: barrier height of the injecting interface
ℏ: reduced Planck constant
m0: electron mass in vacuum
m*: effective electron mass
Q: basic charge quantity.
• F-N Tunneling: Transport of charge carriers through triangular barrier under sufficiently high electric fields
• It is used to write and erase the data Oxide barrier is designed such that direct tunnelling is avoided.
• For program/erase operations, F-N tunneling current is very small (typically < pA)
• All the electrons involved in the F-N tunneling contribute to the program/erase resulting in very high (~100%)
programming efficiency
Question:
• Can we use holes to store data?
• Can we use Channel Hot Electrons (CHE) for program operation?
Shimeng Yu, “Semiconductor Memory Devices and Circuits”, CRC Press, 2022
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Program
• Typically Blocking oxide (BO) is thicker than Tunnel oxide (TO)
• Band bending in TO is more than that in BO – prevents
injected charges to stay in FG and not move further to CG
• Typical program time is 10 to 100us e- FN Tunneling
e-
TO
BO
TO BO
Flat band condition +ve Gate potential applied
Micheloni et al., “3D Flash Memories”, Springer book
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Program
Incremental Step Pulse Programming (ISPP)
For better control of cell Vt after programming, ISPP
is employed:
• Program voltage is increased gradually over a
certain number of pulses &
• ‘Program verify’ is done after each pulse
Program operation happens at “Page” level.
Question:
• Does increasing Vpgm result in increasing number of
electrons stored in FG?
Yoon, “The Fundamentals of NAND Flash Memory”, IEEE Solid State Circuits Magazine, 2022
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Program
Program Inhibit
Cell (A) to be
programmed
Cell (B) to be
programmed
Micheloni et al., “Inside NAND Flash Memories”, Springer book
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Erase Operation
• F-N tunneling is used to erase the data as well!!
• Erase operation happens at “block” level which share common substrate
• Typical erase time is 1ms
Shimeng Yu, “Semiconductor Memory Devices and Circuits”, CRC Press, 2022
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Read
Read
Biases during Read
Micheloni et al., “Inside NAND Flash Memories”, Springer book
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Read/Program Verify
SLC MLC
Micheloni et al., “Inside NAND Flash Memories”, Springer book
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2D to 3D NAND
Micheloni et al., “Inside Solid State Drives”, Springer book
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2D to 3D NAND
Micheloni et al., “Inside Solid State Drives”, Springer book
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Floating Gate vs Charge Trap
• Conductive poly-Si was used for FG devices in 2D NAND
• In 3D NAND, FG devices have been used, but predominantly SiN
based CT devices are in use due to the following advantages:
• Better scalability:
• No need to separate the storage layer among the cells since SiN is a
dielectric material
• Ease of fabrication since SiN is deposited after etching memory holes
which can be larger – especially useful when large number of WL layers
are there
• Less coupling between neighbour cells
Micheloni et al., “3D Flash Memories”, Springer book
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3D NAND Cell/Array Structure
3D NAND Cell NAND Array
Micheloni et al., “3D Flash Memories”, Springer book
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Fabrication
Layer Pattern & MH Etch Ch/Ox/CTL BL Contact Pattern for
Deposition Etch for BLs Deposition Deposition BL Contacts
Micheloni et al., “3D Flash Memories”, Springer book
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NAND Cell/Array Structure
NAND Die Hierarchy:
Cells (WL/BL) Page Blocks Planes Die
Yoon, “The Fundamentals of NAND Flash Memory”, IEEE Solid State Circuits Magazine, 2022
Micheloni et al., “3D Flash Memories”, Springer book yasasvigpr@[Link] 24
Outline
• Introduction
• NAND Fundamentals
• NAND Reliability Issues
• Flash memory for AI/ML
• Future Trends
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Reliability Issues
• Stability of “Vt” decides how reliable a NAND cell is !!
• Quantified by “Vt Width” or “Vt Margin”
• Data can be written in SLC/MLC/TLC/QLC formats
• Any phenomenon that changes the original Vt distribution
can change the data stored and hence leads to errors when
read back
1. Disturbs: Program, Read
2. Data Retention
3. Cross Temperature (Program & Read operations for a data set
happen at different temperatures)
• All these typically depend on parameters such as EP
Cycling, Temperature
Micheloni et al., “3D Flash Memories”, Springer book
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Program Disturb
Cell to be Cell to be
programmed programmed
Program disturb
Pass disturb
Biases during Program Program Disturb in 2D NAND
Spinelli et al., “Reliability of NAND Flash Memories: Planar cells and Emerging Issues in 3D Devices”, Computers, 2017
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Program Disturb
Vt shifts as [Link] program pulses increase
Lee et al., “A New Programming Disturbance Phenomenon in NAND Flash Memory by Source/Drain Hot-electrons generated by GIDL current”, 21st IEEE Non-Volatile
Semiconductor Memory Workshop, 2006 yasasvigpr@[Link] 28
Read Disturb
• ‘Soft programming’ happens on unselected
cells due to Vpass
• Typically, lower state cells are more
impacted – specifically cells in Erase state
Read Disturb in 2D/3D NAND
Spinelli et al., “Reliability of NAND Flash Memories: Planar cells and Emerging Issues in 3D Devices”, Computers, 2017
Cai et al., “Read Disturb Errors in MLC NAND Flash Memory: Characterization, Mitigation, and Recovery”, 45th Annual IEEE/IFIP International Conference on 29
Dependable Systems and Networks, 2015 yasasvigpr@[Link]
Data Retention
• It is expected that the stored data is preserved and unaltered
for a very long time with no biases applied
• However, electrons leak out of CTL with time leads to data
loss !!
• Different mechanisms lead to charge loss in flash memories
• Vertical loss:
• Trap Assisted Tunnelling (TAT)
• Charge de-trapping
• Horizontal loss:
• Lateral Charge Migration
Li et al., “Investigation of charge loss mechanisms IN 3D TANOS cylindrical junction-less charge trapping memory”, 12th IEEE International Conference on Solid-State
and Integrated Circuit Technology (ICSICT), 2014 yasasvigpr@[Link] 30
Data Retention
• Trap Assisted Tunneling (TAT):
• Electrons leak out of CTL through traps (created during EP cycling) in the TO
• Strongly dependent on EP cycling degradation
• Charge detrapping:
• A cell’s Vt depends not only on the charge in CTL, but also on any charge in TO.
• If the oxide charge detraps, Vt shift occurs
• Strongly dependent on EP cycling degradation
Li et al., “Investigation of charge loss mechanisms IN 3D TANOS cylindrical junction-less charge trapping memory”, 12th IEEE International Conference on Solid-State
and Integrated Circuit Technology (ICSICT), 2014 yasasvigpr@[Link] 31
Data Retention
• Lateral charge migration (LCM):
• Electrons from one NAND cell migrate along CTL into intercell region leading to Vt
reduction
• Strongly dependent on temperature
• With scaling, LCM is going to be the dominant charge loss mechanism
Li et al., “Investigation of charge loss mechanisms IN 3D TANOS cylindrical junction-less charge trapping memory”, 12th IEEE International Conference on Solid-State
and Integrated Circuit Technology (ICSICT), 2014 yasasvigpr@[Link] 32
Outline
• Introduction
• NAND Fundamentals
• NAND Reliability Issues
• Flash memory for AI/ML
• Future Trends
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NAND & NOR Flash
Array Structure
NOR NAND
[Link]
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Flash Memory for AI/ML
DNNs involve Vector Matrix Multiplications (VMMs)
MAC Operations
[Link]
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Flash Memory for AI/ML
• Multiplication of the input voltage and the conductance of the device gives the current
• Currents from multiple devices connected to one bit-line are summed up by Kirchhoff’s current law.
• Flash memory:
• Cells are programmed to store different ‘weights’
• High density 🡪 suitable for DNN algorithms requiring huge parameter size
[Link]
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NOR based Implementation
• Demonstrated very high energy efficiency compared to other accelerators
[Link]
[Link] yasasvigpr@[Link] 37
NAND based Implementation
Demonstrated better accuracy compared to RRAM implementation
S.-T. Lee et al., “NAND Flash Based Novel Synaptic Architecture for Highly Robust and High-Density QNNs”, vol 8, IEEE ACCESS, 2020
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Outline
• Introduction
• NAND Fundamentals
• NAND Reliability Issues
• Flash memory for AI/ML
• Future Trends
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Future Trends
Scaling Challenges:
• Physical scaling (XYZ)
• High aspect ratio etch
• Layer-to-layer variations, LCM
• Increase in stack height?
• Fab process improvements are the key!!
• Logical scaling:
• SLC MLC TLC QLC PLC? HLC?
• Cell device engineering is the key!!
Akira Goda, “Recent progress on 3D NAND Flash Technologies”, Electronics, 2021
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Future Trends
Performance Challenges:
• Write bandwidth = page size * [Link] planes/Tprog
• Need to device new methods to reduce Tprog
specifically for QLC!!
• CMOS Architecture changes
• CuA is already widely adopted
• Work on WoW technology is in progress!!
• Block size
• Increase in block size can impact overall data
management especially erase operation
• Work on block-by-deck is in progress!!
Akira Goda, “Recent progress on 3D NAND Flash Technologies”, Electronics, 2021
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Thank You
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