Tutorial 2 Solution

September 17, 2014

1 Determining the midpoint voltage of various configura-

tions
Midpoint volatage in CMOS Inverter is Vi = Vo = VM

1.1 Wp = 6λ and Wn = 4λ
Assuming NMOS is in velocity saturation and PMOS is in saturation region.
IDn (velsat) = IDp (sat)
V Dsatn (VDD −VM −|VT p |)2
µn Cox ( W
L )n V D satn (VM − VT n − 2 ) = µp Cox ( W
L )p 2
2
200( 42 )0.3(VM − 0.35 − 0.3
2 ) = 80( 62 ) (1.8−VM2−0.35)
Solvingf orVM
VM = 0.853V
VGS − Vt VDS V Dsat Region of Operation
NMOS 0.503 0.853 0.3 Velocity saturation The assumption is correct.
PMOS 0.597 0.947 0.6 Saturation

1.2 Wp = 30λ and Wn = 21λ

Assuming both are in velocity saturation region.
IDn (velsat) = IDp (sat)
V Dsatn |V Dsatp |
µn Cox ( W
L )n V D satn (VM − VT n − 2 ) = µp Cox ( W
L )p |V D satp |(VDD − VM − |VT p | − 2 )
200( 21
2 )0.3(VM − 0.35 −
0.3
2 ) = 80( 2 )0.3(1.8 − VM − 0.35 − 0.6
30
2 )
Solvingf orVM
VM = 0.736V
VGS − Vt VDS V Dsat Region of Operation
NMOS 0.386 0.736 0.3 Velocity saturation The assumption is correct.
PMOS 0.714 1.063 0.6 Velocity saturation

1.3 For CMOS Reference Inverter - Wp = 6λ and Wn = 3λ

Assuming NMOS is in velocity saturation and PMOS is in saturation region.
IDn (velsat) = IDp (sat)
V Dsatn (VDD −VM −|VT p |)2
µn Cox ( W
L )n V D satn (VM − VT n − 2 ) = µp Cox ( W
L )p 2
2
200( 32 )0.3(VM − 0.35 − 0.3
2 ) = 80( 62 ) (1.8−VM2−0.35)
Solvingf orVM
VM = 0.9V

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 VGS − Vt VDS V Dsat Region of Operation
NMOS 0.55 0.9 0.3 Velocity saturation The assumption is correct.
PMOS 0.55 0.9 0.6 Saturation

1.4 Wp = 12λ and Wn = 24λ

Assuming both are in velocity saturation region.
IDn (velsat) = IDp (velsat)
V Dsatn |V Dsatp |
µn Cox ( W
L )n V D satn (VM − VT n − 2 ) = µp Cox ( W
L )p |V D satp |(VDD − VM − |VT p | − 2 )
200( 24
2 )0.3(VM − 0.35 −
0.3
2 ) = 80( 2 )0.6(1.8 − VM − 0.35 − 0.6
12
2 )
Solvingf orVM
VM = 0.685V
VGS − Vt VDS V Dsat Region of Operation
NMOS 0.335 0.685 0.3 Velocity saturation The assumption is correct.
PMOS 0.765 1.114 0.6 Velocity saturation

2 Noise margin for inverter’s with different loads

2.1 Resistor Load
When Vi = 0V < VT n (0.35V ) =⇒ Driver Transistor is in Cut-off region.
IL = ID = 0A
Output Voltage Vo = VDD − IL RL = VDD = 1.8
VOH = 1.8 V
When Vi = VDD VGS = VDD = 1.8V
Assuming Vo = VOL is very low such that less than VDsat = 0.3V Transistor is in linear region.
IRL = IDS (linear)
2
VDD −VOL VOL
RL = (W
L )µn COX {(VDD − VT )VOL − 2 }
2
1.8−VOL VOL
60K = ( 12 )200µ{(1.8 − 0.35)VOL − 2 }
Solving for VOL
VOL = 0.051 V
Assumption is correct.
This inverter configuration dissipates power when output volatage is VOL
Power = I V = ( VDDR−V
L
OL
)VDD
VOH = 1.8 V
VOL = 0.051 V

Vi Vo Pstatic
1.8 V 0.051 V 52.4 µ W
0.0 V 1.8 V 0µW

2.2 Saturated NMOS Load

When Vi = 0V < VT n (0.35V ) =⇒ Driver Transistor is in Cut-off region.
IL = ID = 0A
Output Voltage Vo = VDD − VT n

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VOH = 1.8 - 0.35 = 1.45 V
When Vi = VDD VGS = VDD = 1.8V Vo = VOL
Assuming Load transistor is in Velocity saturation and driver is in linear region
IDD (linear) = IDL (velsat)
VOL V Dsatn
µn Cox ( W
L )D VOL (VDD − VT n − 2 )= µn Cox ( W
L )L V D satn (VDD − VT n − VOL − 2 )
VOL
200µ( 12 )VOL (1.8 − 0.35 − 2 )= 200µ( 21 )0.3(1.8 − 0.35 − VOL − 0.3
2 )
Solving for VOL
VOL = 0.239 V
Assumption is correct.
This inverter configuration dissipates power when output volatage is VOL
Power = I V = 127 µA 1.8 V = 229.1 µ W
VOH = 1.45 V
VOL = 0.239 V

Vi Vo Pstatic
1.8 V 0.239 V 229.1 µ W
0.0 V 1.45 V 0µW

2.3 load NMOS connected to a Gate voltage of 3v

When Vi = 0V < VT n (0.35V ) =⇒ Driver Transistor is in Cut-off region.
IL = ID = 0A
Output Voltage Vo = VDD Since the Voltage on Gate is higher than Vdd, output can be all the
way upto supply
VOH = 1.8 V
When Vi = VDD VGS = VDD = 1.8V Vo = VOL
Assuming Load transistor is in Velocity saturation and driver is in Velocity saturation region
IDD (velsat) = IDL (velsat)
V Dsatn V Dsatn
µn Cox ( W
L )D V D satn (VDD − VT n − 2 )= µn Cox ( W
L )L V D satn (VDD − VT n − VOL − 2 )
200µ( 12 )0.3(1.8 − 0.35 − 0.3
2 )= 200µ( 1 )0.3(3.0 − 0.35 − VOL − 0.3
2
2 )
Solving for VOL
VOL = VGG − VDD = 1.2 V ¿ V Dsatn
Assumption is correct.
This inverter configuration dissipates power when output volatage is VOL
Power = I V = 156 µA 1.8 V = 280.8 µ W
VOH = 1.8 V
VOL = 1.2 V

Vi Vo Pstatic
1.8 V 1.2 V 280.8 µ W
0.0 V 1.8 V 0µW

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2.4 Standard Reference CMOS inverter
When Vi = 0V < VT n (0.35V ) =⇒ NMOS Transistor is in Cut-off region.
IL = ID = 0A
Output Voltage Vo = VDD
VOH = 1.8 V
When Vi = VDD VSG (P M OS) = 0V PMOS Transistor is in Cut-off region
Vo = VOL = 0.0V
IL = ID = 0A
This inverter configuration has no current and hence 0W power in either of the input configuration
Power = I V = 0 µA 1.8 V = 0 µ W
VOH = 1.8 V
VOL = 0.0 V

Vi Vo Pstatic
1.8 V 0.0 V 0µW
0.0 V 1.8 V 0µW

3 Propogation delay estimation of a reference inverter driv-

ing a load
3.1 reference CMOS inverter
Estimating the output load capacitance.

CL = Cg,p2 + Cg,n2 + Cdif f,p1 + Cdif f,n1 + 2 × Cover,p1 + 2 × Cover,n1

Cg,n2 = Cox W L = 8 × 3λ × 2λ = 48λ2 = 0.3888f F

Cg,p2 = Cox W L = 8 × 6λ × 2λ = 96λ2 = 0.7776f F

Cdif f,p1 = Cj × ADp1 + Cjsw × P Dp1 = 1 × 30λ2 + 0.22 × 16λ = 0.5598f F

Cdif f,n1 = Cj × ADn1 + Cjsw × P Dn1 = 1 × 19λ2 + 0.22 × 15λ = 0.4509f F

2 × Cover,p1 = 2 × Cover per length × Wp1 = 0.8316f F

2 × Cover,n1 = 2 × Cover per length × Wn1 = 0.4158f F

T aking Req,n = 11.5KΩ and Req,p = 8KΩ

Req,n +Req,p
Ref f = 2

Tpd = 0.69 × Ref f CL = 23.038ps

3.2 Another CMOS inverter of size: PMOS 10, NMOS 8

The diffusion and overlap capacitance of the driver inverter will remain same, only thing that
will change is the gate capacitance.

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 Cg,n2 = Cox W L = 8 × 8 × 3λ × 2λ = 8 × 48λ2 = 3.1104f F

Cg,p2 = Cox W L = 8 × 10 × 3λ × 2λ = 10 × 48λ2 = 3.888f F

CL = 9.2565f F

Tpd = 0.69 × Ref f CL = 62.273ps

3.3 A fixed external capacitance of 5fF

Other than the diffusion and overlap capacitance (Same as above) we will have to include a fixed
external capacitance.

CL = 5 + Cdif f + Cover = 7.2581f F

Tpd = 0.69 × Ref f CL = 48.8289ps

4 Delay estimation using Elmore’s delay model

Estimate the propagation delay for the circuit shown in Fig. 1

Figure 1: RC Ladder

4.1 Theoretical Calculation

Elmore Delay Model gives an approximate delay between both the terminal nodes of the circuits
if it can be represented by a RC ladder. This model does not consider the delay due to branching.
In Fig. 1 the approximate delay between node 1 and node 5 can be determined as,

tpd = R1 (C1 + C2 + C3 + C4 ) + R3 (C3 + C4 ) + R4 (C4 )

Substituting values we get, tpd = 70ps

4.2 Spice simulation

The above model is simulated, both rising and falling propagation delays are estimated. In order
to achieve this we select the input frequency much lower than the maximum frequency it can
support. This will allow the output to saturate at each clock cycle. The spice code for the above
simulation is shown below,

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Spice Code
Tutorial 3, Question 1: Elmore’s Formulae !
*RC circuit
.param SUPPLY=2v

vin 1 0 PULSE 0 {SUPPLY} 0p 100p 100p 500ps 1000ps

*Input frequency = 1GHz.
r1 1 2 10k
c1 2 0 1f
r2 2 4 10k
c2 4 0 1f
r3 2 3 10k
c3 3 0 1f
r4 3 5 10k
c4 5 0 1f

.control
tran 100ps 3000ps
plot v(1) v(5) xlabel Time ylabel Voltage title ’RC Ladder Circuit’
.endc
.end

simulation results
Simulation graph are depicted in Fig. 2a. Propagation delay is the time delay between Vdd/2
points of input and output. In Fig. 2a, we determine the propagation delay when output raises
from 0 to Vdd .

tpd |0−>Vdd = (1.105 × 10−9 ) − (1.05 × 10−9 ) = 55ps

In Fig. 2a, we determine the propagation delay when output falls from Vdd to 0.

tpd |Vdd −>0 = (1.71 × 10−9 ) − (1.65 × 10−9 ) = 60ps

(a)

Figure 2: (a) Variation of voltage at node 5 with respect to variation in node

Legend: Red-Input signal and green-Output signal

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 Delays estimated using Elmore’s delay model are very close to the actual delays when simulated
in spice.