Microprocessor Addressing Modes
1. Introduction
In a microprocessor, an addressing mode defines how the CPU identifies the location of
the data (operand) that an instruction needs to execute.
The operand may be in a register, in memory, or given directly within the instruction.
Addressing modes provide flexibility in accessing data and allow efficient programming.
2. Importance of Addressing Modes
Addressing modes are used to:
Specify how and where operands are fetched or stored.
Simplify programming and enhance code efficiency.
Reduce instruction size and execution time.
Allow use of constants, registers, or memory locations flexibly.
3. Types of Addressing Modes
Microprocessors such as the 8085, 8086, and 8051 use the following common addressing
modes:
A. Immediate Addressing Mode
The operand (data) is specified directly in the instruction itself.
The data immediately follows the opcode in memory.
Example (8085):
MVI A, 45H
Here, 45H is the immediate data loaded into register A.
Example (8086):
MOV AL, 25H
The immediate value 25H is moved to AL.
Diagram:
Instruction: [Opcode | Data]
B. Register Addressing Mode
The operand is stored in a register, and the instruction specifies the register name.
No memory access is required, so this mode is very fast.
Example (8085):
MOV B, C
Contents of register C are copied into register B.
Example (8086):
MOV AX, BX
Transfers data from BX to AX.
Diagram:
┌──────────────┐
│ Register C → │ Register B │
└──────────────┘
C. Direct Addressing Mode
The instruction specifies the memory address where the operand is stored.
The processor fetches data directly from that address.
Example (8085):
LDA 2050H
Load accumulator with the contents of memory address 2050H.
Example (8086):
MOV AL, [1234H]
Load AL with the contents of memory location 1234H.
Diagram:
Memory[2050H] → Accumulator (A)
D. Indirect Addressing Mode
The address of the operand is held in a register pair (like HL, DE in 8085, or BX
in 8086).
The CPU uses the register contents as the address of the operand.
Example (8085):
MOV A, M
Move contents of memory location pointed by HL pair into A.
Example (8086):
MOV AL, [BX]
Load AL with the data from memory whose address is in BX.
Diagram:
HL → 2050H
Memory[2050H] → A
E. Register Indirect Addressing Mode
Similar to indirect, but data transfer occurs between registers and memory through
a pointer register.
Example (8085):
MOV M, A
Store contents of accumulator into memory pointed by HL.
Example (8051):
MOV A, @R0
Move the contents of memory location pointed by R0 into A.
F. Indexed Addressing Mode
Used mainly in 8086 and advanced microprocessors.
The effective address of the operand is generated by adding a constant
(displacement) to the contents of an index register (e.g., SI or DI).
Example (8086):
MOV AL, [SI + 05H]
The operand is fetched from memory location (SI + 05H).
Diagram:
Effective Address = SI + Displacement
G. Implicit Addressing Mode
The operand is implied in the instruction; not specified explicitly.
Example (8085):
CMA
Complement accumulator; operand is implicit (Accumulator A).
Example (8086):
CLC
Clear carry flag; no operand specified.
4. Summary Table
Addressing Example
Description Example (8086)
Mode (8085)
Immediate Operand given in instruction MVI A, 32H MOV AL, 32H
Register Operand in register MOV B, C MOV AX, BX
Operand in specific memory
Direct LDA 2050H MOV AL, [1234H]
address
Indirect Address stored in register pair MOV A, M MOV AL, [BX]
MOV AL,
Indexed Address = base + offset — [SI+05H]
Implicit Operand implied CMA CLC
5. Teaching Aids
Diagrams: Use block diagrams showing register, memory, and bus connections.
Practical examples: Demonstrate on an 8085 simulator or emulator.
Exercises: Have learners write small programs using different addressing modes
Microprocessor input and Output methods
1. Introduction
Microprocessors communicate with the outside world (such as keyboards, displays,
sensors, and storage devices) using input/output (I/O) interfaces. These interfaces allow
the processor to exchange data with external devices efficiently. There are several methods
used to perform I/O operations, depending on how data transfer is controlled between the
microprocessor and peripheral devices.
2. Types of Input/Output Methods
2.1 Memory-Mapped Input/Output (MMIO)
In memory-mapped I/O, peripheral devices are assigned specific address locations in the
same address space as the system memory. This means that the same instructions used for
reading and writing data to memory can also be used to access I/O devices.
Key Features:
• The I/O devices share the same address bus and data bus as memory.
• No separate I/O instructions are required.
• Each I/O port has a unique address like a memory location.
• Allows large address range and flexible addressing.
Advantages:
• Uniform addressing and easy programming.
• Enables the use of all memory-related instructions (like MOV, ADD).
• Efficient use of hardware.
Disadvantages:
• Reduces the memory address space available for RAM and ROM.
• Slightly more complex address decoding.
2.2 Programmed Memory-Mapped Input/Output
In programmed I/O, the processor actively controls all data transfers between itself and
peripheral devices. The CPU executes instructions that directly read from or write to I/O
ports. When programmed I/O is combined with memory-mapped addressing, it becomes
programmed memory-mapped I/O — meaning the CPU uses normal memory access
instructions to transfer data, but all transfers are manually handled by software (the
program).
Operation Steps:
1. CPU issues a command to the I/O device.
2. The CPU continuously checks the status of the device (e.g., ready or not).
3. When the device is ready, CPU reads/writes the data.
4. Process repeats for each data byte/word.
Advantages:
• Simple to implement.
• No additional hardware control required.
Disadvantages:
• CPU is fully occupied with I/O tasks.
• Inefficient for high-speed devices or large data transfers.
2.3 Handshake Controlled Input/Output
Handshake I/O is a synchronization method where both the microprocessor and the I/O
device exchange signals to coordinate data transfer. It ensures that data is transferred only
when both parties are ready, preventing data loss or corruption.
Key Control Signals:
• READY / ACK (Acknowledge): Sent by the device to indicate it is ready.
• STROBE / REQ (Request): Sent by the CPU to indicate a valid data transfer.
Operation:
1. The CPU places data on the bus and sends a STROBE signal.
2. The I/O device, after receiving the data, sends an ACK signal.
3. The CPU waits for the ACK before sending the next byte.
Advantages:
• Reliable data transfer.
• Suitable for devices with varying speeds.
Disadvantages:
• Requires additional control lines.
• More complex circuitry and slower transfer rate compared to DMA.
2.4 Polled Input/Output (Polling Method)
In polled I/O, the CPU repeatedly checks (polls) the status of an I/O device until it becomes
ready to send or receive data. No interrupt signals are used — instead, the CPU
continuously executes a loop checking the device’s status register.
Operation Steps:
1. CPU sends a read/write command to the device.
2. CPU reads the status flag of the device.
3. If the device is not ready, CPU keeps checking.
4. When the device becomes ready, CPU performs the data transfer.
Advantages:
• Simple implementation.
• No special hardware (interrupts) needed.
Disadvantages:
• Wastes CPU time (busy waiting).
• Inefficient for multitasking or slow devices.
3. Summary Table
I/O Method Control Type CPU Speed Complexity Use Case
Involvement
Memory- Address Medium Medium Moderate General-
Mapped I/O decoding purpose I/O
Programmed Software High Slow Simple Low-speed
Memory- controlled devices
Mapped I/O
Handshake Signal Medium Medium Moderate Reliable
Controlled synchronizatio transfers
I/O n
Polled I/O Status polling High Slow Simple Simple
peripherals