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TPS54528
SLVSAY4C – JULY 2011 – REVISED MARCH 2014

TPS54528 4.5-V To 18-V Input, 5-A Synchronous Step-Down Converter With Eco-Mode™
1 Features 3 Description
1• D-CAP2™ Mode Enables Fast Transient The TPS54528 is an adaptive on-time D-CAP2™
Response mode synchronous buck converter. The TPS54528
enables system designers to complete the suite of
• Low Output Ripple and Allows Ceramic Output various end-equipment power bus regulators with a
Capacitor cost effective, low component count, low standby
• Wide VIN Input Voltage Range: 4.5 V to 18 V current solution. The main control loop for the
• Output Voltage Range: 0.76 V to 6 V TPS54528 uses the D-CAP2™ mode control that
provides a fast transient response with no external
• Highly Efficient Integrated FETs Optimized compensation components. The adaptive on-time
for Lower Duty Cycle Applications control supports seamless transition between PWM
– 65 mΩ (High Side) and 36 mΩ (Low Side) mode at higher load conditions and Eco-mode™
• High Efficiency, less than 10 μA at shutdown operation at light loads. Eco-mode™ allows the
• High Initial Bandgap Reference Accuracy TPS54528 to maintain high efficiency during lighter
load conditions. The TPS54528 also has a proprietary
• Adjustable Soft Start circuit that enables the device to adopt to both low
• Pre-Biased Soft Start equivalent series resistance (ESR) output capacitors,
• 650-kHz Switching Frequency (fSW) such as POSCAP or SP-CAP, and ultra-low ESR
ceramic capacitors. The device operates from 4.5-V
• Cycle By Cycle Over Current Limit to 18-V VIN input. The output voltage can be
• Auto-Skip Eco-mode™ for High Efficiency at Light programmed between 0.76 V and 6 V. The device
Load also features an adjustable soft start time. The
TPS54528 is available in the 8-terminal DDA
2 Applications package, and designed to operate from –40°C to
85°C.
• Wide Range of Applications for Low Voltage
System Device Information
– Digital TV Power Supply ORDER NUMBER PACKAGE BODY SIZE
– High Definition Blu-ray Disc™ Players TPS54528DDA HSOP (8) 4,89 mm × 3,9 mm
– Networking Home Terminal
– Digital Set Top Box (STB)

4 Simplified Schematic

1.05-V, Load Transient Response

TPS54528

Vout (50 mV/div)

Iout (2 A/div)

t - Time - 100 ms/div

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54528
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Table of Contents
1 Features .................................................................. 1 8.3 Feature Description................................................... 9
2 Applications ........................................................... 1 8.4 Device Functional Modes........................................ 10
3 Description ............................................................. 1 9 Applications and Implementation ...................... 12
4 Simplified Schematic............................................. 1 9.1 Application Information............................................ 12
9.2 Typical Application ................................................. 12
5 Revision History..................................................... 2
6 Terminal Configuration and Functions................ 3 10 Power Supply Recommendations ..................... 15
7 Specifications......................................................... 4 11 Layout................................................................... 15
11.1 Layout Guidelines ................................................. 15
7.1 Absolute Maximum Ratings ...................................... 4
11.2 Layout Example .................................................... 16
7.2 Handling Ratings....................................................... 4
11.3 Thermal Information .............................................. 17
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information ................................................. 5 12 Device and Documentation Support ................. 18
7.5 Electrical Characteristics........................................... 5 12.1 Documentation Support ........................................ 18
7.6 Timing Requirements - On-Time Timer Control........ 6 12.2 Trademarks ........................................................... 18
7.7 Typical Characteristics .............................................. 6 12.3 Electrostatic Discharge Caution ............................ 18
12.4 Glossary ................................................................ 18
8 Detailed Description .............................................. 9
8.1 Overview ................................................................... 9 13 Mechanical, Packaging, and Orderable
8.2 Functional Block Diagram ......................................... 9
Information ........................................................... 18

5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (May 2012) to Revision C Page

• Formatted data sheet to meet new template requirements ................................................................................................... 1

• Added Table of Contents, and moved Revision History to page 2. ...................................................................................... 3
• Moved ABS Max, Handling Ratings, ROC, Thermal Info, and Electrical Characteristics tables to the new
"Specifications" section. ......................................................................................................................................................... 4
• Added Maximum Power Dissipation graph............................................................................................................................. 8
• Added "Power Supply Recommendations" section ............................................................................................................. 15
• Added "Device and Documentation Support" section ......................................................................................................... 18

Changes from Revision A (January 2012) to Revision B Page

• Changed tOFF(MIN) From: 310 ns To: 330 ns............................................................................................................................ 6

Changes from Original (July 2011) to Revision A Page

• Added CONDITIONS statement at the Typical Characteristics section heading ................................................................... 6

• Changed 2-µA to 6µA in Soft Start and Pre-Biased Soft Start subsection and denominator in equation 2....................... 9

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6 Terminal Configuration and Functions

DDA-8 PACKAGE
(TOP VIEW)

1 EN VIN 8

2 VFB TPS54528 VBST 7

Exposed
3 VREG5 Thermal Pad SW 6

4 SS GND 5

Terminal Functions
TERMINAL
DESCRIPTION
NAME NO.
EN 1 Enable input control. EN is active high and must be pulled up to enable the device.
VFB 2 Converter feedback input. Connect to output voltage with feedback resistor divider.
5.5 V power supply output. A capacitor (typical 1 µF) should be connected to GND. VREG5 is not active
VREG5 3
when EN is low.
SS 4 Soft-start control. An external capacitor should be connected to GND.
Ground terminal. Power ground return for switching circuit. Connect sensitive SS and VFB returns to
GND 5
GND at a single point.
SW 6 Switch node connection between high-side NFET and low-side NFET.
Supply input for the high-side FET gate drive circuit. Connect 0.1µF capacitor between VBST and SW
VBST 7
terminals. An internal diode is connected between VREG5 and VBST.
VIN 8 Input voltage supply terminal.
Exposed Thermal Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be connected to
Back side
Pad GND.

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7 Specifications
7.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
MIN MAX
VIN, EN –0.3 20
VBST –0.3 26
VBST (10 ns transient) –0.3 28
Input voltage range VBST (vs SW) –0.3 6.5 V
VFB, SS –0.3 6.5
SW –2 20
SW (10 ns transient) –3 22
VREG5 –0.3 6.5
Output voltage range V
GND –0.3 0.3
Voltage from GND to thermal pad, Vdiff –0.2 0.2 V
Operating junction temperature, TJ –40 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 Handling Ratings

MIN MAX UNIT
Tstg Storage temperature range –55 150 °C
Human Body Model (HBM) 2 kV
Electrostatic discharge
Charged Device Model (CDM) 500 V

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIN Supply input voltage 4.5 18 V
VBST –0.1 24
VBST (10 ns transient) –0.1 27
VBST(vs SW) –0.1 5.7
SS –0.1 5.7
VI Input voltage EN –0.1 18 V
VFB –0.1 5.5
SW –1.8 18
SW (10 ns transient) –3 21
GND –0.1 0.1
VO Output voltage VREG5 –0.1 5.7 V
IO Output Current IVREG5 0 5 mA
TA Operating free-air temperature –40 85 °C
TJ Operating junction temperature –40 150 °C

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7.4 Thermal Information

TPS54528
THERMAL METRIC (1) UNIT
DDA (8)
θJA Junction-to-ambient thermal resistance 43.5
θJCtop Junction-to-case (top) thermal resistance 49.4
θJB Junction-to-board thermal resistance 25.6
°C/W
ψJT Junction-to-top characterization parameter 7.4
ψJB Junction-to-board characterization parameter 25.5
θJCbot Junction-to-case (bottom) thermal resistance 5.2

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

over operating free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
VIN current, TA = 25°C, EN = 5 V,
IVIN Operating - non-switching supply current 900 1200 μA
VFB = 0.8 V
IVINSDN Shutdown supply current VIN current, TA = 25°C, EN = 0 V 3.6 10 μA
LOGIC THRESHOLD
EN high-level input voltage EN 1.6 V
VEN
EN low-level input voltage EN 0.6 V
VFB VOLTAGE AND DISCHARGE RESISTANCE
TA = 25°C, VO = 1.05 V, IO = 10 mA, Eco-
771 mV
mode™ operation
TA = 25°C, VO = 1.05 V, continuous mode
VFBTH VFB threshold voltage 757 765 773 mV
operation
TA = -40 to 85°C, VO = 1.05 V, continuous
751 765 779 mV
mode operation (1)
IVFB VFB input current VFB = 0.8 V, TA = 25°C 0 ±0.15 μA
VREG5 OUTPUT
TA = 25°C, 6.0 V < VIN < 18 V,
VVREG5 VREG5 output voltage 5.2 5.5 5.7 V
0 < IVREG5 < 5 mA
VLN5 Line regulation 6 V < VIN < 18 V, IVREG5 = 5 mA 25 mV
VLD5 Load regulation 0 mA < IVREG5 < 5 mA 100 mV
IVREG5 Output current VIN = 6 V, VREG5 = 4.0 V, TA = 25°C 60 mA
MOSFET
High side switch resistance 25°C, VBST - SW = 5.5 V 65 mΩ
RDS(on)
Low side switch resistance 25°C 36 mΩ
CURRENT LIMIT
Iocl Current limit L out = 1.5 μH (1) 5.6 6.4 7.9 A
THERMAL SHUTDOWN
(1)
Shutdown temperature 165
TSDN Thermal shutdown threshold (1)
°C
Hysteresis 35

(1) Not production tested.

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Electrical Characteristics (continued)

over operating free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SOFT START
SS charge current VSS = 1 V 4.2 6 7.8 μA
ISS
SS discharge current VSS = 0.5 V 0.1 0.2 mA
UVLO
Wake up VREG5 voltage 3.45 3.75 4.05
UVLO UVLO threshold V
Hysteresis VREG5 voltage 0.19 0.32 0.45

7.6 Timing Requirements - On-Time Timer Control

MIN TYP MAX UNIT
tON On time VIN = 12 V, VO = 1.05 V 150 ns
tOFF(MIN) Minimum off time TA = 25°C, VFB = 0.7 V 260 330 ns

7.7 Typical Characteristics

VIN = 12 V, TA = 25°C (unless otherwise noted).

1200 7

6
1000
Ivccsdn - Shutdown Current - mA
ICC - Supply Current - mA

5
800

4
600
3

400
2

200
1

0 0
-50 0 50 100 150 -50 0 50 100 150
TJ - Junction Temperature - °C TJ - Junction Temperature - °C
VI = 12 V VI = 12 V

Figure 1. VIN Current vs Junction Temperature Figure 2. VIN Shutdown Current vs

Junction Temperature
50 1.1

45

40
1.075 VIN = 18 V
VO - Output Voltage - V
EN - Input Current - mA

35
VIN = 12 V
30

25 1.05

20 VIN = 5 V

15
1.025
10

0 1
0 5 10 15 20 0 1 2 3 4 5
EN - Input Voltage - V IO - Output Current - A
VI= 18 V

Figure 3. EN Current vs EN Voltage Figure 4. 1.05-V Output Voltage vs Output Current

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Typical Characteristics (continued)

VIN = 12 V, TA = 25°C (unless otherwise noted).
1.08 100
VO = 3.3 V
VO = 2.5 V
VO = 1.8 V
90

1.07
VO - Output Voltage - V

IO = 10 mA
80

Efficiency - %
1.06 70
IO = 1 A

60

1.05

50

1.04 40
0 5 10 15 20 0 1 2 3 4 5
VI - Input Voltage - V IO - Output Current - A

Figure 5. 1.05-V Output Voltage vs Input Voltage Figure 6. Efficiency vs Output Current

100 900

90 VO = 3.3 V 850

VO = 2.5 V 800 VO = 3.3 V

fsw - Switching Frequency - kHz

80
VO = 5 V
VO = 2.5 V
70 VO = 1.8 V 750
Efficiency - %

60 700

50 650
VO = 1.05 V
600 VO = 1.2 V
40
VO = 1.5 V
30 550
VO = 1.8 V
20 500

10 450

0 400
0.001 0.01 0.1 0 5 10 15 20
IO - Output Current - A VI - Input Voltage - V
IO= 1 A

Figure 7. LIght Load Efficiency vs Output Current Figure 8. Switching Frequency vs Input Voltage
800 0.78

700
VO = 3.3 V
0.775
fsw - Switching Frequency - kHz

600
VFBTH - Vfb Voltage - V

0.77
500 VO = 1.8 V

400 VO = 1.05 V 0.765

300
0.76
200

0.755
100

0
0.75
0.01 0.1 1 10 -50 0 50 100 150
IO - Output Current - A TJ - Junction Temperature - °C
VI= 12 V

Figure 9. Switching Frequency vs Output Current Figure 10. VFB Voltage vs Junction Temperature

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Typical Characteristics (continued)

VIN = 12 V, TA = 25°C (unless otherwise noted).

Ambient Temperature

Figure 11. Maximum Power Dissipation

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8 Detailed Description

8.1 Overview
The TPS54528 is a 5-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs. It
operates using D-CAP2™ mode control. The fast transient response of D-CAP2™ control reduces the output
capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of low
ESR output capacitors including ceramic and special polymer types.

8.2 Functional Block Diagram

EN EN VIN
1
Logic
VIN
8

VREG5
VBST
Control Logic 7
Ref +

SS + PWM
1 shot
VFB SW VO
2 - 6

XCON
ON
VREG5
VREG5 Ceramic
3 Capacitor

SGND
SS SS 5
4 Softstart + SW GND
PGND ZC
- PGND

SGND
+ SW
OCP
- PGND

VIN

VREG5 UVLO Protection

TSD Logic
UVLO

REF Ref

8.3 Feature Description

8.3.1 Soft Start And Pre-Biased Soft Start
The soft start function is adjustable. When the EN terminal becomes high, 6μA current begins charging the
capacitor which is connected from the SS terminal to GND. Smooth control of the output voltage is maintained
during start up. The equation for the slow start time is shown in Equation 1. VFB voltage is 0.765 V and SS
terminal source current is 6μA.
C6(nF) ´ VFB ´ 1.1 C6(nF) ´ 0.765 ´ 1.1
t SS (ms) = =
ISS (μA) 6 (1)

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Feature Description (continued)

The TPS54528 contains a unique circuit to prevent current from being pulled from the output during startup if the
output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start
becomes greater than feedback voltage VFB), the controller slowly activates synchronous rectification by starting
the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-by-
cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This
scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (VO) starts and ramps
up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to normal
mode operation.

8.3.2 Current Protection

The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The
switch current is monitored by measuring the low-side FET switch voltage between the SW terminal and GND.
This voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature
compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
VOUT, the on-time and the output inductor value. During the on time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current Iout. The TPS54528 constantly
monitors the low-side FET switch voltage, which is proportional to the switch current, during the low-side on-time.
If the measured voltage is above the voltage proportional to the current limit, an internal counter is incremented
per each SW cycle and the converter maintains the low-side switch on until the measured voltage is below the
voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching
cycle begins. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in
the same manner. If the over current condition exists for 7 consecutive switching cycles, the internal OCL
threshold is set to a lower level, reducing the available output current. When a switching cycle occurs where the
switch current is not above the lower OCL threshold, the counter is reset and the OCL limit is returned to the
higher value.
There are some important considerations for this type of over-current protection. The peak current is the average
load current plus one half of the peak-to-peak inductor current. The valley current is the average load current
minus one half of the peak-to-peak inductor current. Since the valley current is used to detect the overcurrent
threshold, the load current is higher than the over-current threshold. Also, when the current is being limited, the
output voltage tends to fall as the demanded load current may be higher than the current available from the
converter. When the over current condition is removed, the output voltage will return to the regulated value. This
protection is non-latching.

8.3.3 UVLO Protection

Undervoltage lock out protection (UVLO) monitors the voltage of the VREG5 terminal. When the VREG5 voltage is
lower than UVLO threshold voltage, the TPS54528 is shut off. This protection is non-latching.

8.3.4 Thermal Shutdown

TPS54528 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 165°C),
the device is shut off. This is non-latch protection.

8.4 Device Functional Modes

8.4.1 PWM Operation
The main control loop of the TPS54528 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with
an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.

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Device Functional Modes (continued)

At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one
shot timer expires. This one shot is set by the converter input voltage, VIN, and the output voltage, VO, to
maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The
one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the
reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need
for ESR induced output ripple from D-CAP2™ mode control.

8.4.2 PWM Frequency And Adaptive On-Time Control

TPS54528 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The
TPS54528 runs with a pseudo-constant frequency of 700 kHz by using the input voltage and output voltage to
set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the
output voltage; therefore, when the duty ratio is VOUT/VIN, the frequency is constant.

8.4.3 Auto-Skip Eco-Mode™ Control

The TPS54528 is designed with Auto-Skip Eco-mode™ to increase light load efficiency. As the output current
decreases from heavy load condition, the inductor current is also reduced and eventually comes to point that its
rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when its zero inductor current is detected. As the load
current further decreases the converter run into discontinuous conduction mode. The on-time is kept almost the
same as is was in the continuous conduction mode so that it takes longer time to discharge the output capacitor
with smaller load current to the level of the reference voltage. The transition point to the light load operation
IOUT(LL) current can be calculated in Equation 2
1 (VIN - VOUT )×VOUT
I OUT ( LL ) = ×
2 × L × fsw VIN (2)

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9 Applications and Implementation

9.1 Application Information
The TPS54528 is designed to provide up to a 2-A output current from an input voltage source ranging from 4.5 V
to 18 V. The output voltage is configurable from 0.76 V to 6 V. A simplified design procedure for a 1.05-V output
is shown below .

9.2 Typical Application

U1
TPS54528DDA

Figure 12. 5-A Synchronous Step-Down (Buck) Converter

9.2.1 Design Requirements

Figure 12 shows the schematic of the design example.
To begin the design process, the user must know a few application parameters:
• Input voltage range
• Output voltage
• Output current
• Output voltage ripple
• Input voltage ripple

9.2.2 Detailed Design Procedure

[Link] Output Voltage Resistors Selection

The output voltage is set with a resistor divider from the output node to the VFB terminal. It is recommended to
use 1% tolerance or better divider resistors. Start by using Equation 3 to calculate VOUT.
To improve efficiency at light loads consider using larger value resistors, high resistance is more susceptible to
noise, and the voltage errors from the VFB input current are more noticeable.
æ R1÷ ö
V = 0.765 x çç1 + ÷
OUT çè R2 ÷ø (3)

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Typical Application (continued)

[Link] Output Filter Selection
The output filter used with the TPS54528 is an LC circuit. This LC filter has double pole at:
1
F =
P 2p L x COUT
OUT (4)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS54528. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls
off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero that
reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the
zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole
of Equation 4 is located below the high frequency zero but close enough that the phase boost provided be the
high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the
values recommended in Table 1.

Table 1. Recommended Component Values

Output Voltage (V) R1 (kΩ) R2 (kΩ) C4 (pF) (1) L1 (µH) C8 + C9 (µF)
1 6.81 22.1 1.0 - 1.5 22 - 68
1.05 8.25 22.1 1.0 - 1.5 22 - 68
1.2 12.7 22.1 1.0 - 1.5 22 - 68
1.5 21.5 22.1 1.5 22 - 68
1.8 30.1 22.1 5 - 22 1.5 22 - 68
2.5 49.9 22.1 5 - 22 2.2 22 - 68
3.3 73.2 22.1 5 - 22 2.2 22 - 68
5 124 22.1 5 - 22 3.3 22 - 68

(1) Optional

Since the DC gain is dependent on the output voltage, the required inductor value increases as the output
voltage increases. For higher output voltages at or above 1.8 V, additional phase boost can be achieved by
adding a feed forward capacitor (C4) in parallel with R1
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 5,
Equation 6 and Equation 7. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current. Use 700 kHz for
fSW.
Use 650 kHz for fSW. Make sure the chosen inductor is rated for the peak current of Equation 6 and the RMS
current of Equation 7.
V V - VOUT
I = OUT x IN(max)
IPP V L x f
IN(max) O SW (5)
I
lpp
I =I +
Ipeak O 2 (6)
2 1 2
I = I + I
Lo(RMS) O 12 IPP (7)
For this design example, the calculated peak current is 5.51 A and the calculated RMS current is 5.01 A. The
inductor used is a TDK SPM6530-1R5M100 with a peak current rating of 11.5 A and an RMS current rating of
11 A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS54528 is intended for use
with ceramic or other low ESR capacitors. Recommended values range from 22µF to 68µF. Use Equation 8 to
determine the required RMS current rating for the output capacitor.
VOUT x (VIN - VOUT )
I =
Co(RMS) 12 x VIN x LO x fSW
(8)

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For this design two TDK C3216X5R0J226M 22µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.29 A and each output capacitor is rated for 4A.

[Link] Input Capacitor Selection

The TPS54528 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A ceramic capacitor over 10 μF is recommended for the decoupling capacitor. An additional 0.1 µF
capacitor (C3) from terminal 8 to ground is optional to provide additional high frequency filtering. The capacitor
voltage rating needs to be greater than the maximum input voltage.

[Link] Bootstrap Capacitor Selection

A 0.1 µF. ceramic capacitor must be connected between the VBST to SW terminal for proper operation. It is
recommended to use a ceramic capacitor.

[Link] Vreg5 Capacitor Selection

A 1-µF. ceramic capacitor must be connected between the VREG5 to GND terminal for proper operation. It is
recommended to use a ceramic capacitor.

9.2.3 Application Performance Curves

Vout (50 mV/div) EN (10 V/div)

VREG5 (5 V/div)

Iout (2 A/div)

Vout (0.5 V/div)

t - Time - 1 ms/div
t - Time - 100 ms/div
VO = 1.05 V IO = 5 A

Figure 13. Load Transient Response Figure 14. Start-Up Wave Form

Vo (10 mV/div) VO = 50 mV / div (-950 mV dc offset)

SW = 10 V / div

SW (5 V/div)

t - Time - 400 ns/div Time = 1 µsec / div

VO = 1.05 V IO = 2 A IO = 30 mA

Figure 15. Voltage Ripple At Output Figure 16. DCM Voltage Ripple At Output

14 Copyright © 2011–2014, Texas Instruments Incorporated

Product Folder Links: TPS54528

 TPS54528
[Link] SLVSAY4C – JULY 2011 – REVISED MARCH 2014

VIN (50 mV/div)

SW (5 V/div)

t - Time - 400 ns/div

VO = 1.05 V IO = 2 A

Figure 17. Voltage Ripple At Input

10 Power Supply Recommendations

The input voltage range is from 4.5V to 18V. The input power supply and the input capacitors should be located
as close to the device as possible to minimize the impedance of the power-supply line.

11 Layout

11.1 Layout Guidelines

1. The TPS54528 can supply large load currents up to 5 A, so heat dissipation may be a concern. The top side
area adjacent to the TPS54528 should be filled with ground as much as possible to dissipate heat.
2. The bottom side area directly below the IC should a dedicated ground area. It should be directly connected
to the thermal pad of the device using vias as shown. The ground area should be as large as practical.
Additional internal layers can be dedicated as ground planes and connected to the vias as well.
3. Keep the input switching current loop as small as possible.
4. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the
feedback terminal of the device.
5. Keep analog and non-switching components away from switching components.
6. Make a single point connection from the signal ground to power ground.
7. Do not allow switching current to flow under the device.
8. Keep the pattern lines for VIN and PGND broad.
9. Exposed pad of device must be connected to PGND with solder.
10. VREG5 capacitor should be placed near the device, and connected PGND.
11. Output capacitor should be connected to a broad pattern of the PGND.
12. Voltage feedback loop should be as short as possible, and preferably with ground shield.
13. Lower resistor of the voltage divider which is connected to the VFB terminal should be tied to SGND.
14. Providing sufficient via is preferable for VIN, SW and PGND connection.
15. PCB pattern for VIN, SW, and PGND should be as broad as possible.
16. VIN Capacitor should be placed as near as possible to the device.

Copyright © 2011–2014, Texas Instruments Incorporated 15

Product Folder Links: TPS54528
TPS54528
SLVSAY4C – JULY 2011 – REVISED MARCH 2014 [Link]

11.2 Layout Example

VIN VIN
INPUT
BYPASS
CAPACITOR

VIN
HIGH FREQENCY
BYPASS
CAPACITOR

TO ENABLE EN VIN
CONTROL BOOST
FEEDBACK
RESISTORS VFB VBST CAPACITOR

VREG5 SW
BIAS SS GND
OUTPUT
INDUCTOR
VOUT
CAP
SLOW
START
CAP
EXPOSED
THERMAL PAD
Connection to
AREA OUTPUT
POWER GROUND FILTER
on internal or CAPACITOR
bottom layer

ANALOG
GROUND
TRACE POWER GROUND

VIA to Ground Plane

16 Copyright © 2011–2014, Texas Instruments Incorporated

Product Folder Links: TPS54528

 TPS54528
[Link] SLVSAY4C – JULY 2011 – REVISED MARCH 2014

11.3 Thermal Information

This 8-terminal DDA package incorporates an exposed thermal pad that is designed to be directly connected to
an external heatsink. The thermal pad must be soldered directly to the printed board (PCB). After soldering, the
PCB can be used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached
directly to the appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be
attached to a special heatsink structure designed into the PCB. This design optimizes the heat transfer from the
integrated circuit (IC).
For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating
abilities, see the Technical Brief, PowerPAD™ Thermally Enhanced Package, Texas Instruments Literature No.
SLMA002 and Application Brief, PowerPAD™ Made Easy, Texas Instruments Literature No. SLMA004.
The exposed thermal pad dimensions for this package are shown in the following illustration.

Figure 18. Thermal Pad Dimensions

Copyright © 2011–2014, Texas Instruments Incorporated 17

Product Folder Links: TPS54528
TPS54528
SLVSAY4C – JULY 2011 – REVISED MARCH 2014 [Link]

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation
D-CAP2TM Frequency Response Model, SLVA546
TPS54528EVM-052, 5-A, SWIFT™ Regulator Evaluation Module, SLVU480

12.2 Trademarks
D-CAP2, Eco-mode are trademarks of Texas Instruments.
Blu-ray Disc is a trademark of Blu-ray Disc Association.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

18 Copyright © 2011–2014, Texas Instruments Incorporated

Product Folder Links: TPS54528

 PACKAGE OPTION ADDENDUM

[Link] 10-Nov-2025

PACKAGING INFORMATION

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

TPS54528DDA Active Production SO PowerPAD 75 | BULK Yes NIPDAU | SN Level-2-260C-1 YEAR -40 to 85 54528
(DDA) | 8
TPS54528DDA.A Active Production SO PowerPAD 75 | BULK Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 54528
(DDA) | 8
TPS54528DDA.B Active Production SO PowerPAD 75 | BULK Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 54528
(DDA) | 8
TPS54528DDAG4 Active Production SO PowerPAD 75 | BULK Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 54528
(DDA) | 8
TPS54528DDAG4.A Active Production SO PowerPAD 75 | BULK Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 54528
(DDA) | 8
TPS54528DDAG4.B Active Production SO PowerPAD 75 | BULK Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 54528
(DDA) | 8
TPS54528DDAR Active Production SO PowerPAD 2500 | LARGE T&R Yes NIPDAU | SN Level-2-260C-1 YEAR -40 to 85 54528
(DDA) | 8
TPS54528DDAR.A Active Production SO PowerPAD 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 54528
(DDA) | 8
TPS54528DDAR.B Active Production SO PowerPAD 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 54528
(DDA) | 8

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

[Link] 10-Nov-2025

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

[Link] 23-May-2025

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS54528DDAR SO DDA 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1
PowerPAD

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

[Link] 23-May-2025

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS54528DDAR SO PowerPAD DDA 8 2500 366.0 364.0 50.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

[Link] 23-May-2025

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
TPS54528DDA DDA HSOIC 8 75 508 7.77 2540 NA
TPS54528DDA DDA HSOIC 8 75 517 7.87 635 4.25
TPS54528DDA.A DDA HSOIC 8 75 508 7.77 2540 NA
TPS54528DDA.A DDA HSOIC 8 75 517 7.87 635 4.25
TPS54528DDA.B DDA HSOIC 8 75 517 7.87 635 4.25
TPS54528DDA.B DDA HSOIC 8 75 508 7.77 2540 NA

Pack Materials-Page 3
 GENERIC PACKAGE VIEW
DDA 8 PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4202561/G
 PACKAGE OUTLINE
DDA0008B SCALE 2.400
PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

C
6.2
TYP SEATING PLANE
5.8
A
PIN 1 ID
AREA 0.1 C
6X 1.27
8
1

5.0 2X
4.8 3.81
NOTE 3

4X (0 -10 )
4
5
0.51
8X
4.0 0.31
B 1.7 MAX
3.8 0.25 C A B
NOTE 4

0.25
TYP
0.10

SEE DETAIL A

4 5
EXPOSED
THERMAL PAD

3.4 0.25
9 GAGE PLANE
2.8

0.15
0 -8 1.27 0.00
1 8
0.40
DETAIL A
2.71 TYPICAL
2.11

4214849/B 09/2025
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012.

[Link]
 EXAMPLE BOARD LAYOUT
DDA0008B PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

(2.95)
NOTE 9
(2.71) SOLDER MASK
DEFINED PAD
SOLDER MASK
OPENING
8X (1.55) SEE DETAILS

1
8

8X (0.6)

(3.4)
SYMM 9 SOLDER MASK
(1.3)
TYP OPENING

(4.9)
NOTE 9
6X (1.27)

4 5
(R0.05) TYP
SYMM METAL COVERED
( 0.2) TYP BY SOLDER MASK
VIA
(1.3) TYP
(5.4)

LAND PATTERN EXAMPLE

SCALE:10X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK METAL SOLDER MASK METAL UNDER

OPENING OPENING SOLDER MASK

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

PADS 1-8

4214849/B 09/2025

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 ([Link]/lit/slma002) and SLMA004 ([Link]/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

[Link]
 EXAMPLE STENCIL DESIGN
DDA0008B PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

(2.71)
BASED ON
0.125 THICK
STENCIL
8X (1.55) (R0.05) TYP
1
8

8X (0.6)

(3.4)
SYMM 9 BASED ON
0.125 THICK
STENCIL

6X (1.27)

5
4

METAL COVERED
SYMM SEE TABLE FOR
BY SOLDER MASK
DIFFERENT OPENINGS
FOR OTHER STENCIL
(5.4)
THICKNESSES

SOLDER PASTE EXAMPLE

EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 3.03 X 3.80
0.125 2.71 X 3.40 (SHOWN)
0.150 2.47 X 3.10
0.175 2.29 X 2.87

4214849/B 09/2025

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.

[Link]
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Last updated 10/2025