FAP201 - FPGA Programming

Part 1: FPGA Fundamentals and Architecture

1. What does FPGA stand for?
A. Field-Processed General ASIC
B. Fixed-Program Gate Architecture
C. Fast Parallel Graphic Array
D. Field-Programmable Gate Array
Answer: D

2. Which feature most clearly distinguishes an FPGA from an ASIC?

A. It contains no routing resources
B. It always runs at a higher clock frequency
C. It is reconfigurable after manufacturing
D. It cannot implement sequential logic
Answer: C

3. What is the main function of a configurable logic block (CLB) in an FPGA?

A. Implement logic functions and registers
B. Generate the power-supply voltage
C. Convert analog signals directly
D. Store the bitstream permanently in all devices
Answer: A

4. A lookup table (LUT) in an FPGA is primarily used to implement:

A. Combinational logic functions
B. Mechanical switching
C. Only clock generation
D. Only analog filtering
Answer: A

5. How many input combinations can a 4-input LUT represent?

A. 8
B. 4
C. 16
D. 32
Answer: C

6. Which FPGA resource is normally used to store state?

A. LUT input pin only
B. I/O resistor
C. Routing switch only
D. Flip-flop
Answer: D

7. What is the purpose of programmable interconnect in an FPGA?

A. Replace all flip-flops
B. Connect logic and other resources
C. Measure board temperature only
D. Convert HDL into C code

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 Answer: B

8. Which resource is best suited for large on-chip data storage?

A. Clock buffer
B. JTAG cable
C. Single LUT input
D. Block RAM
Answer: D

9. Which dedicated FPGA block is commonly used for fast multiplication and accumulation?
A. DSP slice
B. Configuration resistor
C. PLL reset pin
D. I/O bank
Answer: A

10. What does an FPGA bitstream contain?

A. Configuration data for logic, routing, and I/O
B. The operating-system kernel
C. Only testbench stimulus
D. Only source-code comments
Answer: A

11. Which memory technology commonly stores the configuration of an SRAM-based FPGA during
operation?
A. Mechanical relays
B. Optical disk
C. Magnetic tape
D. SRAM cells
Answer: D

12. What usually happens to an SRAM-based FPGA configuration when power is removed?
A. It is lost
B. It becomes an ASIC
C. It doubles in size
D. It is converted to VHDL
Answer: A

13. Which device is often used to load a bitstream into an FPGA at power-up?
A. UART terminal only
B. Audio codec only
C. Configuration flash memory
D. Heat sink
Answer: C

14. What is partial reconfiguration?

A. Reconfiguring part of an FPGA while other parts continue operating
B. Replacing the FPGA package manually
C. Using two clocks in a design
D. Changing only the source-code indentation
Answer: A

15. Which statement about FPGA parallelism is correct?

A. Only one LUT can be active at a time
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 B. Parallelism is impossible without an operating system
C. Independent hardware blocks can operate concurrently
D. All HDL statements always execute sequentially like software
Answer: C

16. What is an I/O bank in an FPGA?

A. A block containing only adders
B. A group of pins sharing electrical resources or standards
C. A software folder for HDL files
D. A set of testbench tasks
Answer: B

17. Which component distributes a clock signal with low skew across the FPGA?
A. UART receiver
B. Global clock network
C. General-purpose LED
D. Asynchronous reset gate only
Answer: B

18. What is the role of a PLL or MMCM in many FPGAs?

A. Implement only AND gates
B. Generate and condition clock signals
C. Program external flash without logic
D. Store user data permanently
Answer: B

19. What is logic density?

A. The voltage of a single I/O pin
B. The amount of programmable logic available in a device
C. The number of comments in HDL
D. The board weight per square centimeter
Answer: B

20. Which design is most appropriate for an FPGA?

A. A custom parallel digital data-processing pipeline
B. A purely mechanical gearbox
C. A paper-based algorithm with no hardware
D. A passive resistor divider only
Answer: A

21. Which FPGA resource commonly supports serializing high-speed I/O data?
A. Simple LUT only
B. Debounce switch
C. Seven-segment resistor
D. SERDES block
Answer: D

22. What is the primary advantage of hard IP blocks in an FPGA?

A. They are slower than LUT implementations by definition
B. They can never be used by HDL
C. Higher efficiency for common functions
D. They eliminate the need for clocks
Answer: C

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23. Which is an example of hard IP in many modern FPGAs?
A. Case statement
B. Source-code comment
C. Testbench delay
D. PCIe controller
Answer: D

24. What does device utilization report?

A. How many FPGA resources are used by the design
B. Only the number of syntax errors
C. Only the board temperature
D. The number of simulation timestamps
Answer: A

25. Why are FPGAs useful for prototyping digital systems?

A. They cannot implement processors
B. They require a new silicon fabrication run for every change
C. They have no debugging support
D. They can be reprogrammed quickly
Answer: D

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Part 2: Digital Logic, Number Systems, and Boolean Algebra
26. What is the binary representation of decimal 13?
A. 1001
B. 1110
C. 1101
D. 1011
Answer: C

27. What is the hexadecimal representation of binary 1111?

A. 10
B. E
C. A
D. F
Answer: D

28. What is the decimal value of unsigned binary 10110?

A. 20
B. 22
C. 18
D. 24
Answer: B

29. In 8-bit two's complement, what is the representation of -1?

A. 00000001
B. 10000000
C. 01111111
D. 11111111
Answer: D

30. What is the range of an unsigned 8-bit number?

A. 0 to 255
B. -128 to 127
C. 0 to 127
D. -255 to 255
Answer: A

31. What is the range of an 8-bit two's complement number?

A. -255 to 255
B. -128 to 127
C. 0 to 255
D. -127 to 128
Answer: B

32. Which Boolean expression represents an AND operation?

A. A ⊕ B
B. A + B
C. ¬A
D. A · B
Answer: D

33. Which gate outputs 1 only when its inputs are different?
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 A. AND
B. NOR
C. XNOR
D. XOR
Answer: D

34. Which gate outputs 1 only when all inputs are 0?

A. XOR
B. OR
C. NOR
D. AND
Answer: C

35. According to De Morgan's law, NOT(A AND B) equals:

A. (NOT A) AND (NOT B)
B. (NOT A) OR (NOT B)
C. A OR B
D. A XOR B
Answer: B

36. What is the result of binary addition 1011 + 0101?

A. 10100
B. 1110
C. 1101
D. 10000
Answer: D

37. What is the least significant bit (LSB) of binary 10110?

A. 10
B. 0
C. 6
D. 1
Answer: B

38. How many distinct values can a 10-bit unsigned signal represent?
A. 1000
B. 1024
C. 512
D. 2048
Answer: B

39. What is sign extension?

A. Replicating the sign bit when increasing signed width
B. Removing the most significant bit
C. Converting binary to decimal text
D. Appending zeros to the left of every number
Answer: A

40. What is zero extension?

A. Adding zeros to the least significant side only
B. Adding zeros to the most significant side
C. Inverting every bit
D. Repeating the sign bit
Answer: B
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41. Which circuit selects one of several inputs based on select signals?
A. Oscillator
B. Counter
C. Multiplexer
D. Decoder
Answer: C

42. Which circuit activates one output corresponding to a binary input code?
A. Multiplexer
B. Register
C. Adder
D. Decoder
Answer: D

43. What does a priority encoder do?

A. Outputs the code of the highest-priority active input
B. Generates a clock
C. Stores every active input
D. Adds all active input values
Answer: A

44. Which circuit performs binary addition?

A. Adder
B. Decoder
C. Latch
D. Comparator
Answer: A

45. What is overflow in signed arithmetic?

A. The carry input is always zero
B. The operands have different widths only
C. The true result is outside the representable range
D. The result equals zero
Answer: C

46. For unsigned addition, which signal commonly indicates overflow beyond the MSB?
A. Parity bit
B. Clock enable
C. Reset
D. Carry-out
Answer: D

47. What does a magnitude comparator determine?

A. Whether one binary number is less than, equal to, or greater than another
B. The number of LUTs used
C. The routing delay only
D. The clock frequency only
Answer: A

48. Which representation is commonly used for signed integers in digital hardware?
A. Two's complement
B. BCD only
C. ASCII
D. Gray code only
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 Answer: A

49. What is a key property of Gray code?

A. It uses only two code words
B. Every value has even parity
C. Adjacent values differ by one bit
D. It cannot represent zero
Answer: C

50. Why is Gray code useful in asynchronous pointer transfer?

A. It requires no synchronizers
B. It eliminates all metastability
C. It doubles memory capacity
D. It reduces the chance of multiple bits changing simultaneously
Answer: D

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Part 3: Verilog Fundamentals
51. Which keyword begins a Verilog module definition?
A. entity
B. architecture
C. module
D. package
Answer: C

52. Which keyword ends a Verilog module definition?

A. finishmodule
B. endmodule
C. endarchitecture
D. end
Answer: B

53. Which Verilog data type is commonly used for a continuously driven net?
A. event
B. integer only
C. wire
D. real
Answer: C

54. Which Verilog data type is traditionally used for a signal assigned inside an always block?
A. wire
B. parameter
C. reg
D. supply0
Answer: C

55. Which statement creates a continuous assignment?

A. repeat
B. assign
C. always
D. initial
Answer: B

56. Which operator represents bitwise AND in Verilog?

A. &&
B. |
C. &
D. ^~
Answer: C

57. Which operator represents logical AND in Verilog?

A. ~&
B. &&
C. &
D. ||
Answer: B

58. Which operator represents equality comparison in Verilog?

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 A. =
B. =~
C. ==
D. <=
Answer: C

59. Which operator represents nonblocking assignment?

A. <=
B. =>
C. <-
D. =
Answer: A

60. Which operator represents blocking assignment?

A. :=
B. =
C. ==
D. <=
Answer: B

61. What does 8'hA5 mean in Verilog?

A. An 8-bit hexadecimal value A5
B. An 8-bit binary value 5
C. A 5-bit decimal value 8
D. A time delay of A5
Answer: A

62. What does 4'b1010 represent?

A. A 4-bit binary literal
B. A module instance
C. A decimal value with width 1010
D. A four-byte string
Answer: A

63. How is a single-line comment written in Verilog?

A. -- comment
B. /* only
C. # comment
D. // comment
Answer: D

64. How is a block comment written in Verilog?

A. // comment //
B. -- comment --
C. /* comment */
D. (* comment *)
Answer: C

65. What is the purpose of a parameter in Verilog?

A. Generate an analog voltage
B. Define a compile-time constant for configurable hardware
C. Create a runtime software variable
D. Replace the clock signal
Answer: B
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66. Which syntax declares an 8-bit vector named data?
A. vector data(8);
B. wire data [7];
C. wire [8:1] only_data;
D. wire [7:0] data;
Answer: D

67. What is selected by data[3]?

A. Bits 3 through 0
B. The fourth module instance
C. A 3-bit delay
D. Bit 3 of data
Answer: D

68. What is selected by data[7:4]?

A. Eight bits starting at 4
B. A decimal range
C. Bits 7 down to 4
D. Only bits 7 and 4
Answer: C

69. Which operator concatenates signals in Verilog?

A. < >
B. ( )
C. { }
D. [ ]
Answer: C

70. What does {4{1'b1}} produce?

A. 8'b11110000
B. 1'b1
C. 4'b1111
D. 4'b0001
Answer: C

71. Which construct conditionally chooses between two expressions in one line?
A. fork
B. case only
C. repeat
D. ?:
Answer: D

72. Which system task prints formatted text during simulation?

A. $synthesize
B. $compile
C. $display
D. $route
Answer: C

73. Which system task commonly terminates a simulation?

A. $finish
B. $exitmodule
C. $stopclock
D. $end
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 Answer: A

74. What is the purpose of `timescale in Verilog?

A. Define simulation time unit and precision
B. Set the FPGA clock frequency physically
C. Select the target device
D. Choose I/O voltage
Answer: A

75. Which construct is generally not synthesizable for real hardware delays?
A. #10 delay in RTL logic
B. A combinational assign statement
C. A flip-flop always block
D. A case statement
Answer: A

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Part 4: Combinational RTL Design
76. Which sensitivity list is preferred for combinational logic in Verilog-2001?
A. initial begin
B. always @*
C. always @(posedge clk)
D. always @(negedge reset)
Answer: B

77. What must be true for a combinational always block to avoid unintended latches?
A. It must include a reset
B. It must contain a clock edge
C. It must use only nonblocking assignments
D. Every output is assigned for every possible input condition
Answer: D

78. Which assignment type is normally recommended inside a combinational always block?
A. Force assignment
B. Blocking assignment
C. Continuous delay assignment
D. Nonblocking assignment only
Answer: B

79. What hardware is inferred by y = sel ? a : b?

A. Counter
B. 2-to-1 multiplexer
C. D flip-flop
D. Clock divider
Answer: B

80. What hardware is inferred by y = a & b?

A. Register
B. AND gate
C. OR gate
D. XOR gate
Answer: B

81. A 4-to-1 multiplexer requires how many select bits?

A. 3
B. 2
C. 1
D. 4
Answer: B

82. A 3-to-8 decoder has how many output lines?

A. 6
B. 8
C. 24
D. 3
Answer: B

83. Which Verilog construct is appropriate for describing a multiplexer with many choices?
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 A. forever loop only
B. case statement
C. initial delay
D. posedge block
Answer: B

84. Why is a default branch useful in a combinational case statement?

A. It creates a clock
B. It forces a DSP block
C. It covers unspecified choices and helps prevent latches
D. It makes simulation run forever
Answer: C

85. What does a combinational loop mean?

A. A clock-enable chain
B. A feedback path with no storage element
C. A registered feedback path
D. A loop that repeats in a testbench only
Answer: B

86. Why are unintended combinational loops undesirable?

A. They remove routing delay
B. They may oscillate or fail timing analysis
C. They always improve performance
D. They automatically create RAM
Answer: B

87. Which operator performs a reduction AND of all bits in vector x?

A. x & y
B. &&x
C. ~&x only
D. &x
Answer: D

88. Which operator performs a reduction OR of all bits in vector x?

A. x | y only
B. |x
C. !x
D. x || y
Answer: B

89. What does ^x compute when x is a vector?

A. Logical NOT
B. Arithmetic power
C. Reduction XOR or parity
D. Left shift
Answer: C

90. What is the main purpose of a barrel shifter?

A. Debounce a switch
B. Store data across clock cycles
C. Shift by a variable number of positions in combinational logic
D. Generate an asynchronous reset
Answer: C
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91. Which operation can implement multiplication by 8 for an unsigned value?
A. Left shift by 3
B. Rotate right by 8
C. XOR with 8
D. Right shift by 3
Answer: A

92. Which operation can implement unsigned division by 4 when truncation is acceptable?
A. Right shift by 2
B. Left shift by 2
C. XOR with 2
D. AND with 4
Answer: A

93. What does a one-hot decoder output look like for a valid input?
A. Exactly two output bits are high
B. All output bits toggle
C. All output bits are high
D. Exactly one output bit is high
Answer: D

94. Which circuit computes y=1 when a equals b?

A. Counter
B. Equality comparator
C. Latch
D. Priority encoder
Answer: B

95. What is the output width of adding two unsigned N-bit numbers if carry is preserved?
A. N+1 bits
B. N bits always
C. N-1 bits
D. 2N bits
Answer: A

96. What is the minimum output width of multiplying two unsigned N-bit numbers without
truncation?
A. N bits
B. N+1 bits
C. N-1 bits
D. 2N bits
Answer: D

97. What is constant propagation during synthesis?

A. Routing clocks through LUTs
B. Changing constants during simulation randomly
C. Converting registers into comments
D. Simplifying logic based on known constant values
Answer: D

98. What is dead-code elimination in synthesis?

A. Removing every case statement
B. Removing logic that cannot affect observable outputs
C. Deleting all reset logic
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 D. Replacing RAM with registers
Answer: B

99. Which coding problem often causes an unintended latch?

A. Using a complete default assignment
B. Using assign for simple logic
C. Missing assignment in one branch of combinational logic
D. Declaring a wire
Answer: C

100. What should a purely combinational module normally omit?

A. Input ports
B. Output ports
C. Boolean operations
D. Clock-dependent state storage
Answer: D

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Part 5: Sequential Logic and Registers
101. Which event expression describes a rising-edge-triggered clock?
A. posedge clk
B. always @*
C. negedge clk
D. clk == 1 in assign
Answer: A

102. Which assignment type is recommended in clocked always blocks?

A. Continuous assignment
B. Blocking assignment only
C. Force assignment
D. Nonblocking assignment
Answer: D

103. What hardware is inferred by q <= d inside always @(posedge clk)?

A. Multiplexer only
B. D flip-flop
C. Combinational decoder
D. Tri-state buffer only
Answer: B

104. What is a register?

A. A group of flip-flops storing multiple bits
B. A clock generator
C. A combinational AND gate
D. A simulation-only task
Answer: A

105. What does a clock enable do?

A. Removes the clock network
B. Creates an asynchronous output
C. Changes the I/O voltage
D. Controls whether a register loads new data on a clock edge
Answer: D

106. Which code behavior represents a synchronous reset?

A. Reset appears in the sensitivity list and acts immediately
B. Reset is implemented only in the testbench
C. Reset is a constant parameter
D. Reset is checked inside a clock-edge block and takes effect on the clock edge
Answer: D

107. Which code behavior represents an asynchronous reset?

A. Reset is not connected to a register
B. Reset changes only synthesis options
C. Reset is included in the sensitivity list with the clock edge
D. Reset is checked only after a clock edge
Answer: C

108. What is the difference between a latch and a flip-flop?

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 A. A flip-flop is always combinational
B. They are identical in all respects
C. A latch is level-sensitive; a flip-flop is edge-triggered
D. A latch stores no data
Answer: C

109. What does a binary counter do?

A. Selects one input without memory
B. Routes configuration bits
C. Generates analog sine waves
D. Increments or decrements a stored binary value on clock events
Answer: D

110. What is a modulo-16 counter width?

A. 8 bits
B. 16 bits
C. 4 bits
D. 5 bits
Answer: C

111. What happens when a 4-bit unsigned counter increments from 1111?
A. It stays at 1111 automatically
B. It becomes 10000 in the same 4 bits
C. It resets the FPGA configuration
D. It wraps to 0000 if overflow is discarded
Answer: D

112. What is a shift register?

A. A clock oscillator
B. A chain of registers that moves data each clock
C. A combinational multiplier
D. A decoder with no storage
Answer: B

113. What is serial-in parallel-out operation?

A. Parallel data enters and one bit is selected combinationally
B. No clock is required
C. All bits enter and leave in parallel
D. Bits enter serially and are observed together on parallel outputs
Answer: D

114. What is a ring counter?

A. A shift register with a circulating one-hot pattern
B. A PLL output
C. A binary adder
D. An asynchronous FIFO
Answer: A

115. What is a Johnson counter?

A. A counter with no feedback
B. A multiplier counter
C. A memory decoder
D. A twisted-ring counter using inverted feedback
Answer: D
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116. Why should combinational logic usually be kept outside the clock path?
A. To avoid creating gated or distorted clocks
B. To remove all registers
C. To force asynchronous behavior
D. To increase clock skew
Answer: A

117. What is clock gating?

A. Converting a clock into a reset
B. Increasing the input voltage
C. Controlling clock delivery to logic to reduce switching
D. Using a data mux as a UART
Answer: C

118. Why is using a dedicated clock enable often safer than fabric-gated clocks in FPGAs?
A. It removes setup-time requirements
B. It guarantees zero skew everywhere
C. It uses supported clocking resources and avoids glitches
D. It eliminates all dynamic power
Answer: C

119. What is a pipeline register used for?

A. Replace all input pins
B. Split a long combinational path into shorter stages
C. Store the FPGA bitstream permanently
D. Create an analog filter
Answer: B

120. What is latency in a pipelined design?

A. The number of I/O standards
B. The time or number of cycles from input to corresponding output
C. The bitstream file size
D. The number of LUT inputs
Answer: B

121. What is throughput?

A. The amount of source-code indentation
B. The rate at which results can be produced
C. The number of reset signals
D. The maximum stored value only
Answer: B

122. A fully pipelined design may have high throughput because it can:
A. Run without a clock
B. Accept new input data every clock cycle
C. Produce only one result after reset
D. Avoid all registers
Answer: B

123. What is a loadable counter?

A. A combinational priority encoder
B. A counter stored in flash only
C. A clock without phase
D. A counter that can accept an external value into its register
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 Answer: D

124. What is a prescaler?

A. A counter or divider used to derive a slower enable or clock rate
B. A LUT configured as RAM only
C. A module that increases data width only
D. An analog amplifier
Answer: A

125. Why is a power-on reset often needed?

A. To increase LUT size
B. To remove timing constraints
C. To place state elements into known states
D. To convert Verilog to VHDL
Answer: C

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Part 6: Finite State Machines
126. What does FSM stand for?
A. Fast Synthesis Method
B. Fixed Signal Memory
C. Finite State Machine
D. Field Switching Matrix
Answer: C

127. What are the main components of an FSM?

A. Only an adder and a multiplier
B. Only input and output pins
C. Only a testbench and waveform
D. State register, next-state logic, and output logic
Answer: D

128. In a Moore machine, outputs depend on:

A. Current inputs only
B. Next clock frequency only
C. Current state only
D. Routing delay only
Answer: C

129. In a Mealy machine, outputs depend on:

A. Reset only
B. Current state and current inputs
C. Configuration memory only
D. Current state only
Answer: B

130. Which FSM type may respond to input changes without waiting for a state change?
A. Moore machine only
B. Mealy machine
C. ROM machine
D. Ring counter only
Answer: B

131. What is state encoding?

A. Encoding the testbench clock
B. Selecting I/O voltage levels
C. Compressing the bitstream file
D. Assigning binary patterns to symbolic states
Answer: D

132. What is one-hot state encoding?

A. No flip-flops are used
B. All states use the same code
C. Each state uses a separate bit with one active bit
D. Each transition changes every bit
Answer: C

133. What is a possible advantage of one-hot encoding in an FPGA?

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 A. No need for a clock
B. Simple and potentially fast decode logic
C. Minimum number of flip-flops in all cases
D. Automatic metastability elimination
Answer: B

134. What is binary state encoding?

A. Using one bit per transition
B. Using analog voltage levels
C. Using the minimum or near-minimum number of bits to represent states
D. Using ASCII names in hardware
Answer: C

135. How many bits are minimally required to encode 8 states in binary?
A. 4
B. 3
C. 8
D. 2
Answer: B

136. What is an illegal state?

A. A state with a self-loop
B. The reset state
C. A state-code pattern not assigned to a valid state
D. A state that has an output
Answer: C

137. Why should an FSM include recovery from illegal states?

A. To increase the clock period
B. To return the design to a known valid state
C. To remove the state register
D. To disable synthesis
Answer: B

138. Which statement is best for describing next-state selection?

A. A combinational case statement
B. A JTAG command
C. A simulation delay only
D. A continuous clock assignment
Answer: A

139. Where is the current state normally updated?

A. In a clocked always block
B. In an assign statement with no clock
C. Inside a parameter declaration
D. Only in the testbench
Answer: A

140. What is the reset state?

A. The state used only during synthesis
B. The state entered when reset is asserted
C. The state with the largest binary code
D. A state that cannot transition
Answer: B
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141. What is a state transition?
A. A change from Verilog to C
B. A change from one state to another under defined conditions
C. A change in I/O voltage standard
D. A change in bitstream file extension
Answer: B

142. What is a self-loop in an FSM?

A. A reset that never ends
B. A duplicated output pin
C. A transition from a state back to itself
D. A combinational loop in the clock tree
Answer: C

143. What is a state diagram used for?

A. Visualize states and transitions
B. Specify PCB trace impedance only
C. Show only timing constraints
D. Store synthesis logs
Answer: A

144. What is a state transition table?

A. A table of FPGA prices
B. A table mapping current state and inputs to next state and outputs
C. A list of pin voltages only
D. A waveform screenshot
Answer: B

145. What coding practice helps prevent latches in FSM next-state logic?
A. Assign a default next state before conditional changes
B. Use delays in every branch
C. Omit assignments in unused branches
D. Use a clock inside the case statement
Answer: A

146. What does state <= next_state represent?

A. Updating the state register on a clock edge
B. Combinational output decoding only
C. A testbench assertion
D. A bitstream download command
Answer: A

147. Which FSM implementation usually separates sequential and combinational logic into two
blocks?
A. No-state style
B. Single-wire style
C. Analog style
D. Two-process style
Answer: D

148. What is output decoding in a Moore FSM?

A. Calculating setup time
B. Generating outputs from the current state
C. Sampling an asynchronous clock
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 D. Loading configuration flash
Answer: B

149. What potential issue can Mealy outputs have if inputs glitch?
A. State memory is lost immediately
B. Outputs may glitch because they depend combinationally on inputs
C. The FPGA cannot be programmed
D. All outputs become high impedance permanently
Answer: B

150. How can registered outputs improve an FSM interface?

A. They eliminate every cycle of latency
B. They make outputs change only on clock edges
C. They require no flip-flops
D. They make timing constraints unnecessary
Answer: B

Page 24
Part 7: Timing and Clocking
151. What is setup time?
A. Minimum time data must be stable before the active clock edge
B. Clock period divided by two only
C. Reset pulse width only
D. Minimum time data must be stable after the edge
Answer: A

152. What is hold time?

A. Time between two resets
B. Minimum time data must remain stable after the active clock edge
C. Time needed to configure the FPGA
D. Minimum time data must be stable before the edge
Answer: B

153. What is clock-to-Q delay?

A. Reset assertion time only
B. Delay from input pin to power rail
C. Bitstream download time
D. Delay from a clock edge to a flip-flop output change
Answer: D

154. What is a critical path?

A. The shortest routing path
B. A testbench file path
C. A path used only by reset
D. The longest timing path that limits maximum clock frequency
Answer: D

155. What does timing closure mean?

A. Closing the FPGA tool
B. Meeting all specified timing constraints
C. Removing every clock
D. Finishing source-code comments
Answer: B

156. What is clock skew?

A. A synthesis warning about comments
B. Difference in clock arrival times at different registers
C. Difference between two data values
D. A change in bit width
Answer: B

157. What is clock jitter?

A. A routing constraint
B. A fixed propagation delay only
C. A memory initialization file
D. Variation of clock-edge timing over time
Answer: D

158. What is the clock period for a 100 MHz clock?

Page 25
 A. 1 ns
B. 100 ns
C. 10 ns
D. 0.1 ns
Answer: C

159. What is the frequency of a clock with a 20 ns period?

A. 50 MHz
B. 100 MHz
C. 20 MHz
D. 5 MHz
Answer: A

160. Which change usually improves maximum clock frequency?

A. Increasing logic depth
B. Using unconstrained paths
C. Removing all registers
D. Adding pipeline stages to shorten combinational paths
Answer: D

161. What is slack in timing analysis?

A. Clock frequency plus voltage
B. Number of LUTs remaining
C. Bitstream size difference
D. Required time minus arrival time
Answer: D

162. What does positive setup slack indicate?

A. The path meets the setup requirement
B. The path violates setup time
C. The clock is missing
D. The register has no input
Answer: A

163. What does negative slack indicate?

A. Unused logic
B. A timing violation
C. A correct asynchronous path
D. A successful bitstream load
Answer: B

164. What is a false path constraint?

A. A path with incorrect source code only
B. A path that has no logic physically
C. A path that must always be the critical path
D. A declaration that a path is not required to meet normal timing analysis
Answer: D

165. What is a multicycle path constraint?

A. A path that changes every cycle
B. A path with multiple clocks but no data
C. A path allowed more than one clock cycle to propagate
D. A path used only during simulation
Answer: C
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166. Why must timing exceptions be used carefully?
A. Incorrect exceptions can hide real timing failures
B. They remove the need for clocks
C. They always reduce FPGA area to zero
D. They automatically fix metastability
Answer: A

167. What is a generated clock?

A. A simulation variable only
B. A clock derived from another clock by logic or clocking resources
C. An asynchronous input with no period
D. A clock typed manually in comments
Answer: B

168. Why should clocks use dedicated clock-routing resources?

A. To prevent synthesis
B. To achieve low skew and predictable timing
C. To increase glitches
D. To consume more LUTs
Answer: B

169. What is duty cycle?

A. The number of clocks in a design
B. The delay through a LUT
C. The percentage of used flip-flops
D. The fraction of a clock period the signal is high
Answer: D

170. A 50% duty-cycle clock is high for:

A. Half of each period
B. One quarter of each period
C. No part of the period
D. The entire period
Answer: A

171. What is a timing constraint file used for?

A. Store source-code comments
B. Write testbench stimulus only
C. Generate analog waveforms
D. Specify clocks, I/O delays, and timing exceptions
Answer: D

172. What is input delay in static timing analysis?

A. External delay relative to a clock before data reaches an FPGA input
B. Reset recovery time only
C. Delay from FPGA output to an internal register only
D. Bitstream loading delay
Answer: A

173. What is output delay in static timing analysis?

A. Simulation compilation time
B. Delay from a LUT to itself
C. Timing requirement from an FPGA output to an external receiving device
D. Clock distribution delay only
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 Answer: C

174. What does Fmax mean?

A. Maximum number of resets
B. Maximum number of files in a project
C. Maximum input voltage
D. Maximum clock frequency at which timing requirements are met
Answer: D

175. Which report identifies the longest failing paths?

A. Pin-planning report only
B. Source-code formatter report
C. Timing report
D. Power-on self-test only
Answer: C

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Part 8: Clock Domain Crossing, Reset, and Metastability
176. What is metastability?
A. A stable high-impedance output
B. An uncertain temporary state in a flip-flop caused by timing violation
C. A permanent FPGA configuration mode
D. A type of block RAM
Answer: B

177. When is metastability most likely?

A. When reset is never connected
B. When only combinational logic is used
C. When data is constant for many cycles
D. When asynchronous data changes near a sampling clock edge
Answer: D

178. What is the common way to synchronize a single-bit asynchronous signal?

A. A two-flip-flop synchronizer
B. A block RAM
C. A large multiplexer
D. A combinational XOR gate
Answer: A

179. Why are two flip-flops used in a synchronizer?

A. To double the input frequency
B. To eliminate all latency
C. To give metastability more time to resolve before use
D. To create an asynchronous reset
Answer: C

180. Does a two-flip-flop synchronizer guarantee zero probability of failure?

A. No, it greatly reduces but does not eliminate the probability
B. Yes, always
C. Only if no clock is used
D. Only for multi-bit buses
Answer: A

181. What does CDC stand for?

A. Central Design Compiler
B. Clock Domain Crossing
C. Clock Data Counter
D. Configurable Delay Cell
Answer: B

182. Why is directly sampling a multi-bit asynchronous bus unsafe?

A. It cannot be simulated
B. It always creates a latch
C. Different bits may be captured in different cycles
D. It uses too few LUTs
Answer: C

183. Which structure is commonly used to transfer data streams between unrelated clock domains?
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 A. Clock divider only
B. Single inverter
C. Asynchronous FIFO
D. Simple combinational wire
Answer: C

184. What are Gray-coded pointers used for in an asynchronous FIFO?

A. Replacing RAM
B. Safer pointer synchronization across clock domains
C. Increasing data width
D. Generating analog levels
Answer: B

185. What is a handshake protocol used for in CDC?

A. Assign package pins
B. Generate a bitstream
C. Measure FPGA temperature
D. Coordinate reliable transfer of data or events between domains
Answer: D

186. What is pulse synchronization?

A. Converting parallel data to analog
B. Transferring a one-cycle event from one clock domain to another
C. Holding reset forever
D. Dividing a clock by two only
Answer: B

187. Why can a narrow pulse be missed when crossing into a slower clock domain?
A. The pulse automatically stretches
B. It always becomes metastable forever
C. It may not overlap any sampling edge
D. The slower domain has no registers
Answer: C

188. Which technique can transfer a narrow event reliably across domains?
A. Toggle synchronizer or handshake
B. Direct combinational connection
C. Removing the destination clock
D. Clock gating with data
Answer: A

189. What is asynchronous reset assertion?

A. Reset can become active only on a clock edge
B. Reset can become active without waiting for a clock edge
C. Reset is not connected to flip-flops
D. Reset is generated by the testbench only
Answer: B

190. Why is reset deassertion often synchronized?

A. To eliminate the clock
B. To increase reset voltage
C. To avoid recovery/removal violations and inconsistent release
D. To configure block RAM
Answer: C
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191. What is reset recovery time?
A. Time between two testbench tasks
B. Time to reload the bitstream
C. Time data must remain after a clock edge
D. Time reset must be inactive before a clock edge
Answer: D

192. What is reset removal time?

A. Time needed to remove a module
B. Time to erase flash
C. Minimum time reset must remain stable after a clock edge during deassertion
D. Time for a LUT output to toggle
Answer: C

193. What is a clock domain?

A. Only external input pins
B. All logic in the FPGA package
C. Only combinational paths
D. Logic driven by the same clock or synchronously related clocks
Answer: D

194. Which signal usually needs synchronization when entering a clock domain?
A. A compile-time parameter
B. A constant tied to zero
C. A signal already registered by the same clock
D. An asynchronous external push button
Answer: D

195. What is MTBF in metastability analysis?

A. Maximum Toggle Bit Frequency
B. Memory Transfer Bus Format
C. Mean Time Between Failures
D. Minimum Timing Buffer Factor
Answer: C

196. How can synchronizer MTBF generally be improved?

A. Remove all flip-flops
B. Allow more settling time or use additional stages
C. Reduce clock period without other changes
D. Increase asynchronous toggle rate
Answer: B

197. What is the main purpose of a CDC analysis tool?

A. Choose Verilog indentation
B. Generate PCB artwork only
C. Identify unsafe crossings and synchronization structures
D. Measure analog current directly
Answer: C

198. Why should synchronized control signals not be used to transfer an unrelated multi-bit data bus
directly?
A. The bus may not be coherent when sampled
B. Synthesis cannot compile buses
C. The control signal uses too much RAM
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 D. The bus becomes analog
Answer: A

199. What does data coherency mean in CDC?

A. The data has no clock
B. The data width equals the address width
C. All bits of a transferred word correspond to the same logical sample
D. Every bit is always one
Answer: C

200. Which CDC method is appropriate for occasional multi-bit words?

A. Direct wiring
B. Independent two-flop synchronizer on every bit without protocol
C. A combinational feedback loop
D. Handshake with stable data capture
Answer: D

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Part 9: Synthesis, Implementation, and Constraints
201. What does synthesis do?
A. Translate RTL into a logical netlist
B. Run only the testbench
C. Create an analog PCB model
D. Physically solder the FPGA
Answer: A

202. What does technology mapping do?

A. Map generic logic into FPGA-specific resources
B. Select a text editor
C. Convert binary to decimal
D. Assign testbench delays
Answer: A

203. What does placement do?

A. Connect the FPGA to a USB cable
B. Write HDL comments
C. Assign logical cells to physical FPGA locations
D. Create clock waveforms only
Answer: C

204. What does routing do?

A. Compile C source only
B. Initialize simulation variables
C. Connect placed resources using programmable interconnect
D. Choose module names
Answer: C

205. What is implementation in an FPGA flow?

A. The process including mapping, placement, routing, and timing analysis
B. Only selecting a board color
C. Only writing a testbench
D. Only creating a module header
Answer: A

206. What is a netlist?

A. A list of internet addresses
B. A waveform file only
C. A list of comments
D. A representation of components and their connections
Answer: D

207. What is RTL?

A. Routing Timing List
B. Real-Time Language
C. Register-Transfer Level
D. Random Test Logic
Answer: C

208. What does synthesizable HDL mean?

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 A. HDL used only for documentation
B. HDL containing unlimited delays
C. HDL constructs that tools can implement as hardware
D. HDL that runs only on a CPU
Answer: C

209. Which construct is usually simulation-only?

A. An initial block that generates a forever clock in a testbench
B. A clocked register block
C. A continuous assignment
D. A combinational case statement
Answer: A

210. What is elaboration?

A. Measuring clock jitter physically
B. Programming configuration flash only
C. Routing the PCB
D. Resolving parameters, hierarchy, and generated structures before synthesis or simulation
Answer: D

211. What is hierarchy in an HDL design?

A. Modules instantiated inside other modules
B. The ranking of clock frequencies
C. The sequence of test vectors
D. The order of signal bits only
Answer: A

212. What is module instantiation?

A. Starting a simulator
B. Creating an instance of a module within another module
C. Assigning a package pin
D. Declaring a comment
Answer: B

213. Why use parameters in reusable modules?

A. Make signals analog
B. Allow widths and behaviors to be configured
C. Prevent all optimization
D. Remove the need for ports
Answer: B

214. What is a generate block used for?

A. Generate analog noise
B. Conditionally or repeatedly create hardware at elaboration
C. Generate a clock with no logic
D. Generate runtime software threads
Answer: B

215. What does a synthesis warning about an unused signal usually mean?
A. The FPGA is damaged
B. The bitstream is encrypted
C. The clock is too fast by definition
D. The signal does not affect implemented outputs or state
Answer: D
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216. What is resource sharing?
A. Duplicating every operator
B. Removing all multiplexers
C. Using only external memory
D. Using one hardware operator for multiple operations at different times
Answer: D

217. What is logic replication?

A. Using one LUT for all outputs
B. Copying source files for backup only
C. Duplicating logic to improve fanout or timing
D. Replicating testbench delays
Answer: C

218. What is fanout?

A. The width of an adder
B. The number of states in an FSM
C. The number of clocks generated
D. The number of loads driven by a signal
Answer: D

219. Why can high fanout cause timing problems?

A. It removes clock skew
B. It creates more block RAM
C. It increases routing load and delay
D. It always reduces power to zero
Answer: C

220. What is a pin constraint?

A. A simulation stop condition
B. A limit on source-code lines
C. A RAM initialization value
D. A mapping between a logical port and a physical FPGA pin
Answer: D

221. Why must the correct I/O standard be assigned?

A. To match electrical voltage and signaling requirements
B. To choose the Verilog language version only
C. To eliminate the need for a board clock
D. To improve indentation
Answer: A

222. What is a design rule check (DRC)?

A. A method for arithmetic rounding
B. A test of software licensing only
C. A waveform display format
D. A check for structural and implementation rule violations
Answer: D

223. What is an unconstrained path?

A. A path used only by comments
B. A path that cannot toggle
C. A path with no physical routing
D. A timing path not covered by sufficient timing constraints
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 Answer: D

224. Why is an unconstrained design dangerous?

A. It always uses too many LEDs
B. It cannot contain registers
C. Timing may not be analyzed against the real requirements
D. It automatically fails synthesis
Answer: C

225. What file is produced after successful FPGA implementation for device programming?
A. Bitstream file
B. Testbench source only
C. Schematic PDF only
D. Waveform image only
Answer: A

Page 36
Part 10: Memory and Storage
226. What is synchronous RAM?
A. Memory whose read or write operations are controlled by a clock
B. Memory with no address input
C. Memory that cannot be written
D. Memory used only outside the FPGA
Answer: A

227. What is ROM?

A. Read-only memory
B. Random output module
C. Register operation mode
D. Routing optimization map
Answer: A

228. What is single-port RAM?

A. Memory with one address bit
B. Memory without a clock
C. Memory with one access port
D. Memory that stores one bit only
Answer: C

229. What is dual-port RAM?

A. Memory with two independently accessible ports
B. Memory with no write enable
C. Memory with exactly two locations
D. Memory that is always read-only
Answer: A

230. What is block RAM?

A. A simulation-only array
B. A group of blocked signals
C. External hard disk storage
D. Dedicated on-chip memory resource in an FPGA
Answer: D

231. What is distributed RAM?

A. Memory implemented only in external DDR
B. A configuration cable
C. A RAM with no address
D. Memory implemented using LUT resources
Answer: D

232. When is block RAM generally preferred over registers?

A. For combinational gates only
B. For larger memories
C. For a single control bit only
D. For clock generation
Answer: B

233. What is memory depth?

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 A. Number of bits in each location
B. Number of addressable locations
C. Number of clocks
D. Number of ports only
Answer: B

234. What is memory width?

A. Number of reset cycles
B. Number of RAM blocks in the device
C. Number of bits stored per location
D. Number of addressable locations
Answer: C

235. How many address bits are needed for 256 memory locations?
A. 16
B. 4
C. 8
D. 256
Answer: C

236. How many address bits are needed for 1024 memory locations?
A. 8
B. 1024
C. 12
D. 10
Answer: D

237. What does write enable control?

A. Whether the FPGA is configured
B. Whether output pins are analog
C. Whether the clock is generated
D. Whether input data is stored at the selected address
Answer: D

238. What is read latency?

A. Delay from applying an address to receiving valid read data
B. The size of the RAM
C. Time to write source code
D. Time between resets
Answer: A

239. What does memory initialization mean?

A. Setting initial contents of memory before or during configuration
B. Clearing source-code comments
C. Assigning FPGA pins
D. Measuring memory voltage
Answer: A

240. What is a memory initialization file used for?

A. Create a testbench clock
B. Store placement coordinates only
C. Specify only clock constraints
D. Provide initial ROM or RAM contents
Answer: D
Page 38
241. What is a FIFO?
A. Fast Input Frequency Oscillator
B. First-In, First-Out buffer
C. Field Interface File Object
D. Fixed Internal Function Output
Answer: B

242. What does FIFO full indicate?

A. The FPGA is fully utilized
B. The clock stopped
C. No data can be read
D. No additional data can be written safely
Answer: D

243. What does FIFO empty indicate?

A. The write clock is faster
B. The reset is asserted
C. No space is available to write
D. No valid data is available to read
Answer: D

244. What is FIFO overflow?

A. Resetting the write pointer
B. Reading when the FIFO is empty
C. Synchronizing clocks
D. Writing when the FIFO has no free space
Answer: D

245. What is FIFO underflow?

A. Loading a bitstream
B. Writing when the FIFO is full
C. Reading when the FIFO is empty
D. Increasing memory width
Answer: C

246. What is a circular buffer?

A. A clock distribution network
B. A physically round memory chip
C. A read-only shift register
D. A buffer whose address pointers wrap around
Answer: D

247. What does byte enable allow?

A. Programming configuration flash only
B. Selecting the FPGA device
C. Writing selected byte lanes of a wider memory word
D. Changing the clock period
Answer: C

248. What is memory inference?

A. Manually placing every memory transistor
B. Reading memory during simulation only
C. Connecting external DRAM without logic
D. Writing RTL patterns that synthesis recognizes as RAM or ROM
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 Answer: D

249. Why should vendor-supported RAM coding templates be followed?

A. To prevent parameters
B. To eliminate all simulation
C. To improve correct memory inference and behavior
D. To remove address decoding
Answer: C

250. What is a register file?

A. A routing database
B. An external flash image
C. A file containing only reset code
D. A small array of registers addressed for read and write
Answer: D

Page 40
Part 11: Arithmetic, Fixed-Point, and DSP
251. What is fixed-point representation?
A. A number format with unlimited precision
B. A clocked state encoding
C. A text-only numeric format
D. A number format with a fixed position for the binary point
Answer: D

252. What does Q1.7 commonly describe?

A. A RAM with 1 address and 7 data bits
B. A fixed-point format with 1 integer/sign-related bit and 7 fractional bits
C. A queue with 17 entries
D. A 1-bit number clocked at 7 MHz
Answer: B

253. What is quantization error?

A. A bitstream encryption failure
B. Error caused only by routing
C. Error caused by representing a value with limited precision
D. A clock-domain crossing event
Answer: C

254. What is truncation?

A. Changing signed data to text
B. Adding one to every result
C. Discarding lower or upper bits without rounding
D. Increasing bit width
Answer: C

255. What is rounding?

A. Discarding all fractional bits without consideration
B. Choosing the nearest representable value according to a rule
C. Always forcing the result to zero
D. Changing the clock frequency
Answer: B

256. What is saturation arithmetic?

A. Clamping overflowed results to minimum or maximum representable values
B. Resetting after every operation
C. Multiplying by the clock period
D. Allowing results to wrap around
Answer: A

257. What is wraparound arithmetic?

A. Clamping to the maximum value
B. Preventing any overflow
C. Using floating-point only
D. Discarding overflow bits so the value wraps modulo the word size
Answer: D

258. What is a multiply-accumulate operation?

Page 41
 A. Shift a value without arithmetic
B. Add two addresses and reset
C. Multiply two clocks
D. Multiply two values and add the product to an accumulator
Answer: D

259. Which FPGA resource is optimized for multiply-accumulate operations?

A. I/O pad
B. DSP slice
C. JTAG state machine only
D. Configuration pin
Answer: B

260. What is pipelining in a multiplier used for?

A. Remove the need for operands
B. Increase achievable clock rate and throughput
C. Convert multiplication into division
D. Eliminate all latency
Answer: B

261. What is operand width growth in multiplication?

A. The product always has the same width as one operand
B. The product width is unrelated to operands
C. The product needs one bit only
D. The product may require the sum of operand widths
Answer: D

262. What is arithmetic right shift?

A. Rotate without preserving sign
B. Right shift that replicates the sign bit
C. Left shift with wraparound
D. Right shift that always inserts ones
Answer: B

263. What is logical right shift?

A. A shift that changes no bits
B. Right shift that repeats the sign bit
C. Right shift that inserts zeros at the MSB side
D. A multiplication by two
Answer: C

264. For an unsigned integer, left shift by one is equivalent to:

A. Multiplication by 2 when no overflow occurs
B. Division by 2
C. Bitwise inversion
D. Addition of 1
Answer: A

265. For an unsigned integer, right shift by one is equivalent to:

A. Subtraction of 1
B. Addition of 2
C. Integer division by 2
D. Multiplication by 2
Answer: C
Page 42
266. What is a carry chain in an FPGA?
A. A list of testbench tasks
B. Dedicated fast routing for arithmetic carry propagation
C. A series of clock buffers
D. A JTAG cable
Answer: B

267. What is an accumulator?

A. A clock multiplexer only
B. A configuration memory
C. A register that repeatedly stores a running sum
D. A combinational decoder
Answer: C

268. What is a divider generally compared with an adder?

A. Impossible to implement in an FPGA
B. Purely analog
C. More resource-intensive and slower
D. Always smaller and faster
Answer: C

269. Which design approach can reduce divider hardware when the divisor is a power of two?
A. Use a multiplier by zero
B. Use a general iterative divider
C. Use a reset signal
D. Use a right shift
Answer: D

270. What is an iterative arithmetic unit?

A. A simulation-only function
B. A unit with no clock and infinite speed
C. A unit duplicated for every bit automatically
D. A unit that reuses hardware across multiple clock cycles
Answer: D

271. What is the area-throughput tradeoff?

A. More parallel hardware can increase throughput but consume more resources
B. More hardware always lowers throughput
C. Less hardware always lowers latency
D. Area and throughput are unrelated
Answer: A

272. What is DSP inference?

A. Generating a clock from data
B. Creating an FSM state
C. Coding arithmetic so synthesis maps it to dedicated DSP resources
D. Reading audio files in simulation
Answer: C

273. What is overflow detection for signed addition commonly based on?
A. The result equals one operand
B. Operands have the same sign but the result has the opposite sign
C. Carry-out is always zero
D. The operands have different widths only
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 Answer: B

274. What is precision?

A. The number of module instances
B. The clock voltage
C. The number of representable detail bits in a numeric format
D. The number of I/O pins
Answer: C

275. Why is fixed-point often used instead of floating-point in small FPGA designs?
A. It can use fewer resources and have predictable hardware cost
B. It always has greater dynamic range
C. It eliminates quantization
D. It requires no design decisions
Answer: A

Page 44
Part 12: Interfaces and Peripherals
276. What does UART stand for?
A. User Asynchronous Reset Trigger
B. Universal Asynchronous Receiver/Transmitter
C. Unified Address Routing Table
D. Universal Analog Register Timer
Answer: B

277. Does a basic UART require a shared clock line between transmitter and receiver?
A. No
B. Yes, always
C. Only for parity
D. Only for the start bit
Answer: A

278. What marks the beginning of a UART frame?

A. Stop bit
B. Start bit
C. Clock bit
D. Parity bit
Answer: B

279. What is the usual logic level of an idle UART line?

A. Low
B. High impedance only
C. High
D. Alternating every clock
Answer: C

280. What is baud rate?

A. Number of UART pins
B. Number of symbols transmitted per second
C. FPGA clock frequency only
D. Number of bytes stored in RAM
Answer: B

281. What is the purpose of a UART stop bit?

A. Reset the FPGA
B. Select parity type
C. Start the receiver clock
D. Mark the end of a frame and provide idle spacing
Answer: D

282. What is parity used for?

A. Clock multiplication
B. Data encryption
C. Address decoding
D. Simple error detection
Answer: D

283. What does SPI stand for?

Page 45
 A. System Programming Input
B. Serial Peripheral Interface
C. Synchronous Parallel Interconnect
D. Serial Phase Indicator
Answer: B

284. Which SPI signal is generated by the master to clock data?

A. MOSI
B. CS only
C. SCLK
D. MISO
Answer: C

285. What does MOSI mean in SPI?

A. Master Out, Slave In
B. Memory Output Signal Interface
C. Main Oscillator Slave Input
D. Master Only Serial Input
Answer: A

286. What does MISO mean in SPI?

A. Master Interface Serial Output
B. Main Internal System Oscillator
C. Memory Input Slave Output
D. Master In, Slave Out
Answer: D

287. What is chip select used for in SPI?

A. Set the clock frequency automatically
B. Select the target slave device
C. Carry data from slave to master
D. Reset all slaves permanently
Answer: B

288. What do CPOL and CPHA define in SPI?

A. Data width and address width
B. Parity and stop bits
C. Clock polarity and clock phase
D. Reset and enable levels
Answer: C

289. What does I2C stand for?

A. Input-to-Controller
B. Inter-Integrated Circuit
C. Integrated Interrupt Channel
D. Internal Two-Clock
Answer: B

290. How many main signal lines are used by I2C?

A. One
B. Three
C. Four
D. Two: SDA and SCL
Answer: D
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291. Why are pull-up resistors used on I2C lines?
A. I2C outputs are open-drain/open-collector
B. They store address bits
C. I2C lines are analog inputs only
D. They generate the clock
Answer: A

292. What is an I2C ACK?

A. A reset command
B. An address clock counter
C. An analog calibration key
D. An acknowledgment bit from the receiver
Answer: D

293. What is PWM?

A. Pulse-Width Modulation
B. Programmable Wire Mapping
C. Phase Window Multiplication
D. Parallel Word Memory
Answer: A

294. How is PWM duty cycle changed?

A. By changing the HDL language
B. By removing the counter
C. By changing the fraction of the period the output is high
D. By changing only the pin number
Answer: C

295. What is switch debouncing?

A. Assigning the switch to a clock pin
B. Increasing switch voltage
C. Converting a switch into analog data
D. Filtering rapid transitions caused by mechanical contacts
Answer: D

296. Why is a push button often synchronized before use?

A. It already uses the same clock
B. It is asynchronous to the FPGA clock
C. It contains a bitstream
D. It is always an analog signal
Answer: B

297. How is a seven-segment display commonly driven?

A. By UART only
B. By a PLL output
C. By controlling segment lines and possibly multiplexing digits
D. By configuration flash
Answer: C

298. What is display multiplexing?

A. Changing the FPGA configuration each digit
B. Driving every digit with no timing
C. Using analog video encoding
D. Rapidly activating digits one at a time so they appear continuously lit
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 Answer: D

299. What is a GPIO?

A. Global Programming Internal Oscillator
B. General-Purpose Input/Output
C. Generated Pulse Interface Option
D. General Parallel Instruction Operation
Answer: B

300. What is an interrupt-like event signal in FPGA logic typically used for?
A. Replace the system clock
B. Set I/O voltage automatically
C. Store large arrays
D. Notify control logic that an event occurred
Answer: D

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Part 13: Verification and Testbenches
301. What is the purpose of a testbench?
A. Configure FPGA pins physically
B. Generate PCB power
C. Provide stimulus and check the design during simulation
D. Replace the synthesized design
Answer: C

302. Does a testbench normally have external input and output ports?
A. No
B. Only analog ports
C. Yes, always
D. Only output ports
Answer: A

303. What is the DUT in verification?

A. Delay Unit Table
B. Design Under Test
C. Digital Usage Tool
D. Data Update Trigger
Answer: B

304. What is stimulus?

A. The placement database
B. The FPGA bitstream
C. Input patterns applied to the DUT
D. The clock constraint file only
Answer: C

305. What is a waveform viewer used for?

A. Inspect signal values over simulation time
B. Choose package pins
C. Place logic physically
D. Program the FPGA flash
Answer: A

306. What is functional simulation?

A. A timing report
B. Simulation of power supply only
C. Simulation after board assembly only
D. Simulation focused on logical behavior without detailed implementation delays
Answer: D

307. What is post-synthesis simulation?

A. Simulation of source-code comments
B. Simulation before writing RTL
C. Simulation using a synthesized netlist
D. Simulation with no DUT
Answer: C

308. What is timing simulation?

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 A. A pin-planning method
B. Simulation including estimated or annotated delays
C. Simulation with time removed
D. A synthesis optimization
Answer: B

309. What is a self-checking testbench?

A. A testbench that automatically compares actual and expected results
B. A testbench that never drives inputs
C. A testbench with only manual waveform inspection
D. A testbench synthesized into every FPGA
Answer: A

310. What is an assertion?

A. A physical pull-up resistor
B. A bitstream section
C. A clock buffer
D. A statement that checks a required condition during verification
Answer: D

311. What is a corner case?

A. A clock with 50% duty cycle
B. The center of the normal input range
C. An unusual boundary condition likely to expose bugs
D. A package pin at a corner only
Answer: C

312. Why should reset behavior be tested?

A. To increase simulation speed only
B. To remove all state
C. To verify the design enters known states and recovers correctly
D. To select I/O standards
Answer: C

313. What is randomized testing?

A. Generating varied inputs using random or pseudo-random methods
B. Ignoring expected outputs
C. Testing only input zero
D. Changing the FPGA device randomly during synthesis
Answer: A

314. What is directed testing?

A. Applying specifically chosen input sequences
B. Using only random inputs
C. Testing without expected behavior
D. Testing only after implementation
Answer: A

315. What is coverage in verification?

A. The physical area of the FPGA package
B. A measure of which behaviors or structures have been exercised
C. The bitstream compression ratio
D. The number of board connectors
Answer: B
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316. What is code coverage?
A. Measurement of routing length only
B. Measurement of clock frequency only
C. Measurement of executed HDL statements, branches, or conditions
D. Measurement of flash capacity
Answer: C

317. What is functional coverage?

A. Measurement of source-code indentation
B. Measurement of FPGA temperature
C. Measurement of whether specified scenarios and value combinations occurred
D. Measurement of pin count
Answer: C

318. Why are simulation delays commonly used in a testbench?

A. To assign FPGA pins
B. To schedule stimulus and model timing behavior
C. To reduce LUT usage
D. To synthesize physical delay lines automatically
Answer: B

319. Why should testbench-only delays not be relied upon in synthesizable RTL?
A. They are required for every register
B. They improve timing closure automatically
C. They create block RAM
D. They generally do not describe portable real hardware timing
Answer: D

320. What is a clock generator in a testbench?

A. A synthesis constraint
B. A process that toggles the clock periodically
C. A PLL placed on the board
D. A memory initialization file
Answer: B

321. What is a reference model?

A. The FPGA package drawing
B. The routing algorithm
C. A reset synchronizer only
D. A trusted model used to compute expected results
Answer: D

322. What is regression testing?

A. Skipping previously passing tests
B. Changing the target board every time
C. Testing one case only
D. Rerunning a test suite after changes to detect new failures
Answer: D

323. What is a test vector?

A. A clock tree branch
B. A physical direction on the PCB
C. A synthesis license file
D. A specific set or sequence of DUT inputs
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 Answer: D

324. What does X usually represent in four-state simulation logic?

A. High impedance
B. Exactly zero
C. Unknown value
D. Exactly one
Answer: C

325. What does Z usually represent in four-state simulation logic?

A. Unknown arithmetic overflow
B. High-impedance value
C. Clock edge
D. Reset state
Answer: B

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Part 14: Tools, Board Workflow, Debugging, and Optimization
326. What is JTAG commonly used for in FPGA development?
A. Creating source-code parameters
B. Programming and debugging the device
C. Increasing LUT size
D. Generating analog power
Answer: B

327. What is boundary scan?

A. A Verilog loop
B. A JTAG-based method for testing device pins and board connections
C. A memory allocation method
D. A clock multiplication mode
Answer: B

328. What is an integrated logic analyzer (ILA) core?

A. A configuration flash
B. On-chip debug logic that captures internal signals
C. An external analog oscilloscope only
D. A synthesis optimizer
Answer: B

329. Why is an ILA useful?

A. It programs the PCB microcontroller only
B. It replaces all testbenches
C. It guarantees timing closure
D. It observes internal FPGA signals while hardware is running
Answer: D

330. What limits the capture depth of an on-chip logic analyzer?

A. The clock duty cycle only
B. The number of source-code comments
C. Available on-chip memory resources
D. The USB cable color
Answer: C

331. What is a trigger condition in an ILA?

A. A RAM width setting
B. An event that starts or qualifies signal capture
C. A command that erases the FPGA
D. A pin constraint
Answer: B

332. What is pin planning?

A. Choosing FSM states
B. Assigning design ports to suitable physical package pins
C. Writing testbench vectors
D. Selecting arithmetic operators
Answer: B

333. Why must board schematics be checked before assigning pins?

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 A. To match FPGA pins with actual board components and electrical connections
B. To choose simulation delays
C. To calculate only RAM depth
D. To determine Verilog syntax
Answer: A

334. What is a top-level module?

A. A testbench task
B. A synthesis report
C. The first module alphabetically
D. The highest module connecting the design to external ports
Answer: D

335. What is a project constraint mismatch likely to cause?

A. A larger LUT input count
B. Automatic improvement in Fmax
C. Incorrect pin behavior or timing analysis
D. Perfect simulation results
Answer: C

336. What is the purpose of programming configuration flash?

A. Allow the FPGA to load a design automatically at power-up
B. Increase clock frequency
C. Store waveform screenshots
D. Replace block RAM during operation
Answer: A

337. What is a common first step when hardware output is wrong but simulation passes?
A. Check pin assignments, clocks, resets, and I/O standards
B. Increase every signal width
C. Delete all registers
D. Remove timing constraints
Answer: A

338. Why can a design pass behavioral simulation but fail on hardware?
A. Real timing, reset, CDC, and I/O conditions may differ
B. HDL cannot represent registers
C. Hardware ignores the bitstream
D. Simulation always models every physical effect perfectly
Answer: A

339. What is resource utilization optimization?

A. Removing all hierarchy labels
B. Changing only waveform colors
C. Reducing or balancing use of LUTs, registers, RAM, and DSP blocks
D. Increasing source-code length
Answer: C

340. What is timing optimization?

A. Removing all clocks
B. Adding arbitrary delays to RTL
C. Changing architecture or implementation to meet required clock performance
D. Using only behavioral simulation
Answer: C
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341. What is power optimization?
A. Driving all outputs continuously
B. Increasing every clock frequency
C. Reducing unnecessary switching and resource activity
D. Duplicating all logic
Answer: C

342. What contributes to dynamic power in digital logic?

A. Only source-code comments
B. Only static leakage
C. Only board dimensions
D. Signal switching activity and clock frequency
Answer: D

343. Why can clock enables reduce dynamic power?

A. They prevent unnecessary register toggling
B. They increase the number of clock edges
C. They remove configuration memory
D. They force all LUTs to toggle
Answer: A

344. What is an IP core?

A. A reusable predesigned hardware block
B. A source-code comment format
C. A simulation timestamp
D. A physical FPGA pin only
Answer: A

345. Why use a vendor IP catalog?

A. Remove the need for constraints
B. Replace HDL with analog circuits
C. Quickly integrate tested functions such as memory, FIFO, PLL, or interfaces
D. Avoid all synthesis
Answer: C

346. What is IP customization?

A. Changing the FPGA package physically
B. Replacing the board power supply
C. Editing the silicon transistors manually
D. Setting parameters such as width, depth, and clock options
Answer: D

347. What is version control useful for in FPGA projects?

A. Programming the FPGA without tools
B. Tracking HDL, constraints, scripts, and changes
C. Replacing simulation
D. Measuring clock jitter directly
Answer: B

348. Which files should generally be kept under version control?

A. Only waveform screenshots
B. Only temporary generated cache files
C. Source HDL, constraints, scripts, and reproducible configuration files
D. Only the final bitstream with no source
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 Answer: C

349. What is reproducible build automation?

A. Deleting all reports
B. Using scripts and fixed settings so the project can be rebuilt consistently
C. Manually changing settings every build
D. Ignoring tool versions
Answer: B

350. What is the best final verification before submitting an FPGA lab?
A. Remove all warnings by hiding reports
B. Assume simulation is enough without checking constraints
C. Rebuild, check reports, program the board, and test required functions
D. Submit only screenshots without source
Answer: C

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