The Functions of a Computer

Detailed Study Notes — Computer & Microprocessor Architecture Fundamentals

1. Introduction
A computer is, at its core, a machine that accepts input, processes it according to a stored set of instructions, and produces
output. Every computer — from an 8-bit microcontroller inside a washing machine to a multi-core server — is built around
the same conceptual skeleton: a processing unit, memory, and a way to talk to the outside world. This note builds that
skeleton up from first principles, then goes inside the CPU itself to explain registers, the ALU, the control unit, buses,
interrupts, and finally how a microprocessor actually executes an instruction cycle by cycle.

2. A Typical Computer System — Early Days

In the earliest general-purpose computer designs (following the von Neumann model), the system was organized as four
separate functional blocks connected directly to the Central Processing Unit (CPU):

• Input — devices that bring data/instructions into the machine (punch card readers, keyboards, etc.)
• CPU — the 'brain' that fetches, decodes and executes instructions
• Memory — stores both instructions and data
• Output — devices that present results to the outside world (printers, displays, etc.)
In this early arrangement, the CPU had dedicated point-to-point connections to Input, Memory, and Output separately. This is
simple to reason about but does not scale — every new device needs its own dedicated wiring into the CPU, which quickly
becomes impractical as systems grow.

3. A Typical Computer System — Nowadays (Shared Bus

Architecture)
Modern computers replace the separate point-to-point links with a shared bus — a common highway of wires that all
components (CPU, Memory, Input, Output) connect to and communicate over. Only one device 'talks' on the bus at a time
(using addressing and control signals to avoid collisions), but any device can reach any other device through the same
physical set of lines.

• Advantage: Adding a new device only means tapping into the existing bus, not running new dedicated wires to the
CPU.
• Trade-off: Because the bus is shared, only one transfer can happen at a time, which can become a bottleneck — this is
sometimes called the 'von Neumann bottleneck.'

3.1 Why Peripheral Interface Chips Are Needed

A microprocessor (µP) cannot directly drive real-world I/O devices by itself. Its bus lines are electrically and logically
designed to talk to memory-like devices, not directly to keyboards, motors, or displays. Therefore, dedicated
peripheral/interface chips sit between the CPU bus and the actual I/O hardware, translating bus transactions into the signals a
device understands.
A classic example is the Intel 8255 Programmable Peripheral Interface (PPI) — a chip that provides 24 general-purpose I/O
lines (grouped as Port A, Port B, and Port C) that the CPU can configure and use to talk to switches, LEDs, printers, and
similar simple devices. This is why the modern block diagram is drawn as CPU — Memory — Input/Output, all connected
via a shared bus, with chips like the 8255 acting as the bridge to physical devices.

4. Memory
Memory is the subsystem that stores both instructions and data:

• Instructions: coded pieces of information that direct/control the activities of the CPU (the program).
• Data: coded pieces of information that are processed by the CPU (the operands the program works on).
In a classic von Neumann architecture, instructions and data share the same memory space and the same bus — the CPU
cannot fetch an instruction and a data operand in the same bus cycle. In a Harvard architecture (used in many modern
microcontrollers and DSPs), instruction memory and data memory are physically separate, allowing simultaneous instruction
fetch and data access, which improves performance.

Note: Most general-purpose microprocessors (8085, 8086, x86, ARM application cores) are von-Neumann-style at the
programmer's model level, even though internally many use a 'modified Harvard' cache architecture for speed.

5. Input and Output Ports

5.1 Why Ports Are Needed
Memory alone is often not large enough (or not appropriate) to hold all the data an application needs to exchange with the
real world in real time. Input Ports solve this by giving the CPU a dedicated gateway to receive information from external
equipment (sensors, keyboards, communication links) as and when it arrives, rather than requiring everything to be pre-
loaded into memory.

5.2 Output Ports

Symmetrically, Output Ports let the CPU communicate the results of its processing to the outside world. Typical destinations
include:

• A display unit — for a human operator to read results directly

• A peripheral device that produces 'hard copy' — e.g. a printer
• A peripheral storage device — e.g. a hard disk
• Process-control signals — e.g. controlling actuators/motors/valves in an industrial control system

5.3 Memory-Mapped vs I/O-Mapped I/O (extension)

There are two common schemes for addressing ports:

• I/O-mapped I/O: Ports have their own separate address space and are accessed with special instructions (e.g. IN / OUT
in x86). Memory and I/O address spaces do not overlap.
• Memory-mapped I/O: Ports are assigned addresses within the normal memory address space and are accessed using
ordinary memory-read/write instructions — simpler instruction set, but 'uses up' part of the memory address range.
6. The Internal Architecture of a CPU
Zooming inside the CPU block itself, three major functional units are connected together by an internal bus:

• Registers (R1, R2, R3, ... Rn) — small, extremely fast storage locations inside the CPU
• Arithmetic Logic Unit (ALU) — performs arithmetic and logic operations
• Control Circuitry / Control Unit (CU) — sequences and coordinates everything
The CPU also has I/O lines for external communication — this is where the CPU connects out to the system's address, data,
and control buses.

6.1 Registers
Registers are temporary storage units located within the CPU itself. Because they sit inside the processor (rather than out on
the memory bus), reading and writing a register is far faster than accessing main memory.

• Some registers have dedicated, fixed uses (e.g. Program Counter, Stack Pointer, Flag register).
• Others are general-purpose and can be used flexibly by the programmer/compiler for whatever value is needed at the
time.
• In many microprocessors, one register is specially designated the Accumulator — the primary register through which
most ALU results pass.
• The number of registers, and how they are organized, varies significantly from one microprocessor to another (e.g. the
8085 has a small register set; modern x86-64 CPUs have many more, plus renamed 'hidden' registers internally).

6.2 Arithmetic Logic Unit (ALU)

As the name implies, the ALU is the portion of CPU hardware that performs arithmetic and logic operations on binary data.
At its heart, an ALU generally contains an adder circuit, because:

• Arithmetic operations — addition is performed directly; subtraction is commonly implemented using 2's complement
addition; multiplication and division are built up from repeated addition/shifting (or dedicated hardware in modern
CPUs).
• Logic operations — bitwise AND, OR, NOT (and typically XOR, shifts, and rotates as well) are performed directly on
the bit patterns.

6.2.1 Flags
The ALU also sets Flag bits (in a Flag/Status register) that record certain conditions or status information after an arithmetic
or logic operation completes. Flags are essential because they let the program make decisions (conditional jumps) based on
the outcome of the previous operation. Common flags found across most microprocessors include:

Flag Meaning

Zero (Z) Set if the result of the operation is zero

Carry (CY) Set if there is a carry out of the most significant bit (unsigned overflow)

Sign (S) Set to match the most significant bit of the result (indicates negative in signed
representation)

Overflow (O/V) Set if a signed arithmetic operation produces a result too large to fit in the
destination

Parity (P) Set based on whether the result has an even or odd number of 1-bits
 Flag Meaning

Auxiliary/Half Carry (AC) Set if there is a carry out of a lower nibble into a higher nibble (used for BCD
arithmetic)

6.3 Control Unit (CU)

The Control Unit is the primary functional unit within a CPU — it does not itself do arithmetic, but it maintains the correct
sequence of events required for every processing task, using the clock as its timing reference. The CU issues the appropriate
control signals to initiate the correct action in every other unit, both internal to the CPU (registers, ALU) and external to it
(memory, I/O ports).

There are two broad design philosophies for building a CU (extension beyond the slides):

• Hardwired control: control signals are generated by fixed logic circuits (gates, flip-flops). Fast, but inflexible and hard
to modify/extend.
• Microprogrammed control: control signals are generated by 'micro-instructions' stored in a small internal control
memory. Easier to design and modify, at some cost to raw speed.

6.3.1 Interrupts
The CU is often capable of responding to external signals known as interrupts. An interrupt request causes the CU to
temporarily suspend execution of the main program in order to service the interrupting device; once servicing is complete,
the CU automatically resumes the main program from exactly where it left off.

Extension — interrupts are usually classified along two axes:

• Hardware vs Software: Hardware interrupts come from external pins/devices (e.g. a peripheral signalling it has data
ready); software interrupts are triggered deliberately by an instruction in the program (e.g. INT in x86), often used for
OS system calls.
• Maskable vs Non-maskable: Maskable interrupts can be selectively ignored ('masked') by the programmer when not
wanted; non-maskable interrupts (NMI) cannot be disabled and are reserved for critical events (e.g. power failure).
• Vectored vs Non-vectored: In a vectored interrupt, the interrupting device itself supplies (or implies) the address of its
service routine; in a non-vectored interrupt, the CPU always jumps to one fixed, predetermined address and software
then figures out which device needs service.

7. Buses
A bus is a set of single or parallel lines grouped together that connect the registers, ALU, and CU (and, at the system level,
the CPU, memory, and I/O) with each other, allowing them to exchange information. There are three functional types of bus
in any CPU/system design:

Bus Direction Purpose

Address Bus Unidirectional (CPU → Carries the address that identifies which memory
Memory/I/O) location or I/O port is being accessed. Its width
(16/20/24/32/64-bit) determines the maximum
addressable space.

Data Bus Bidirectional Carries the actual data being transferred, in either
direction, between CPU and memory/I/O. Its width
 Bus Direction Purpose

(8/16/32/64/128-bit) is a major factor in how much

data can move per cycle — this is closely related to
the notion of an 'n-bit processor' (see Section 10).

Control Bus Mixed (some lines CPU → Carries timing and coordination signals such as
outside, some outside → CPU) read/write strobes, ready signals, clock signals, and
interrupt request/acknowledge lines.

Note: A wider address bus means more addressable memory (e.g. a 20-bit address bus, as in the 8086, can address 2^20 =
1,048,576 locations = 1 MB), while a wider data bus generally means higher throughput per bus cycle.

8. Microprocessor — Basic Concept

A microprocessor (µP) integrates the Control Unit, ALU, and the data/pointer registers onto a single chip, and exposes three
buses to the outside world: the Address Bus, the Control Bus (carrying timing signals, ready signals, interrupts, etc.), and the
bidirectional Data Bus.

However, a microprocessor by itself is completely useless — it must be connected to external peripheral chips on a
motherboard to form a working system, typically including:

• Boot ROM — firmware used at startup to bring the system up

• Instruction (program) ROM — permanent storage for the program to run
• RAM — working memory for data and, often, a runtime copy of the program
• UART — for serial communication
• Parallel interface chips — for connecting to devices like a keyboard or screen
• Transducers and other application-specific I/O
All of these external chips are wired together with the microprocessor through the shared Address, Data, and Control buses.

9. Microcontroller — Basic Concept

A microcontroller (µC) takes the microprocessor idea one step further: it puts a limited amount of the most commonly needed
resources — RAM, ROM, I/O ports, and a timer — inside the same chip as the CPU core. Even though the amount of on-
chip RAM/ROM is 'limited' compared to a full computer, it is 'enough' for the majority of embedded applications (household
appliances, simple industrial controllers, sensors, etc.), removing the need for most external support chips.

9.1 Microprocessor vs Microcontroller

Aspect Microprocessor (µP) Microcontroller (µC)

On-chip memory/I/O None (external RAM/ROM/I/O RAM, ROM, I/O ports, timers built in
required)

External components needed Many (RAM, ROM, I/O chips, etc.) Very few — mostly self-contained

Pin count High Lower

Typical use General-purpose computing (PCs, Embedded/dedicated control tasks

servers)
 Aspect Microprocessor (µP) Microcontroller (µC)

Cost & board size Higher (more chips, bigger board) Lower (fewer chips, compact board)

Design/upgrade effort More complex to design and modify Simpler, faster design cycle

9.2 Advantages of Microcontroller over Microprocessor

• Lower pin count, since many buses stay internal to the chip
• Reduced design time and smaller board layout size
• Easier upgrade path, since on-chip peripherals are already speed-matched to the core
• Lower cost, partly from simpler boards and partly from bulk-purchasing a single chip
• Higher reliability, since fewer external connections means fewer points of failure
• A common, unified software and hardware design environment, usually supplied by the manufacturer

10. Operation of a Microprocessor — Fetch, Decode, Execute

At the most fundamental level, a microprocessor runs a program by repeating a three-step cycle for every single instruction:

• 1. Fetch — the CPU reads the next instruction from memory, using the address held in the Program Counter (PC); the
PC is then incremented to point to the following instruction.
• 2. Decode — the Control Unit interprets the fetched bit pattern to determine which operation is being requested and
which operands/registers are involved.
• 3. Execute — the CU issues the control signals needed to actually carry out the operation (e.g. the ALU performs an
addition, or data is moved between a register and memory).

10.1 Instruction Cycle, States, and Clock Period

The combined fetch-decode-execute sequence for a single instruction is known as the Instruction Cycle. Within a cycle, the
CPU passes through several States:

• State: a portion of the cycle associated with one clearly-defined activity (for example, 'fetch opcode' or 'read memory
operand').
• Clock period: the interval between successive pulses of the timing oscillator that drives the CPU — the most basic
'tick' the CPU can measure.
As a general rule, completing a single state requires one or more clock periods, and a full instruction cycle is made up of
several states. This is why different instructions take different numbers of clock cycles to complete — a simple register-to-
register move might need only a few clock periods, while an instruction that reads from memory, does arithmetic, and writes
back the result will need considerably more.

Extension — in many real processors (e.g. the 8085/8086 family) this hierarchy is described with more granular terms:

• T-state (Time state) — one clock period, the smallest unit of time in the CPU
• Machine cycle — a group of T-states corresponding to one bus transaction, such as 'opcode fetch,' 'memory read,' or
'memory write'
• Instruction cycle — one or more machine cycles required to fetch and fully execute one complete instruction
11. What Is an n-bit Processor?
If a processor can operate on n bits of data simultaneously (in a single ALU operation), it is called an n-bit processor.
Because the ALU is the unit that actually performs the arithmetic/logic operation on the data, it is the width of the ALU (and
its associated internal data path/registers) that determines the 'size' of the processor — not, strictly speaking, the width of the
external data bus, address bus, or the registers used for addressing.

For example, a processor with an 8-bit-wide ALU that processes 8 bits of data per operation is termed an 8-bit processor (e.g.
the Intel 8085), even if some of its addressing registers are wider. A processor built around a 16-bit ALU (e.g. the Intel 8086)
is a 16-bit processor. This naming convention has continued through 32-bit and 64-bit processor generations.

Note: It's a common point of confusion that a processor's 'bit-ness' is sometimes loosely equated with its address-bus
width. Strictly, the ALU/data-path width defines the n in 'n-bit processor'; the address bus width instead determines the
maximum addressable memory, and the two numbers do not have to match (the 8086, for instance, is a 16-bit processor
with a 20-bit address bus).

12. Quick Revision Summary

Concept One-line takeaway

Computer system Input + CPU + Memory + Output, now connected via a shared bus instead of separate
wires

Memory Stores both instructions (control the CPU) and data (processed by the CPU)

I/O Ports Gateways for the CPU to exchange information with the outside world beyond what
memory alone can hold

Registers Fast temporary storage inside the CPU; some dedicated, some general-purpose

ALU Performs arithmetic/logic operations; sets flags describing the result

Control Unit Sequences all CPU activity using the clock; handles interrupts

Buses Address (where), Data (what), Control (how/when)

Microprocessor CU + ALU + registers on one chip; needs external RAM/ROM/I/O to be useful

Microcontroller Microprocessor + RAM + ROM + I/O + timer, all on one chip — self-contained for
embedded use

Instruction cycle Fetch → Decode → Execute, built from states/clock periods (T-states → machine
cycles → instruction cycle)

n-bit processor n = width of the ALU/data path that is processed simultaneously