Chapter 5 — Processors Comprehensive Study Notes

Chapter 5
Processors
Comprehensive Study Notes — Cross-Verified Against Textbook

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Chapter 5 — Processors Comprehensive Study Notes

Contents
TOC \h \o "1-3"

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Chapter 5 — Processors Comprehensive Study Notes

1. The Processor — An Overview

A processor (also called the Central Processing Unit, or CPU) is the electronic component that
executes instructions. It is the 'brain' of the computer — it carries out the fetch-decode-execute
cycle continuously, processing billions of instructions per second in modern systems.

Every program you run, every keystroke processed, every pixel drawn on screen, is the result of
the processor executing a sequence of simple instructions stored in memory. Understanding
how this works at the hardware level is central to this chapter.

CHAPTER 5 CORE TOPICS

1. Processor architecture — components and their roles (ALU, CU, registers, buses)
2. The Fetch-Decode-Execute (FDE) cycle — how instructions are processed
3. Factors affecting processor performance — clock speed, cores, cache, pipelining
4. Memory hierarchy — registers, cache, RAM, secondary storage
5. Input and Output devices — types, interfaces, and how they communicate with the CPU
6. Secondary storage — magnetic, optical, and solid-state technologies
7. Buying a computer — real-world application of performance factors

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2. Processor Architecture
Processor architecture refers to the internal organisation of the CPU — its components and how
they connect. The standard architecture taught at this level is the von Neumann architecture, in
which a single memory stores both program instructions and data, and a single processor
executes instructions one at a time.

VON NEUMANN ARCHITECTURE — CORE PRINCIPLE

Programs (instructions) and data are both stored in the same memory.
The CPU fetches instructions from memory and executes them sequentially.
This contrasts with Harvard Architecture, where instruction memory and data memory are
physically separate (used in some embedded systems and CPUs with separate instruction/data
caches).

2.1 Main Components of the CPU

The CPU contains three main functional units: the Arithmetic Logic Unit (ALU), the Control Unit
(CU), and a set of registers. These are connected internally by the internal bus.

Arithmetic Logic Unit (ALU)

The ALU performs all arithmetic and logical operations. It is the computational engine of the
CPU. Every mathematical calculation and every Boolean/comparison operation passes through
the ALU.

• Arithmetic operations: addition, subtraction, multiplication, division

• Logical operations: AND, OR, NOT, XOR (the Boolean operations from Chapter 4)
• Comparison operations: greater than, less than, equal to — producing flags used for
branching
• Shift operations: shifting bits left or right (equivalent to multiplying/dividing by 2)

EXAM QUESTION TYPE

Q: 'State two types of operation performed by the ALU.'
A: Arithmetic operations (e.g. addition, subtraction) AND logical/Boolean operations (e.g. AND,
OR, NOT).
Do NOT just say 'calculations' — be specific and give examples.

Control Unit (CU)

The Control Unit is the manager of the CPU. It does not perform calculations itself — instead it
directs all other components, coordinating the fetch-decode-execute cycle.

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• Fetches instructions from main memory

• Decodes instructions — determines what operation is required
• Sends control signals to the ALU, registers, memory, and I/O devices
• Controls the timing of all operations using the system clock
• Manages the flow of data along the internal and system buses

EXAM QUESTION TYPE

Q: 'Describe the role of the Control Unit.'
A: The Control Unit manages and coordinates the operation of the CPU. It fetches instructions
from memory, decodes them to determine what action is needed, and sends control signals to
direct the ALU, registers, and other components. It does NOT perform calculations itself.

2.2 Registers
Registers are extremely fast, small memory locations built directly into the CPU. They hold data
that is currently being used or processed. Because they are on the CPU chip itself (not separate
memory chips), access to registers is almost instantaneous — they are the fastest storage in
the entire system.

Program Counter (PC)

The Program Counter holds the memory address of the NEXT instruction to be fetched. After
each fetch, the PC is automatically incremented to point to the following instruction. During a
branch or jump instruction, the PC is updated to the branch address instead.

EXAM QUESTION TYPE — PC

Q: 'What is the role of the Program Counter?'
A: The Program Counter holds the memory address of the next instruction to be fetched from
main memory. It is incremented after each fetch so that instructions are processed in sequence,
unless a branch instruction redirects it.

Memory Address Register (MAR)

The MAR holds the memory address of the location in main memory that is about to be read
from or written to. Before any memory access, the required address is placed into the MAR. The
address bus then carries this address to memory.

MAR IN THE FDE CYCLE

During FETCH: PC value is copied into MAR, then the address in MAR is sent along the address
bus to memory.
During EXECUTE: if the instruction requires a memory access (e.g. LOAD or STORE), the data

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address is placed in MAR before the memory operation.

Memory Data Register (MDR) / Memory Buffer Register (MBR)

The MDR (also called the MBR in some textbooks — both terms refer to the same register)
temporarily holds data that has just been read from memory or data that is about to be written to
memory. It acts as a buffer between the CPU's high-speed internal operations and the slower
main memory.

• When reading from memory: data fetched from memory is placed in the MDR before
being transferred to other registers
• When writing to memory: data to be written is placed in the MDR first, then transferred to
memory

Current Instruction Register (CIR) / Instruction Register (IR)

The CIR holds the instruction that is currently being decoded and executed. Once an instruction
is fetched from memory and placed in the MDR, it is then transferred to the CIR so the Control
Unit can decode and act on it.

EXAM QUESTION TYPE — CIR

Q: 'What does the CIR store?'
A: The CIR stores the instruction that is currently being decoded and executed by the Control
Unit.

Accumulator (ACC)
The Accumulator is a general-purpose register that stores intermediate results of ALU
operations. In many instruction sets, one operand of every arithmetic operation must be in the
accumulator, and the result is placed back in the accumulator.

Example: To add two numbers, you load the first number into the ACC, then ADD the second
number — the result goes back into the ACC.

General-Purpose Registers
Modern processors have many general-purpose registers (often 8, 16, or 32) that can hold any
data: integers, memory addresses, or intermediate calculation results. They allow the CPU to
keep frequently-used data inside the processor, avoiding slow memory accesses.

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2.3 The System Buses

A bus is a set of parallel electrical wires that carry signals between components. The system
bus connects the CPU to main memory and I/O devices. There are three separate buses, each
carrying a different type of signal.

Bus Name What It Carries Direction Width Effect

Address Bus Memory addresses CPU → Memory / I/O Width determines
(which location to (unidirectional) addressable memory
access)
Data Bus Actual data being Bidirectional (both Width determines data
transferred directions) transfer amount
Control Bus Control signals (read, Bidirectional Coordinates all
write, clock, interrupt) operations

Address Bus Width

The width of the address bus determines how many different memory locations the CPU can
directly address. Each additional bit doubles the addressable memory.

Number of addressable locations = 2^(address bus width)

ADDRESS BUS WIDTH EXAMPLES — VERIFIED

16-bit address bus: 2^16 = 65,536 locations (64 KB)
32-bit address bus: 2^32 = 4,294,967,296 locations (4 GB)
64-bit address bus: 2^64 = 18,446,744,073,709,551,616 locations (16 exabytes)
This is why 32-bit operating systems cannot use more than 4 GB of RAM — the address bus is
not wide enough to point to more locations.

Data Bus Width

The width of the data bus determines how many bits are transferred in a single bus transaction.
A 64-bit data bus transfers twice as much data per cycle as a 32-bit bus, increasing throughput.

EXAM QUESTION TYPE — BUSES

Q: 'Explain why increasing the width of the address bus increases the amount of memory a CPU
can use.'
A: Each bit on the address bus can be either 0 or 1. With n bits, the CPU can generate 2^n
different addresses, each pointing to a unique memory location. Increasing n (making the bus
wider) exponentially increases the number of addressable locations, allowing more RAM to be
installed and used.

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Q: 'State one difference between the address bus and the data bus.'
A: The address bus is unidirectional (carries addresses from CPU to memory only), whereas the
data bus is bidirectional (data can travel in either direction between CPU and memory).

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3. The Fetch-Decode-Execute (FDE) Cycle

The Fetch-Decode-Execute cycle (also called the instruction cycle) is the fundamental process
by which the CPU processes instructions. It repeats continuously while the computer is running.
Every single instruction in every program goes through this cycle.

THE THREE STAGES

FETCH — Retrieve the next instruction from main memory
DECODE — Interpret the instruction to determine what action is required
EXECUTE — Carry out the instruction

This cycle repeats billions of times per second in a modern CPU.

3.1 FETCH Stage — Detailed Steps

The fetch stage retrieves the next instruction from main memory and places it in the CIR. Here
is every micro-operation that occurs:

Step 1: The value stored in the Program Counter (PC) — the address of the next
instruction — is copied into the Memory Address Register (MAR).
Step 2: The address in the MAR is placed on the Address Bus. A READ signal is sent on
the Control Bus.
Step 3: Main memory reads the instruction at that address and places it on the Data Bus.
Step 4: The data on the Data Bus is received and stored in the Memory Data Register
(MDR).
Step 5: The instruction is copied from the MDR into the Current Instruction Register (CIR).
Step 6: The Program Counter is incremented by 1 (or by the instruction size) so it now
points to the NEXT instruction.

IMPORTANT: WHEN DOES THE PC INCREMENT?

The PC is incremented DURING the fetch stage (step 6 above), BEFORE the instruction is
executed.
This means the PC always points to the NEXT instruction to be fetched, not the one currently
being executed.
This happens automatically and continuously — it is why instructions execute in sequence by
default.

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3.2 DECODE Stage

The Control Unit reads the instruction now held in the CIR and decodes it. Decoding means
determining:

• What type of operation is required (arithmetic, logic, data transfer, branch, etc.)
• What data or memory addresses are involved (the operand)
• Which components need to be activated to carry out the instruction

The instruction is split into its opcode (operation code — what to do) and operand (what data or
address to act on). The CU then sets up the necessary internal pathways and signals.

3.3 EXECUTE Stage

The Control Unit sends signals to execute the decoded instruction. What happens in this stage
depends entirely on the instruction type:

Instruction Type Example What Happens During

Execute
Arithmetic ADD R1, R2 ALU adds values in R1 and R2;
result stored in accumulator or
destination register
Logic AND R1, R2 ALU performs Boolean AND on
the values; result stored in
destination register
Data Load LOAD R1, [100] MAR ← 100; memory read;
MDR ← data from address 100;
R1 ← MDR
Data Store STORE R1, [200] MAR ← 200; MDR ← R1;
memory write at address 200
Branch JUMP 500 PC is updated to 500 (not
incremented normally) —
execution continues from
address 500
Conditional BRANCH IF ZERO Checks flag from ALU; if
condition met, PC ← branch
address; else PC continues
normally
I/O OUTPUT R1 Contents of R1 sent to output
device via I/O controller

EXAM QUESTION TYPE — FDE CYCLE DETAIL

Q: 'Describe, using register names, what happens during the fetch stage.'

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A: The contents of the PC are copied to the MAR. The address in the MAR is sent along the
address bus to main memory. A read signal is sent along the control bus. The instruction at that
address is returned along the data bus and stored in the MDR. The instruction is then copied
from the MDR to the CIR. The PC is incremented to point to the next instruction.

Q: 'What is the role of the MAR during the fetch stage?'

A: The MAR holds the address of the memory location being accessed. During fetch, it holds the
address of the next instruction (copied from the PC) so that address can be placed on the
address bus.

3.4 Registers Used in Each Stage — Summary Table

Stage Registers Involved Action
Fetch PC → MAR Address of next instruction sent
to MAR
Fetch MAR → Address Bus Address placed on address bus
Fetch Data Bus → MDR Instruction loaded from memory
into MDR
Fetch MDR → CIR Instruction moved to CIR for
decoding
Fetch PC + 1 → PC PC incremented to next
instruction
Decode CIR CU reads and interprets opcode
and operand
Execute CIR → ALU Operands sent to ALU for
arithmetic/logic
Execute ALU → ACC Result stored in accumulator
Execute ACC → MAR/MDR For STORE instructions, data
written to memory
Execute CIR → PC For JUMP instructions, PC
updated to branch address

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4. Factors Affecting Processor Performance

A processor's performance — how fast it can execute instructions — is determined by several
interacting factors. Understanding these factors is essential for both exam questions and the
'buying a computer' section of the chapter.

THE FOUR MAIN PERFORMANCE FACTORS

1. Clock Speed — how many cycles per second the processor runs
2. Number of Cores — how many independent processors are on the chip
3. Cache Size — how much fast on-chip memory is available
4. Pipelining — executing multiple instruction stages simultaneously

4.1 Clock Speed

The system clock generates a regular electrical pulse (the clock signal) that synchronises all
operations inside the CPU. Every operation takes a whole number of clock cycles to complete.
Clock speed is measured in Hertz (Hz) — cycles per second.

Unit Value Typical Use

1 Hz 1 cycle per second Extremely slow — theoretical
1 MHz 1,000,000 cycles per second Early home computers (1980s)
1 GHz 1,000,000,000 cycles per Modern CPUs (range: 3–6 GHz)
second

A higher clock speed means more cycles per second, allowing more instructions to be executed
per second — assuming the same number of cycles per instruction.

EXAM QUESTION TYPE — CLOCK SPEED

Q: 'Explain how an increase in clock speed affects processor performance.'
A: A higher clock speed means the processor completes more cycles per second. Since each
instruction takes a fixed number of clock cycles, more cycles per second means more
instructions can be executed per second, increasing overall performance. However, higher clock
speeds generate more heat and consume more power.

Q: 'A processor has a clock speed of 3.2 GHz. How many clock cycles occur per second?'
A: 3.2 GHz = 3.2 × 10^9 = 3,200,000,000 cycles per second.

CLOCK SPEED ALONE IS NOT EVERYTHING

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A processor running at 4 GHz is NOT necessarily twice as fast as one running at 2 GHz.
Different processor architectures take different numbers of cycles to execute the same
instruction.
Cache size, number of cores, pipelining, and memory speed all interact with clock speed.
A modern CPU at 3 GHz can outperform an older CPU at 5 GHz on many tasks.

4.2 Number of Cores

A core is a complete, independent processing unit within the CPU chip. A dual-core processor
has two cores; a quad-core has four; modern high-end CPUs may have 8, 16, 24, or more
cores.

Each core has its own ALU, CU, registers, and L1/L2 cache. Multiple cores can execute
different instructions simultaneously (true parallelism), significantly increasing the amount of
work done per unit time.

Core Count Name Max Simultaneous Instruction

Streams
1 Single-core 1
2 Dual-core 2
4 Quad-core 4
8 Octa-core 8
16+ Many-core 16+

MORE CORES ≠ ALWAYS FASTER

Multiple cores only help if the software is written to use multiple cores (multi-threaded).
A single-threaded program (like many simple applications) will use only one core — adding more
cores provides no benefit for that program.
A video rendering task or a modern game (designed for parallelism) benefits greatly from more
cores.
This is why software design and processor design must work together.

EXAM QUESTION TYPE — CORES

Q: 'Explain why a quad-core processor does not always perform four times faster than a single-
core processor.'
A: A quad-core processor can only achieve four times the throughput if all four cores are kept
busy simultaneously. If the software is not designed to use multiple threads (parallel execution
paths), only one core will be active. Additionally, cores share the memory bus and L3 cache,
creating bottlenecks when multiple cores try to access memory simultaneously.

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4.3 Cache Memory

Cache memory is small, extremely fast memory built directly onto (or very close to) the CPU
chip. It stores copies of frequently-used data and instructions so the CPU can access them
without waiting for the much slower main RAM.

The fundamental problem cache solves: CPUs can execute billions of operations per second,
but RAM access typically takes tens of nanoseconds — hundreds of CPU cycles of waiting.
Cache bridges this speed gap.

Cache Levels
Cache is organised into levels, each larger and slightly slower than the previous:

Level Location Typical Size Speed Purpose

L1 Cache On each core, 32 KB – 512 KB Fastest (~1–4 Holds instructions
closest to ALU per core cycles) and data currently
in use
L2 Cache On each core or 256 KB – 4 MB Fast (~4–12 Second-level
shared per core cycles) buffer; slightly
larger than L1
L3 Cache Shared between 4 MB – 64 MB Moderate (~30– Shared between
all cores total 50 cycles) cores; reduces
main memory
accesses
Main RAM On motherboard 4 GB – 128 GB Slow (~200+ Primary program
(separate chip) cycles) and data storage
during runtime

Cache Hit and Cache Miss

When the CPU needs data, it first checks L1 cache, then L2, then L3, then main RAM. The
outcome is described as:

• Cache hit: the data is found in cache — very fast access

• Cache miss: the data is not in cache — must fetch from the next level (slower)

EXAM QUESTION TYPE — CACHE

Q: 'Explain how cache memory improves processor performance.'
A: Cache is a small, fast memory built onto or very close to the CPU. It stores copies of
frequently-used data and instructions. When the CPU needs data, it checks cache first. If found
(a cache hit), the data is supplied in a few cycles instead of the hundreds of cycles needed to
access main RAM. This reduces the time the CPU spends waiting for data (wait states),
increasing the number of useful instructions executed per second.

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Q: 'Why does increasing cache size improve performance?'

A: A larger cache can hold more data and instructions simultaneously, increasing the probability
of a cache hit. Fewer cache misses mean fewer slow accesses to main RAM, so the CPU
spends less time waiting and more time executing instructions.

4.4 Pipelining
Pipelining is a technique where multiple instructions are in different stages of the FDE cycle
simultaneously, overlapping their execution. Just as a factory assembly line processes multiple
cars at different stages at the same time, a pipelined CPU processes multiple instructions
simultaneously.

Without pipelining (sequential execution):

Instruction 1: [FETCH][DECODE][EXECUTE]
Instruction 2: [FETCH][DECODE][EXECUTE]
Instruction 3: [FETCH]
[DECODE][EXECUTE]

With pipelining (overlapped execution):

Instruction 1: [FETCH][DECODE][EXECUTE]
Instruction 2: [FETCH][DECODE][EXECUTE]
Instruction 3: [FETCH][DECODE][EXECUTE]

In the pipelined example, after the pipeline is full, one instruction completes every cycle instead
of every three cycles — a theoretical 3× speedup for a 3-stage pipeline.

PIPELINE HAZARDS — WHAT LIMITS PIPELINING

Data hazard: Instruction 2 needs the result of Instruction 1, which isn't finished yet. The pipeline
must stall (wait).
Control hazard (branch): A branch instruction changes the PC. Instructions already fetched into
the pipeline may be wrong — they must be discarded (pipeline flush).
Structural hazard: Two instructions need the same hardware resource simultaneously.
Modern CPUs use branch prediction and out-of-order execution to minimise these hazards.

EXAM QUESTION TYPE — PIPELINING

Q: 'Explain what is meant by pipelining and how it improves processor performance.'
A: Pipelining is a technique in which multiple instructions are processed simultaneously, each at
a different stage of the fetch-decode-execute cycle. While one instruction is being executed, the
next is being decoded, and the one after that is being fetched. This overlapping means that, once
the pipeline is full, the CPU can complete approximately one instruction per clock cycle rather

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than one instruction every three cycles, increasing throughput significantly.

Q: 'Give one reason why pipelining does not always provide the expected performance
improvement.'
A: Branch instructions cause problems because the CPU may have fetched the wrong
instructions into the pipeline. When the branch is executed, the incorrectly-fetched instructions
must be discarded (pipeline flush), wasting cycles. This is called a branch hazard or control
hazard.

4.5 Performance Factors — Comparison Table

Factor What It Affects How Increasing It Limitation
Helps
Clock Speed Cycles per second More cycles → more Heat/power;
instructions per second diminishing returns
above ~5 GHz
Core Count Parallel execution More tasks done Only helps if software
streams simultaneously is multi-threaded
Cache Size Data availability on- More cache hits → Large caches are
chip fewer slow RAM expensive and take
accesses chip space
Pipelining Instruction throughput Multiple instructions Branch/data hazards
overlap → ~1 cause pipeline
instruction per cycle stalls/flushes

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5. Memory and Storage

Memory and storage in a computer system exist in a hierarchy. The higher up the hierarchy, the
faster and more expensive per byte — but also smaller in capacity. The lower down, the slower
and cheaper — but larger in capacity. The CPU works with the hierarchy to keep frequently-
used data as close (and fast) as possible.

Level Type Speed Size Volatile? Example

1 — Fastest CPU < 1 cycle Bytes to KB Yes ACC, PC,
Registers MAR
2 L1 Cache 1–4 cycles 32–512 KB Yes On-chip L1
3 L2/L3 Cache 4–50 cycles 256 KB–64 Yes On-chip/near-
MB chip
4 Main RAM ~200 cycles 4–128 GB Yes DDR5 RAM
5 SSD microseconds 256 GB–8 TB No NVMe SSD
6 — Slowest HDD/Optical/ milliseconds Hundreds GB- No HDD, Blu-ray,
Tape TB tape

VOLATILE VS NON-VOLATILE
VOLATILE memory loses all data when power is removed. Examples: all RAM, all cache, all
registers.
NON-VOLATILE memory retains data without power. Examples: HDD, SSD, optical discs, USB
drives, ROM.
This is why you save files to storage — not to RAM.

5.1 Main Memory — RAM and ROM

RAM — Random Access Memory

RAM is the main working memory of the computer. It holds the operating system, applications
currently running, and data being actively used. 'Random access' means any location can be
read or written in the same amount of time regardless of where it is.

• Volatile — all contents lost when power is removed

• Read/write — both reading and writing are possible
• Much faster than secondary storage but much slower than cache
• Current standard: DDR5 SDRAM for desktop/laptop systems

DRAM vs SRAM

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Type Full Name Storage Speed Cost Use

Mechanism
DRAM Dynamic RAM Capacitor Slower Cheaper Main RAM
(needs
constant
refreshing)
SRAM Static RAM Flip-flop circuit Faster Much more CPU Cache
(no refresh expensive
needed)

ROM — Read Only Memory

ROM is non-volatile memory that retains its contents without power. It can be read but not
(easily) written to during normal operation. ROM is used for firmware — software permanently
embedded in hardware.

• Non-volatile — contents survive power-off

• Typically read-only during normal operation (some types can be reprogrammed in
special circumstances)
• Used to store the BIOS/UEFI firmware that initialises the computer on startup

EXAM QUESTION TYPE — RAM VS ROM

Q: 'Give two differences between RAM and ROM.'
A: (1) RAM is volatile (loses data when power is removed); ROM is non-volatile (retains data
without power). (2) RAM is read/write (can be both read and written to); ROM is read-only during
normal operation. (3) RAM holds programs currently running; ROM holds firmware like the BIOS
that runs at startup.

5.2 Virtual Memory

Virtual memory is a memory management technique that uses a section of the secondary
storage (hard drive or SSD) as an extension of RAM. When RAM is full, the OS moves some of
its contents (called pages) to a special area on the storage device called the swap file or page
file.

This allows programs to run even when they need more memory than the physical RAM
installed. The OS maintains a page table mapping virtual addresses (what programs see) to
physical addresses (where data actually is).

• Advantage: allows more programs to run simultaneously than RAM alone would permit
• Disadvantage: significantly slower than real RAM — reading/writing to a hard drive or
even an SSD is orders of magnitude slower than RAM
• Excessive use of virtual memory (called 'thrashing') causes severe slowdowns

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EXAM QUESTION TYPE — VIRTUAL MEMORY

Q: 'Describe what is meant by virtual memory and explain one disadvantage of using it.'
A: Virtual memory is a technique where part of the secondary storage (e.g. HDD or SSD) is used
as an extension of RAM. When RAM is full, the operating system moves some data to the virtual
memory area on storage to free up RAM for active processes. A disadvantage is that accessing
secondary storage is much slower than accessing RAM (milliseconds vs nanoseconds), so
programs run significantly slower when virtual memory is heavily used.

5.3 Secondary Storage Technologies

Secondary storage provides large-capacity, non-volatile storage for programs, files, and data.
Three main technologies are used, each with different characteristics.

Magnetic Storage (Hard Disk Drive — HDD)

HDDs store data as magnetic patterns on rotating metal platters coated with a ferromagnetic
material. A read/write head on a moving arm reads and writes data by detecting or changing the
magnetic orientation of tiny regions (bits) on the platter.

• Non-volatile — magnetic patterns persist without power

• Large capacity — consumer HDDs range from 1 TB to 20+ TB
• Relatively slow — mechanical movement (spinning platters, moving head arm) limits
speed; typical read/write speeds: 80–200 MB/s
• Fragile — mechanical parts make HDDs susceptible to physical shock
• Access time depends on: seek time (head movement) + rotational latency (platter
rotation) + transfer time

HOW A HARD DRIVE WORKS — TEXTBOOK DETAIL

Platters spin at 5,400 or 7,200 RPM (revolutions per minute) — some server drives at 10,000–
15,000 RPM.
The read/write head 'flies' nanometres above the platter surface on a cushion of air.
Data is organised in concentric circular tracks, subdivided into sectors (typically 512 bytes or 4
KB each).
The head arm moves across tracks (seek); the platter rotates the desired sector under the head
(rotational latency).
Both movements take milliseconds — slow compared to nanosecond RAM access.

Solid State Drive (SSD)

SSDs store data as electrical charges in NAND flash memory cells — arrays of transistors that
retain their state without power. There are no moving parts whatsoever.

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• Non-volatile — flash memory retains data without power

• Much faster than HDD — typical speeds: 500 MB/s (SATA SSD) to 7,000+ MB/s (NVMe
SSD)
• Silent and shock-resistant — no moving parts
• More expensive per GB than HDD — but prices have fallen dramatically
• Limited write cycles — each cell can only be written a finite number of times (typically
1,000–100,000 cycles depending on type), though modern drives last many years in
typical use

Factor HDD SSD

Speed 80–200 MB/s 500–7,000+ MB/s
Capacity 1–20+ TB 256 GB–8 TB (consumer)
Cost/GB Cheaper (~£0.02/GB) More expensive (~£0.07/GB)
Durability Fragile (moving parts) Robust (no moving parts)
Noise Audible spinning/clicking Silent
Power Higher Lower
Lifespan 3–5 years average 5–10 years average

Optical Storage
Optical storage uses a laser to read data from (and in writable formats, write data to) a disc. A
laser beam is reflected differently by 'pits' (burned/pressed indentations) and 'lands' (flat areas)
on the disc surface — these differences are decoded as 0s and 1s.

Format Capacity Laser Type

CD 700 MB Infrared (780 nm) ROM, R (write-once),
RW (rewritable)
DVD 4.7 GB / 8.5 GB dual- Red (650 nm) ROM, R, RW
layer
Blu-ray 25 GB / 50 GB dual- Blue-violet (405 nm) ROM, R, RE
layer (rewritable)

Shorter laser wavelengths can focus on smaller pits, allowing more data to be packed onto the
same disc size. This is why Blu-ray (blue laser) holds far more than CD (infrared laser).

EXAM QUESTION TYPE — STORAGE TECHNOLOGIES

Q: 'Give two advantages of SSD over HDD for use in a laptop.'
A: (1) SSD has no moving parts, making it more resistant to damage from physical shocks
(important in a portable device). (2) SSD is much faster, reducing load times and improving
responsiveness. (3) SSD uses less power, extending battery life.

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Q: 'Explain why Blu-ray discs can store more data than DVDs.'
A: Blu-ray uses a blue-violet laser with a shorter wavelength (405 nm) than the red laser used in
DVDs (650 nm). A shorter wavelength can be focused on a smaller spot, allowing pits to be
made smaller and packed more closely together, increasing storage capacity.

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6. Input and Output Devices

Input devices allow data to enter the computer system. Output devices allow the computer to
communicate results to the user or the environment. Many modern devices are both
(touchscreens, network interfaces).

6.1 Input Devices

Device Type of Input How It Works Typical Use
Keyboard Text/commands Electrical contacts General text entry
close when key
pressed; scancode
sent to CPU
Mouse Pointer movement Optical sensor tracks GUI navigation
movement; buttons
detected electrically
Touchscreen Touch position Capacitive: finger Smartphones, tablets
disturbs electric field;
resistive: pressure
Scanner Image/document CCD/CIS sensor Digitising physical
captures reflected light documents
line by line
Microphone Sound Diaphragm vibration → Voice input, recording
electrical signal →
ADC → digital audio
Webcam/Camera Image/video CMOS/CCD sensor Video calls,
converts light to photography
electrical charges
Barcode Reader Barcode data Laser/LED reflects off Retail, inventory
barcode; light/dark
patterns decoded
QR Code Reader 2D code data Camera captures 2D Payments, links
matrix code; software
decodes pattern
Graphics Tablet Drawing input Electromagnetic or Digital art, design
pressure-sensitive grid
detects stylus position
Sensor (generic) Physical data Converts physical IoT, monitoring
property (temperature,
pressure) to electrical
signal → ADC

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6.2 Output Devices

Device Output Type How It Works Typical Use
Monitor (LCD) Visual Backlight + liquid General display
crystals block/pass
light per pixel; colour
from RGB filters
Monitor (OLED) Visual Each pixel is a light- Phones, premium
emitting organic displays
compound — no
backlight needed
Printer (inkjet) Hard copy Tiny nozzles spray Home/office
droplets of ink onto documents, photos
paper
Printer (laser) Hard copy Laser charges drum; High-volume office
toner adheres to printing
charged areas; heat
fuses toner to paper
3D Printer Physical object Deposits material Prototyping,
(plastic, resin) layer by manufacturing
layer from digital model
Speakers Sound Digital audio → DAC → Audio output
amplifier → vibrating
cone → sound waves
Projector Visual Lamp/laser projects Presentations, cinema
image from LCD/DLP
chip onto surface
Actuator Physical movement Receives electrical Robotics, automation
signal; produces
mechanical motion
(motor, valve, etc.)

EXAM QUESTION TYPE — INPUT/OUTPUT DEVICES

Q: 'A supermarket uses a barcode scanner at the checkout. State two other input devices and
one output device that the checkout system might use.'
A: Input: Touchscreen (for staff to enter information), keyboard (for entering codes manually).
Output: Receipt printer / display screen.

Q: 'Describe how a laser printer produces a printed page.'

A: A laser beam is directed across a rotating drum coated with a photosensitive material, creating
a pattern of electrical charge corresponding to the image. Toner (fine powder) is attracted to the
charged areas. The drum rolls across paper and the toner transfers. Heat rollers (the fuser unit)
permanently bond the toner to the paper.

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6.3 Analogue vs Digital — ADC and DAC

The real world produces analogue signals — continuously varying values (temperature, sound,
light). Computers work with digital signals — discrete binary values. Converting between them
requires:

• ADC (Analogue to Digital Converter): converts continuous analogue signals into

discrete digital values. Used by microphones, sensors, cameras.
• DAC (Digital to Analogue Converter): converts digital values back into analogue
signals. Used by speakers, audio outputs, analogue displays.

Sound recording: Microphone (analogue) → ADC → Digital file → DAC →

Speaker (analogue)

EXAM QUESTION TYPE — ADC/DAC

Q: 'A temperature sensor measures the temperature outside a building. Explain why an ADC is
needed to connect this sensor to a computer.'
A: The temperature sensor produces an analogue signal — a continuously varying voltage that
represents temperature. Computers can only process digital (binary) signals. The ADC converts
the continuously-varying analogue signal into a stream of discrete binary values that the
computer can store and process.

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7. Buying a Computer — Applying Performance

Knowledge
The textbook includes a section on choosing a computer, which directly tests your ability to
apply the performance factors from Section 4 to real-world decisions. This is a common exam
question format.

Specification What It Means More Is Better When... Typical Value (2024)

Processor (CPU) Clock speed × cores = Running demanding Intel i7/i9 or AMD
processing power software, multitasking Ryzen 7/9; 3–5 GHz;
8–16 cores
RAM Working memory for Running many apps 16 GB minimum; 32
running programs simultaneously; video GB for demanding
editing tasks
Storage (SSD) Speed and capacity of Fast boot times, large 512 GB NVMe SSD
file storage files minimum; 1–2 TB
preferred
Cache On-chip fast memory Always — larger cache L3: 8–32 MB is typical
always helps
GPU Graphics processing Gaming, 3D modelling, NVIDIA RTX 4060–
for display/gaming video rendering, AI 4090 for gaming
tasks
Display Resolution and refresh Creative work (high 1920×1080 @ 144 Hz
rate resolution), gaming or 2560×1440 @ 165
(high refresh rate) Hz
Battery (laptop) How long without Portability and travel 40–100 Wh; 8–15
power hours claimed

EXAM QUESTION TYPE — BUYING A COMPUTER

Q: 'A graphic designer needs a new computer. Suggest and justify three specifications they
should prioritise.'
A: (1) Large RAM (32 GB+) — graphic design software loads large image files and multiple
layers into RAM; insufficient RAM causes slow performance or crashing. (2) Fast multi-core
processor — rendering complex images uses all available CPU cores; a faster clock speed
reduces render time. (3) High-resolution display — graphic designers need to see fine details
accurately; a 4K display provides more pixels for detailed work.

Q: 'A student is choosing between an HDD and an SSD for their laptop. Give two reasons why an
SSD would be a better choice.'
A: (1) No moving parts — more resistant to physical shock, important for a portable device that
may be dropped. (2) Faster read/write speeds — reduces boot times and application load times
significantly.

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8. Chapter Questions — Fully Worked Answers

The following questions are drawn from the end-of-chapter exercises in the textbook. These
exact question styles and topics appear in examinations.

Q1. Describe the role of each register in the FDE cycle: PC, MAR,
MDR, CIR
PC — Program Counter
• Stores the memory address of the NEXT instruction to be fetched
• Automatically incremented after each fetch
• Updated to branch address when a jump/branch instruction executes

MAR — Memory Address Register

• Holds the memory address that is about to be read from or written to
• During fetch: receives the PC value (address of next instruction)
• During execute: holds data address for LOAD/STORE instructions
• Connected to the address bus — its contents are sent to memory along the address bus

MDR — Memory Data Register

• Temporary buffer between the CPU and main memory
• During read: holds data just retrieved from memory before it goes to CIR or other
register
• During write: holds data to be written to memory

CIR — Current Instruction Register

• Holds the instruction currently being decoded and executed
• The Control Unit reads from the CIR to determine what action to take
• Holds its value throughout the decode and execute stages

Q2. Explain the complete sequence of events in the FDE cycle for one
instruction
Using a LOAD instruction as the example (LOAD R1, [150] — load data from address 150 into
register R1):

Step 1: FETCH: PC contains, say, 200 (address of this instruction). PC value copied to
MAR.

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Step 2: FETCH: Address 200 sent along address bus to main memory. READ signal on
control bus.
Step 3: FETCH: Memory returns the LOAD instruction along the data bus → stored in
MDR.
Step 4: FETCH: Instruction copied from MDR to CIR. PC incremented to 201.
Step 5: DECODE: Control Unit reads CIR. Identifies: opcode = LOAD, operand = [150].
Step 6: EXECUTE: CU places data address 150 into MAR.
Step 7: EXECUTE: Address 150 sent along address bus to memory. READ signal sent.
Step 8: EXECUTE: Memory returns data at address 150 along data bus → stored in MDR.
Step 9: EXECUTE: Data copied from MDR into register R1.
Step 10: Cycle repeats: PC now holds 201, so next instruction is fetched from address 201.

Q3. Explain why the clock speed alone is not a reliable measure of
processor performance
• Different processor architectures take different numbers of clock cycles to execute the
same instruction — a faster clock on a less efficient architecture may still be slower
overall
• The number of cores matters: a 3 GHz quad-core may outperform a 4 GHz single-core
on multi-threaded tasks
• Cache size affects how often the processor must wait for slow RAM — a larger cache
reduces stalls
• Pipelining efficiency varies — a pipeline with frequent hazards stalls more and achieves
less work per cycle
• Memory bandwidth limits performance — a fast CPU waiting for slow RAM is not
efficient
• Instruction set efficiency differs — RISC architectures complete more instructions per
cycle than CISC on equivalent workloads

Q4. Compare magnetic hard disk drives (HDD) and solid-state drives
(SSD)
Criterion HDD SSD
Storage mechanism Magnetic patterns on rotating Electrical charge in NAND flash
platters cells
Speed 80–200 MB/s (limited by 500–7,000+ MB/s (purely
mechanical movement) electronic)
Moving parts Yes — motor, platters, actuator None
arm, read/write head
Physical shock Sensitive — mechanical shock Robust — no damage from
can cause head crash and data typical drops
loss

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Criterion HDD SSD

Power consumption Higher — motor must spin Lower — significant battery
platters continuously saving in laptops
Noise Audible spinning/clicking sounds Completely silent
Capacity per £ Much cheaper — around £0.02– More expensive — around
0.03/GB £0.06–0.10/GB
Lifespan concern Mechanical wear on moving Limited write cycles per cell
parts (wear levelling used)
Data recovery Possible from damaged platters Harder to recover from failed
in labs flash chips

Q5. Describe how cache memory works and explain why it improves
performance
• Cache is small, extremely fast SRAM memory built onto or very close to the CPU
• It stores copies of recently-used or frequently-used data and instructions
• When the CPU needs data, it checks L1 cache first, then L2, then L3, then main RAM
• If found in cache (cache hit): data supplied in 1–50 cycles
• If not found (cache miss): data fetched from main RAM (~200+ cycles) and a copy
placed in cache for future use
• As programs tend to access the same data repeatedly (locality of reference), cache hit
rates are typically 95%+ in practice
• The overall effect: the average memory access time is dramatically reduced, keeping the
CPU supplied with data and minimising idle wait time

LOCALITY OF REFERENCE — WHY CACHE WORKS

Temporal locality: data that was recently used is likely to be used again soon (loops access the
same variables repeatedly).
Spatial locality: data near recently-accessed data is likely to be needed soon (arrays are stored
contiguously).
Cache exploits both types of locality by fetching entire 'cache lines' (typically 64 bytes) at once.

Q6. Give examples of input and output devices for specific scenarios
Scenario Suitable Input Suitable Output Justification
Device(s) Device(s)
Hospital patient Temperature sensor, Display screen, Sensors provide
monitoring blood pressure sensor, alarm/speaker continuous analogue
pulse oximeter data converted via
ADC; screen/alarm
alerts staff
Supermarket self- Barcode scanner, Screen, receipt printer, Multiple input types for

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Scenario Suitable Input Suitable Output Justification

Device(s) Device(s)
checkout weight sensor, speaker product ID, payment,
touchscreen, card user interaction
reader
Home security system Motion sensor, camera, Siren/speaker, LED Sensors detect
door sensor light, notification to intrusion; outputs alert
phone occupants
Factory robot arm Position sensor, force Actuator motors, status Sensors provide
sensor, vision camera display feedback; actuators
control physical
movement
Interactive museum Touchscreen, Screen, projector, Multiple intuitive input
exhibit microphone, motion speakers methods; rich audio-
sensor visual output

Q7. Explain what pipelining is and describe one situation where it fails
to give the expected speedup
Definition: Pipelining is a technique in which multiple instructions are processed simultaneously,
each at a different stage of the fetch-decode-execute cycle. While instruction N is being
executed, instruction N+1 is being decoded, and instruction N+2 is being fetched. This overlap
allows the processor to theoretically complete one instruction per clock cycle rather than one
instruction every three cycles.

Situation where pipelining fails — Branch Hazard:

• When a conditional branch instruction is encountered (e.g. IF...THEN), the next
instruction to execute depends on the branch outcome
• But the CPU has already fetched and begun decoding the next sequential instructions
into the pipeline
• When the branch condition is evaluated during execute, it may determine that execution
should jump to a different address
• The instructions already in the pipeline are now wrong — they must be discarded (a
'pipeline flush')
• The pipeline must be refilled from the new address, causing several wasted cycles
• Modern CPUs use 'branch prediction' to guess the branch outcome and pre-fetch
accordingly, but mispredictions still cause flushes

Q8. A student claims a computer with 16 GB RAM will always

outperform one with 8 GB. Evaluate this claim
• The claim is PARTIALLY true but oversimplified

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• If the 8 GB system runs out of RAM and uses virtual memory heavily while the 16 GB
system does not, the 16 GB system will be significantly faster for memory-intensive
tasks
• However, if neither system uses more than 8 GB, the extra RAM provides no
performance benefit
• For light tasks (browsing, word processing), 8 GB is sufficient and the two systems will
perform identically
• For heavy tasks (video editing, running multiple virtual machines, large games), 16 GB
provides meaningful benefit
• Other factors dominate: a 16 GB system with a slow HDD and an old dual-core CPU
may be slower than an 8 GB system with an NVMe SSD and a modern 8-core CPU
• Conclusion: More RAM helps if RAM was the limiting factor; otherwise, clock speed,
cores, storage speed, and cache are more important

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9. Exam Preparation — Chapter 5 Priority Summary

Based on the attached exam paper (Chapters 1–4) and the structure of Chapter 5, these are the
highest-priority topics for exam success:

PRIORITY 1 — FDE CYCLE REGISTER DESCRIPTIONS

You MUST be able to name and describe every register (PC, MAR, MDR, CIR, ACC) and trace
exactly which data moves where in each stage.
Practice writing out the full FDE cycle using register names for at least three different instruction
types: a fetch, a LOAD, and a BRANCH.
Common error: saying 'data goes to memory' without specifying via MAR/MDR and the
address/data buses.

PRIORITY 2 — FACTORS AFFECTING PERFORMANCE

Expect a multi-mark question asking you to explain TWO or THREE performance factors.
For each factor, give: (1) what it is, (2) how increasing it improves performance, (3) a limitation or
trade-off.
Clock speed, cores, cache, and pipelining must all be explained with specific detail — not vague
statements.

PRIORITY 3 — STORAGE COMPARISON (HDD VS SSD)

Know the comparison table. Exam questions often give a scenario ('a photographer storing large
RAW files') and ask you to recommend and justify.
Always justify based on the scenario — a photographer needs large capacity (HDD advantage)
but also fast access (SSD advantage).

PRIORITY 4 — INPUT/OUTPUT DEVICE SCENARIOS

Given a real-world system (hospital, factory, supermarket), be able to identify appropriate I/O
devices AND explain why each is suitable.
Remember to explain how the device works, not just name it.
Include ADC/DAC when relevant (sensor input, speaker output).

PRIORITY 5 — VIRTUAL MEMORY AND CACHE

Virtual memory: what it is, how it works (swap file/page file on secondary storage), and why it's
slow.
Cache: hierarchy (L1/L2/L3), hit vs miss, why locality of reference makes it effective.
These are frequently worth 3–4 marks each — worth writing full paragraph-style answers in the
exam.

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THREE THINGS THAT LOSE MOST MARKS IN CHAPTER 5

1. Not using register names in FDE cycle answers — saying 'it goes to memory' instead of 'MAR
value is sent along the address bus to memory'.
2. Not giving a limitation alongside each performance factor — examiners reward balanced
answers.
3. Confusing RAM and storage — RAM is volatile working memory; secondary storage is non-
volatile long-term storage. Mixing these up loses marks every time.

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