EMBEDDED SYSTEMS

MODULE II –
COMMUNICATION DEVICES
Anoop Thomas
Bus in Embedded Systems
◻ A data connection between two or more devices connected to the computer
◻ Used to connect major components

CPU

DMA {Direct memory access}

Memory modules

Peripheral devices, etc.

◻ Can be synchronous or asynchronous

Synchronous bus
◻ Transmitter and receivers are synchronized with clock.
◻ Data bits are transmitted with synchronization of clock.
◻ Devices should be at same speed.
◻ Character is received at constant Rate.
◻ Data transfer takes place in block.
◻ Used in high speed transmission.
Asynchronous bus
◻ Transmitters and receivers are not synchronized by clock.

◻ Connect many devices with varying speeds

◻ Character may arrive at any rate at the receiver.

◻ Data transfer is character oriented.

◻ Start and stop bits are required to establish communication of each character.

◻ Used in low speed transmission.

Different Buses
◻ Buses that work in sync with CPU and system clock are called the
local buses or system buses.
◻ Buses that work asynchronously with the CPU are called the
expansion buses.
◻ The memory bus is a local bus while the ISA bus is an expansion
bus.
What Does a Bus carry?
◻ Electrical Power.

◻ Control Signals.

◻ Memory Address.

◻ Data.
Bus Communication for networking
◻ Bus communication simplifies the number of connections
and provides a common way (protocol) of connecting
different or same type of I/O devices
IO Bus
◻ I/O devices communicate with the processor through an
I/O bus, which is separate from the memory bus that the
processor uses to communicate with the memory system.
◻ A bus has a fixed bandwidth that must be shared by all of
the devices on the bus.
Serial Bus
◻ A serial bus has very few lines and the number of lines as
per the protocol.
◻ A wide range of I/O devices without having to
implement a specific interface for each I/O device.
◻ All can communicate through a common serial bus.
Parallel Bus
◻ Using a parallel I/O bus allows a computer or controller
or embedded system to interface with number of internal
systems at very short distances without having to
implement a specific interface for each I/O device.
 Local Bus
◻ A set of parallel
conductors, which allow
devices attached to it to
communicate with the
CPU.
◻ The bus consists of three
main parts:
Control lines, Address
lines, Data lines
Bus Communication Advantages
◻ It is easy to connect a device to the network.
◻ It is cheaper than other network options.
◻ The failure of one station does not affect the rest of the network.
◻ No hubs or switches are required.
◻ Extensions can be made to the network.
◻ Multiple nodes can be installed without difficulty.
Serial communication
 Serial bus protocols
◻ I2C Bus – Inter-Integrated Circuit

◻ CAN Bus – Controller Area Network

◻ USB Bus – Universal Serial Bus

Parallel communication
 Parallel communication standards
◻ ISA bus – Industry Standard Architecture

◻ EISA bus – Extended Industry Standard Architecture

◻ PCI bus – Peripheral Component Interconnect

◻ PCI-X bus– Peripheral Component Interconnect

eXtended
Serial Communication Standards and
Devices
◻ Simplex, half-duplex, full-duplex
◻ For parallel data transfer, data rate is bytes/sec & for
serial data communication it is bits/sec
◻ Synchronous, Asynchronous & Iso-synchronous
communication
Iso-synchronous Synchronous communication special
case when bits of a full frame are sent in the maximum
time interval, which can be variable.
Serial Communication Standards and
Devices
◻ UART - Universal Asynchronous Receiver/Transmitter

◻ HDLC - High-level Data Link Control

◻ SPI - Serial Peripheral Interface

Bit rate & Baud rate
◻ Bit Rate is how many data bits are transmitted per second.
A baud Rate is the number of times per second a signal in a
communications channel changes.
For example:
A figure of 2400 bits per second means 2400 zeros or ones can
be transmitted in one second, hence the abbreviation “bps”.
A 2400 baud rate means that the channel can change states up to
2400 times per second. Change state refers to the actual state of
the connection (such as voltage, frequency, or phase level).
bps = baud per second x the number of bit per baud
Universal Asynchronous Receiver/
Transmitter
◻ UART uses only two wires to transmit data between devices.
◻ The transmitting UART converts parallel data into serial
form.
◻ Receiving UART, converts the serial data into parallel data.
◻ UARTs transmit data asynchronously.
◻ UART can operate in half duplex mode or full duplex mode,
depending upon the number of buffers used.
Universal Asynchronous Receiver/
Transmitter
◻ UART reads the incoming bits at a specific frequency
known as the baud rate.

◻ Baud rate is a measure of the speed of data

transfer, expressed in bits per second (bps).

◻ Both UARTs must operate at about the same baud rate.

UART
Data frame of UART
Data frame of UART
Configured to transmit and receive
◻ Both UARTs must also must be configured to transmit
and receive the same data packet structure.
Steps of UART transmission
1. The transmitting UART receives data in parallel from
the data bus:
Steps of UART transmission…
2. The transmitting UART adds the start bit, parity bit, and
the stop bit(s) to the data frame:
Steps of UART transmission…
3. The entire packet is sent serially from the transmitting
UART to the receiving UART. The receiving UART
samples the data line at the pre-configured baud rate:
Steps of UART transmission…
4. The receiving UART discards the start bit, parity bit,
and stop bit from the data frame:
Steps of UART transmission…
5. The receiving UART converts the serial data back into
parallel and transfers it to the data bus on the receiving
end:
How UART Works !
◻ The UART that is going to transmit data receives the data from a
data bus.
◻ The data bus is used to send data to the UART by another device
like a CPU, memory, or microcontroller.
◻ Data is transferred from the data bus to the transmitting UART
in parallel form.
◻ After the transmitting UART gets the parallel data from the data
bus, it adds a start bit, a parity bit, and a stop bit, creating the
data packet.
How UART Works !
◻ Next, the data packet is output serially, bit by bit at the Tx pin.
◻ The receiving UART reads the data packet bit by bit at its Rx pin.
◻ The receiving UART then converts the data back into parallel
form and removes the start bit, parity bit, and stop bits.
◻ Finally, the receiving UART transfers the data packet in parallel to
the data bus on the receiving end
Advantages of UART
◻ Only uses two wires
◻ No clock signal is necessary
◻ Has a parity bit to allow for error checking
◻ The structure of the data packet can be changed as long
as both sides are set up for it
◻ Well documented and widely used method
Disadvantages of UART
◻ The size of the data frame is limited to a maximum of 9
bits
◻ Doesn’t support multiple slave or multiple master
systems
◻ The baud rates of each UART must be within 10% of
each other
HDLC (High-Level Data Link
Control)
HDLC features
1. It is most widely accepted protocol. It offers a high
level of flexibility, adaptability, reliability and
efficiency.
2. Full duplex communication is possible.
3. It is Bit-oriented protocol i.e. use bits to stuff flags
occurring in data.
4. Flow control - adjust window size based on receiver
capability.
HDLC Overview
◻ Defines three types of stations
Primary, Secondary, Combined
◻ HDLC Configurations
Unbalanced, Balanced, Symmetrical
◻ Defines three types of data transfer mode
Normal Response mode [NRM]
Asynchronous Response mode [ARM]
Asynchronous Balanced mode [ABM]
◻ Three types of frames
Unnumbered or U-frame, Information or I-frame, Supervisory or S-frame
HDLC – Station Types
Nodes within a network running HDLC are called stations. HDLC supports three types of
stations for data link control:
◻ Primary stations—Responsible for controlling the secondary and combined stations on the
link. Depending on the HDLC mode, the primary station is responsible for issuing
acknowledgement packets to allow data transmission from secondary stations.
◻ Secondary stations—Controlled by the primary station. Under normal circumstances,
secondary stations cannot control data transmission across the link with the primary station,
are active only when requested by the primary station, and can respond to the primary
station only (not to other secondary stations). All secondary station frames are response
frames.
◻ Combined stations—A combination of primary and secondary stations. On an HDLC link,
all combined stations can send and receive commands and responses without any
permission from any other stations on the link and cannot be controlled by any other station
HDLC - Configuration
◻ HDLC also defines three types of configurations for the
three types of stations.
◻ The word configuration refers to the relationship between
the hardware devices on a link. Following are the three
configurations defined by HDLC:
Unbalanced Configuration
Balanced Configuration
Symmetrical Configuration
Unbalanced Configuration
Balanced Configuration
Symmetrical Configuration
◻ Not widely in use today.
HDLC Operational Modes
◻ Normal Response Mode (NRM)
Just an acknowledgment of a frame. NRM is only used within an
unbalanced configuration.
◻ Asynchronous Response Mode (ARM)
Contain data or control information regarding the status of the
secondary station. Asynchronous, the secondary station must wait
until it detects and idle channel before it can transfer any frames.
◻ Asynchronous Balanced Mode (ABM)
Not used widely today.
HDLC Operational Modes
◻ Normal Response Mode (NRM)
The primary station on the HDLC link initiates all information
transfers with secondary stations.
A secondary station on the link can transmit a response of one or more
information frames only when it receives explicit permission from the
primary station.
When the last frame is transmitted, the secondary station must wait
for explicit permission before it can transmit more frames.
NRM is used most widely for point-to-multipoint links, in which a
single primary station controls many secondary stations.
HDLC Operational Modes
◻ Asynchronous Response Mode (ARM)
The secondary station can transmit either data or control traffic at any time,
without explicit permission from the primary station.
The primary station is responsible for error recovery and link setup, but the
secondary station can transmit information at any time.
ARM is used most commonly with point-to-point links, because it reduces the
overhead on the link by eliminating the need for control packets.
◻ Asynchronous Balance Mode (ABM)
All stations are combined stations.
Because no other station can control a combined station, all stations can transmit
information without explicit permission from any other station.
ABM is not a widely used HDLC mode
HDLC frame structure

FCS – Frame Check Sequence

Field
Size of different fields
Field Name Size(in bits)
◻ Flag Field 8 bits
◻ Address Field 8 bits
◻ Control Field 8 or 16 bits
◻ Information Field or data Variable; Not used in
some frames
◻ Frame Check Sequence(FCS ) 16 or 32 bits

◻ Closing Flag Field 8 bits

HDLC – Control field format
Three different classes of frames used in
HDLC
◻ Unnumbered frames, used for exchanging session
management and control information between communicating
devices.
◻ Information frames, which carry actual information. If the
first bit in control field is 0 it is identified as I-frame.
◻ Supervisory frames, which are used for error and flow
control purposes and hence contain send and receive sequence
numbers. If first two bits of control field are 1 and 0 it is
identified as S-frame.
HDLC – Control field format
Poll/Final Bit (P/F)
◻ Recognized when it is set to 1, if set to 0 it is ignored.

◻ Provide dialogue between the primary station and

secondary station.
Frame check Sequence field
◻ 16-bit or 32-bit cyclic redundancy check bits.

◻ Used for error detection.

HDLC – Control field format
S-Frame
◻ Four types of S-frames are possible corresponding to four values of
‘S’
◻ SS=00 corresponds to Receive Ready (RR) frames.
◻ SS=01 Reject (REJ) is used to request the retransmission of
frames.
◻ SS=10 corresponds to Receive not Ready (NRN) frame and is
used for flow control.
◻ SS=11 Selective Reject (SREJ) is used by a station to request
retransmission of specific frames.
HDLC – Control field format
Unnumbered Format Commands and responses
(U-Frame)
◻ Used to extend the number of data link control functions.

◻ Frames have 5 modifier bits,

Which allow for up to 32 additional commands and 32

additional response functions.
13 command functions and 8 response functions are there.
 SPI - Serial Peripheral Interface

SD card modules, RFID card reader modules, and 2.4 GHz wireless transmitter/receivers all use SPI to
communicate with microcontrollers.
◻ SCLK — Serial
Clock
◻ MOSI — Master
Output, Slave
Input
◻ MISO — Master
Input, Slave
Output
◻ SS/CS — Slave
SPI Bus
SPI - Data Transmission
Shift register
• Size – multiple of 8
• Data in & out
• LS/MS bit configuration register
Multislave SPI configuration
Daisy-Chain Method
SPI – 4 different SPI modes
◻ Depending on SCLK edge used for shifting:
SPI mode SCLK starting edge SCLK closing edge

0 Sampling data at rising edge Transmit new data at falling edge

1 Transmit new data at rising edge Sampling data at falling edge

2 Sampling data at falling edge Transmit new data at rising edge

3 Transmit new data at falling edge Sampling data at rising edge

Advantages of SPI
◻ Fast for point-to-point connections.
◻ Easily allows streaming/constant data inflow.
◻ No complicated slave addressing system.
◻ No addressing in protocol, so it’s simple to implement.
◻ Broadly supported.
◻ Higher data transfer rate than I2C (almost twice as fast).
Disadvantages of SPI
◻ Uses four wires (I2C and UARTs use two).
◻ No acknowledgement that the data has been successfully
received (I2C has this).
◻ No form of error checking like the parity bit in UART.
◻ Only allows for a single master.
◻ Slave select/chip select makes multiple slaves more
complex.
Applications of SPI
SPI is used to talk to a variety of peripherals, such as:
◻ Sensors: Temperature, pressure, ADC, touch-screens.

◻ Control devices: audio codecs, digital potentiometers, DAC.

◻ Memory: flash and EEPROM.

◻ Real-time clocks.

◻ LCD (liquid-crystal display), sometimes even for managing

image data.
◻ Any MMC (MultiMediaCard) or SD (Secure Digital) card.
 I2C - Inter-Integrated Circuit
61

◻ Invented by Philips in the early 1982 (now NXP

Semiconductors).
◻ Three data transfer speeds such as standard (100kbps),
fast-mode (400kbps) and high-speed-mode (3.4Mbps).
◻ Supports 7-bit and 10-bit address space device and its
operation differ with low voltages.
◻ I2C is a multi-master, low-bandwidth, short distance,
serial communication bus protocol.
 I2C - Inter-Integrated Circuit
62

◻ Serial Data line

(SDA) and Serial
Clock line (SCL).
◻ Voltages -
+5/+3.3 V
◻ Slave device has a
unique address.
 Sequence of operations for communicating
63
with an 12C slave device
1) The master device pulls the clock line (SCL) of the bus to 'HIGH'
2) The master device pulls the data line (SDA) 'LOW', when the
SCL line is at logic 'HIGH' (This is the 'Start' condition for data
transfer).
3) The master device sends the address (7 bit or 10 bit wide) of the
'slave' device to which it wants to communicate, over the SDA
line. Clock pulses are generated at the SCL line for synchronising
the bit reception by the slave device. The MSB of the data is
always transmitted first. The data in the bus is valid during the
'HIGH' period, of the clock signal.
 Sequence of operations for communicating
64
with an 12C slave device
4) The master device sends the Read or Write bit (Bit value = 1 Read
operation; Bit value = 0 Write operation) according to the
requirement.
5) The master device waits for the acknowledgement bit from the
slave device whose address is sent on the bus along with the
Read/Write operation command. Slave devices connected to the
bus compares the address received with the address assigned to
them.
6) The slave device with the address requested by the master device
responds by sending an acknowledge bit (Bit value = 1) over the
SDA line
 Sequence of operations for communicating
65
with an 12C slave device
7) Upon receiving the acknowledge bit, the Master device sends the 8bit
data to the slave device over SDA line, if the requested operation is
'Write to device'. If the requested operation is 'Read from device', the
slave device sends data to the master over the SDA line.
8) The master device waits for the acknowledgement bit from the device
upon byte transfer complete i.e for a write operation and sends an
acknowledge bit to the Slave device for a read operation.
9) The master device terminates the transfer by pulling the SDA line
'HIGH' when the clock line SCL is at logic 'HIGH' (Indicating the
'STOP' condition).
 I2C – Frame
66
 I2C Basic Commands Sequence
67

◻ Start Bit Condition

◻ Stop Bit Condition
◻ Acknowledgement Condition
◻ Master to slave Write operation
◻ Read Operation Slave to Master
I2C – Start & Stop
◻ Start Condition: The SDA
line switches from a high
voltage level to a low voltage
level before the SCL line
switches from high to low.
◻ Stop Condition: The SDA
line switches from a low
voltage level to a high voltage
level after the SCL line
switches from low to high.

68
 I2C – Device Addressing
69

• Address Frame: A 7 or 10 bit sequence unique to each slave that identifies the
slave when the master wants to talk to it.
• Read/Write Bit: A single bit specifying whether the master is sending data to the
slave (low voltage level) or requesting data from it (high voltage level).
• ACK/NACK Bit: Each frame in a message is followed by an
acknowledge/no-acknowledge bit. If an address frame or data frame was
successfully received, an ACK bit is returned to the sender from the receiving
device.
 I2C – Data transfer with ACK
70

• After the master detects the ACK bit from the slave, the first data
frame is ready to be sent.
• The data frame is always 8 bits long, and sent with the most
significant bit first. Each data frame is immediately followed by an
ACK/NACK bit to verify that the frame has been received
successfully.
 Advantages of I2C
71

◻ Only uses two wires

◻ Supports multiple masters and multiple slaves
◻ ACK/NACK bit gives confirmation that each frame is
transferred successfully
◻ Hardware is less complicated than with UARTs
◻ Well known and widely used protocol
 Disadvantages of I2C
72

◻ Slower data transfer rate than SPI

◻ The size of the data frame is limited to 8 bits
◻ More complicated hardware needed to implement than
SPI
 Examples of I2Cs
73

◻ I2C-compatible devices found in embedded systems

include EEPROMs, thermal sensors, and real-time
clocks.
◻ I2C is also used as a control interface to signal
processing devices that have separate,
application-specific data interfaces.
◻ For instance, it's commonly used in multimedia
applications, where typical devices include RF tuners,
video decoders and encoders, and audio processors.
 Difference between UART, SPI &
74
I2C
Features UART SPI I2C

Full Form Universal Asynchronous Receiver/Transmitter Serial Peripheral Interface Inter-Integrated Circuit

As this is asynchronous communication, data

Max data rate limit is not
rate between two devices wanting to I2C supports 100 kbps, 400 kbps,
specified in SPI interface.
Data rate communicate should be set to equal value. 3.4 Mbps. Some variants also
Usually 10 Mbps to 20
Maximum data rate supported is about 230 supports 10 Kbps and 1 Mbps.
Mbps
Kbps to 460kbps.

Distance Lower about 50 feet Highest Higher

Type of comm. Asynchronous Synchronous Synchronous

Number of
Not Applied One One or more than One
masters
Difference between UART, SPI &
I2C
Features UART SPI I2C

No Common Clock
signal is used. Both There is common clock signal
There is one common serial clock signal
Clock the devices will use between multiple masters and
between master and slave devices.
there independent multiple slaves.
clocks.

Hardware
Lesser Less More
complexity

Each company or manufacturers have got their

own specific protocols to communicate with
It uses start and stop bits. It
peripherals. Hence one needs to read datasheet
uses ACK bit for each 8 bits of
For 8 bits of data to know read/write protocol for SPI
data which indicates whether
Protocol one start bit and one communication to be established. For example
data has been received or not.
stop bit is used. we would like SPI communication between
Figure depicts the data
microcontroller and EPROM. Here one need to
K.V. Shibu, Introduction to Embedded Systems, 2e, McGraw Hill Education communication protocol.
go through read/write operational diagram in
India, 2016 Chapter 1
the EPROM data sheet.
CAN (CONTROLLER AREA
NETWORK) BUS
Wayne Wolf, “Computers as Components: Principles of Embedded
Computing System Design”
 Automotive communication buses
77

◻ Controller Area Network (CAN) bus

Robert Bosch, medium speed (125 Kbps) & high speed (1 Mbps)
Protocol for error handling in data transmission
Safety-critical operations like ABS, airbag control, engine control,
navigation system
◻ Local Interconnect Network (LIN) bus
Single master multiple slave, low speed single wire (20 Kbps)
Mirror controls, fan controls, seat positioning controls, window
controls where response time is not critical issue
◻ Media-Oriented System Transport (MOST) bus
Audio/video equipment interfacing, European cars, point-to-point
 CAN (Controller Area Network)
78
Bus
◻ Started originally in 1983 at Robert Bosch.
◻ Protocol was officially released in 1986.
◻ First CAN controller chips, produced by Intel and
Philips, introduced in the market in the year of 1987.
◻ Designed for automotive electronics and was first used in
production cars in 1991.
◻ Uses bit-serial transmission.
CAN bus …
◻ Optical link can also be
used. The bus protocol
supports multiple masters
on the bus.
◻ Fig: Each node in the CAN
bus has its own electrical
drivers and receivers that
connect the node to the bus
in wired-AND fashion.

79
 CAN bus …
80

◻ The format of a CAN data frame

 CAN data frame
81

◻ A data frame starts with a 1 and ends with a string of seven zeroes.
(There are at least three bit fields between data frames.)
◻ First field contains the packet’s destination address and is known as the
arbitration field.
◻ The destination identifier is 11 bits long.
◻ The trailing remote transmission request (RTR) bit is set to 0 if the data
frame is used to request data from the device specified by the identifier.
◻ When RTR = 1 packet is used to write data to the destination identifier.
◻ The control field provides an identifier extension and a 4-bit length for the
data field with a 1 in between.
 CAN data frame …
82

◻ IDE A dominant single identifier extension (IDE) bit means that

a standard CAN identifier with no extension is being transmitted.
◻ r0 (value =1) Reserved bit (for possible use by future standard
amendment).
◻ DLC The 4-bit data length code (DLC) contains the number of
bytes of data being transmitted. Data–Up to 64 bits of application
data may be transmitted.
◻ CRC The 16-bit (15 bits plus delimiter) cyclic redundancy check
(CRC) contains the checksum (number of bits transmitted) of the
preceding application data for error detection.
 CAN data frame …
83

◻ Data field is from 0 to 64 bytes depending on the value given in the

control field.
◻ Cyclic redundancy check (CRC) is sent after the data field for error
detection.
◻ Acknowledge field is used to let the identifier signal whether the frame
was correctly received: the sender puts a recessive bit (1) in the ACK slot
of the acknowledge field; if the receiver detected an error, it forces the
value to a dominant (0) value.
◻ If the sender sees a 0 on the bus in the ACK slot it must retransmit.
◻ The ACK slot is followed by a single bit delimiter followed by the
end-of-frame field.
 CAN data frame …
84

◻ EOF This end-of-frame (EOF), 7-bit field marks the end of

a CAN frame (message) and disables bit stuffing, indicating a
stuffing error when dominant.
◻ When 5 bits of the same logic level occur in succession
during normal operation, a bit of the opposite logic level is
stuffed into the data.
◻ IFS This 7-bit inter-frame space (IFS) contains the time
required by the controller to move a correctly received frame
to its proper position in a message buffer area.
 CAN bus …
85

CAN Versions
NOMENCLATUR STANDARD MAX. IDENTIFIER
E SIGNALING
RATE

Low–Speed CAN ISO 11519 125 kbps 11-bit

CAN 2.0A ISO 11898:1993 1 Mbps 11-bit

CAN 2.0B ISO 11898:1995 1 Mbps 29-bit

 CAN bus …
86

5 Different message types are:

◻ Data Frame: It consists of arbitrary field, data field, crc field and
the acknowledge fields.
◻ Remote Frame: It requests for transmission of data from another
node. Here the RTR bit is recessive.
◻ Error Frame: It is transmitted when a error is detected.

◻ Overload Frame: It is used to provide delay between messages. It

is transmitted when the nodes become too busy.
◻ Valid Frame: A message is valid if the EOF field is recessive. Else
the message is transmitted again.
 CAN bus …
87

◻ The image below shows how the different devices are

connected using the CAN protocol.
 CAN Bus…
88
 Advantages of CAN Bus
89

◻ The controller area network (CAN) reduces wiring since it is a distributed

control and this ensures enhancing of the system performance.
◻ It support multi master and multicast features.
◻ The CAN bus has maximum length of 40 meters.
◻ The CAN provides the ability to work in different electrical environment.
◻ It has single serial bidirectional line to achieve half duplex
communication.
◻ It has standard bus in distributed network.
◻ It cost is low and lightweight network.
◻ It has automatic retransmission for message that lost attribution.
 Disadvantages of CAN Bus
90

◻ It has high software expenditure. It incurs more

expenditure for software development and maintenance.
◻ It is likely to have undesirable interactions between
nodes.
◻ Though maximum number of nodes are not specified for
the network. It supports upto 64 nodes due to electrical
loading.
 Applications of CAN bus
91

◻ The controller area network (CAN) is used for

transmission airbags, antilock braking, electric power
steering etc.
◻ It is used in audio video systems.
◻ The controller area network (CAN) is used in lifts and
escalators.
◻ It is used in sport cameras.
◻ It is used in automatic doors.
◻ It is used in telescope and coffee machines.
 Applications of CAN bus
92

◻ The controller area network (CAN) is used in aircraft with

flight state sensors, navigation systems, flight data analysis
to aircraft engine control systems such as fuel systems,
linear actuators and pumps.
◻ It is used to windows, doors, and mirror adjustment.
◻ It is used in railway applications such as streetcars, trams,
undergrounds, light railways and long-distance trains
incorporate etc.
PARALLEL
COMMUNICATION
STANDARDS
ISA, PCI and PCI-X Bus
 Parallel communication bus types
94

◻ ISA bus – Industry Standard Architecture

◻ EISA bus – Extended Industry Standard Architecture

◻ PCI bus – Peripheral Component Interconnect

◻ PCI-X bus– Peripheral Component Interconnect

eXtended
ISA BUS – INDUSTRY
STANDARD
ARCHITECTURE
 ISA BUS
96

8-bit 16-bit
ISA (8 Bit) Buses
• Used in the first 4.77-MHz PCs introduced in 1982.
• 62 - Pin Bus.
• 8 Data Lines (allowing for 8 bits of data to be transferred at a time).
• 20 address lines (1 Mbytes of addressing ).
ISA (16 bit) Buses
• 8.33-MHz Bus introduced in 1984.
• 62 + 36 - Pin Bus.
• Eight more data lines (allowing for 16-bit data transfers).
• Four more address lines (allowing 16 Mbytes of addressing).
 ISA BUS
More More
DMA IRQ lines 8-15 DMA ± 5, ±12V
IRQ lines
lines 2-7 clock lines Power & G

Extra 8 bits of Extra 4 bits of 20 bits of Address bus

I/O bus Address bus 8 bits of I/O bus

16 bit Original 8 bit ISA

99
 ISA Bus
100

◻ The BUS is divided into two sides.

◻ The first side pins are named A1 to A31
and it is the components side.
It consists of the address and data buses.
◻ The second side pins are named B1 to
B31 and it is the solder side.
This side contents the power pins and the
signals related to interrupts and DMA
transfers.
ISA Bus
Advantages Disadvantages
◻ Low cost ◻ Low speed
◻ Compatibility ◻ Jumpers and DIP switches
◻ Used widely ◻ Becoming out-dated
◻ Limited number of
interrupts.
◻ No central registry.

101
EISA – EXTENDED
INDUSTRY STANDARD
ARCHITECTURE
 EISA – Extended Industry Standard
103
Architecture
◻ Developed by the "Gang of Nine" (nine non-IBM
manufacturers of IBM-compatible PCs, led by Compaq)
in 1988.
◻ 32 Bit Bus.
◻ Runs at 8.33 MHz.
◻ Pins - 98 + 100 inlay
◻ The theoretical maximum transfer speed is 33 Mbytes/s.
◻ Compatible with 8 bit ISA, 16 bit ISA, 32 bit EISA
 EISA
104

Advantages
◻ ISA Compatibility: ISA cards will work in EISA slots.
◻ 32 Bit Bus Width: Like MCA (Micro Channel Architecture, 1987) ,
the bus was expanded to 32 bits.
◻ Bus Mastering: The EISA bus supports bus mastering adapters for
greater efficiency, including proper bus arbitration.
◻ Plug and Play: EISA automatically configures adapter cards, similar
to the Plug and Play standards of modern systems
 EISA
105

Disadvantages
◻ It never became widely used .
◻ It is no longer found in computers today.
 ISA bus
106
 ISA BUS
107

ISA Card
 EISA bus
108
 EISA – 1988
109

◻ EISA card – Does not fit in ISA slot.

◻ EISA card do not fit in existing ISA-slot systems so never became popular.
◻ Was mainly used in server systems where highest performance was more
important than compatibility with older platforms.
 PCI + ISA Bus
110
 PCI bus
111
 PCI bus
112
PCI BUSES – PERIPHERAL
COMPONENT
INTERCONNECT BUSES
 Older PC Implementations
114
 Newer PC Implementations
115
 Block diagram of a PCI bus system
116
 PCI Buses – Peripheral Component
117
Interconnect Buses
• Created by Intel (1992)
• PCI bus, 32 or 64-bit operating at 33 MHz
• PCI-X bus, 32 or 64-bit operating at 66/133 MHz
• Designed to support ISA and EISA buses.
• It interfaces the expansion bus and the memory bus.
 PCI Bus – Peripheral Component
118
Interconnect Bus
3 main goals:
To get better performance when transferring data between the
computer and its peripherals.
■ uses a higher clock rate (25 or 33 MHz) than ISA.
To be as platform independent as possible.
■ is used extensively on IA-32, Alpha, PowerPC, SPARC64, and IA-64 systems.
To simplify adding and removing peripherals to the system.
■ supports for auto detection of interface boards.
 PCI Express bandwidth comparison
119
 PCI Technology
120

Conventional PCI
It is a parallel bus, synchronous to a single bus clock.
Initial PCI 1.0 proposal by Intel in 1991
Introduced by PCI-SIG as PCI 2.0 in 1993
Version 2.1 approved in 1995
Recent version 2.3 approved in March 2002
PCI-X
PCI-X standard was developed jointly by IBM, HP, and Compaq and submitted for approval in 1998.
Version 1.0 approved in September 1999
Version 2.0 approved in July 2002
PCI Express
High-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X, and AGP
bus standards
Formerly known as 3GIO
Version 1.0 approved in July 2002
 Conventional PCI
121

◻ Plug-and-Play Functionality
◻ Standard PCI is 32 bit and operates at 33 MHz
Throughput 133 MB/sec
◻ PCI 2.1 introduced
Universal PCI cards supporting both 3.3V and 5V
32-Bit throughput @ 66 MHz: 266 MB/sec
64-Bit throughput @ 66 MHz: 532 MB/sec
◻ PCI 2.3 system no longer supports 5V-only adapters
3.3V and Universal PCI products are still fully supported
 PCI-X 1.0
122

◻ Based on existing PCI architecture

◻ 64-Bit slots with support for 3.3V and Universal PCI
No support for 5V-only boards!
◻ Fully backwards-compatible
Conventional 33/66 MHz PCI adapters can be used in PCI-X
slots
PCI-X adapters can be used in conventional PCI slots
◻ Provides two speed grades: 66 MHz and 133 MHz
 PCI-X 2.0
123

◻ Based on PCI-X 1.0

Still fully backwards-compatible
◻ Introduces ECC (Error Correction Codes mechanism to improve
robustness and data integrity)
◻ Provides two additional speed grades
PCI-X 266: 266 MHz (2.13 GB/sec)
PCI-X 533: 533 MHz (4.26 GB/sec)
◻ Bandwidth sufficient to support new breed of cutting-edge
technologies
10 Gigabit Ethernet / Fiber Channel
4X/12X infiniBand
 PCI-X Speed Limitations
124

◻ PCI-X supports point-to-point and multi-drop loads

◻ Highest speed grades are supported exclusively with
point-to-point loads
PCI-X 133
PCI-X 266
PCI-X 533
◻ Two PCI-X 133 loads operate at 100 MHz
PCI CONFIGURATION
 Configuration Space Header
126

Device Vendor 0
ID
Statu ID
Comman 0
s Class d Re 4
0
BIS Code
Header Latency Cachev Line 8
0
T Type Timer
Base Address Size 1
C
0
Base Address 0
1
1
Base Address 4
1
2
Base Address 8
1
3
Base Address C
2
4
Base Address 0
2
5 CIS
Cardbus 4
2
Subsystem Pointer Subsystem Vendor 8
2
ID Expansion ROM Base ID C
3
Address
Reserve 0
3
d
Reserve 4
3
Max_La Min_Gn d Interrupt Interrupt 8
3
t t Pin Line C
 System Initialization
127

◻ Configuration allows software (BIOS) to initialize the system

◻ Each device has configuration registers

◻ At power up software scans bus(es)

◻ Software analyses system requirements

◻ Configuration registers are set to configure individual devices

 PCI Configuration Register
128

◻ Device ID
◻ Vendor ID
◻ Status / Command reg.
◻ Base Address [0,1,2,3,4,5]
◻ Maximum Latency
◻ Minimum GNT
◻ Subsystem ID, Subsystem Vendor ID
 PCI Configuration Register
129
 PCI Command Types [C/BE]
130

◻ 0000 -> INTR ack

◻ 0010 -> I/O Read
◻ 0011 -> I/O Write
◻ 0110 -> Memory Read
◻ 0111 -> Memory Write
◻ 1010 -> Configuration read
◻ 1011 -> Configuration write
 PCI device identification
131

◻ The hardware circuitry of each peripheral board will know

memory locations, I/O ports, and configuration registers.
◻ Memory locations and I/O ports are shared by all the devices
on a PCI bus.
◻ Each PCI peripheral is identified by a bus number(16-bits),
combined by bus (8), device(5), and function(3).
◻ Using the lspci tool, we can get the information of each PCI
peripheral.
◻ BB:DD.F as three values (bus, device, and function)
 Each PCI device on Bus
132

◻ May contain a processor and software to perform a

specific function.
◻ Each device has the specific memory address-range,
specific interrupt-vectors and the device I/O port
addresses.
◻ A bus of appropriate specifications and protocol
interfaces these to the host computer system or compute
◻ PCI bus unique feature is its configuration address space.
 PCI controller Features
133

◻ Accesses one device at a time

◻ All the devices within host device or system can share
the I/O port and memory addresses, but cannot share the
configuration registers
◻ Device cannot modify other configuration registers but
can access other device resources or share the work or
assist the other device PCI controller Features
 PCI Bus Configuration
134

◻ When power is applied to a PCI device, the hardware the

will respond only to configuration transactions.
Configuration Registers and Initialization
◻ PCI devices feature a 256-byte address space. The first
64 bytes are standardized, while the rest are device
dependent.
◻ The PCI registers are always little-endian.
 PCI Bus accessing
135

Accessing the Configuration Space

◻ After the driver has detected the device, it usually needs to read
from or write to the three address spaces: memory, port, and
configuration.
◻ Because the microprocessor has no way to access the configuration
space directly, the computer vendor has to use the PCI controller to
write and read registers.
Accessing the I/O and Memory Spaces
◻ A PCI device implements up to 6 I/O address regions.

◻ Each region consists of either memory or I/O locations.

 PCI Bus
136

Advantages

Very high speed, plug & play, dominant board-level bus

Disadvantages

■ Incompatible with older systems, can cost more

 Overview of Speeds of buses
137

Bus Type Bus Width Bus Speed MB/sec

ISA 16 bits 8 MHz 16MBps
EISA 32 bits 8 MHz 32MBps
PCI 32 bits 33 MHz 132MBps

PCI 64 bits 33 MHz 264MBps

PCI 64 bits 66 MHz 512MBps

PCI 64 bits 133 MHz 1GBps

 BUS COMPARISON
138

Theoretical
Bus Clock Bus
Type of Bus Maximum Advantages Disadvantages
Signal Width
Transfer Rate
8 Mbytes/sec Low speed, jumpers & DIP
ISA 8 MHz 16-bit Low cost, compatibility, widely used
(64 Mbits/sec) switches. Becoming obsolete

Incompatible with older

1 Gbytes/sec (8 Very high speed, plug & play, dominant
PCI 133 MHz 64-bit systems,
Gbits/sec) board-level bus
can cost more
Lower speed than PCI, need
Designed for industrial use, hot
132 Mbytes/sec adapter for PC use,
Compact PCI 33 MHz 64-bit swapping/plug & play, ideal for embedded
(1 Gbit/sec) incompatible with older
systems
systems
Slower than PCI and other
Low cost, ideal for portable systems, hot
1.5 Mbytes/sec plug-in busses (such as
USB 1.1 n/a n/a swapping/plug & play, up to 127 devices
(12 Mbits/sec) firewire), not compatible with
via 1 port
older peripherals
 BUS COMPARISON
139

Theoretical
Type of Bus Clock Bus
Maximum Advantages Disadvantages
Bus Signal Width
Transfer Rate
All the advantages of USB plus
significantly higher speeds making
60 Mbytes/sec (480 Not compatible with older
USB 2.0 n/a n/a it compatible with high-speed
Mbits/sec) peripherals, still slower than PCI
peripherals such as data drives and
video cameras.

Enables multiple PCs to remotely Most peripheral devices cannot be

Ethernet share information and peripheral connected directly to ethernet,
1.25 Mbyte/sec (10
10 Base n/a n/a devices, provides error checking adapter is required. Slow data
Mbits/sec)
T lacking in standard serial communication by current
communication standards Possible security issues.