4th Sem CSE.
Microcontrollers (Course Code: BCS 402) 2026
Module-2 8 Hrs
Syllabus:
Introduction to the ARM Instruction Set: Data Processing Instructions, Branch
Instructions, Software Interrupt Instructions, Program Status Register Instructions,
Coprocessor Instructions, Loading Constants.
Textbook 1: Chapter 3 - 3.1 to 3.6
Data Processing Instructions:
The data processing instructions manipulate data within registers.
Various data processing instructions are,
1) Move instructions
2) Arithmetic instructions
3) Logical instructions
4) Comparison instructions
5) Multiply instructions
1) Move instructions:
Move is the simplest data processing instruction.
Move instruction copies register value / immediate value ‘N’ into a destination
register ‘Rd’.
Move instructions are also called as “Barrel Shifter Instructions”. Imp
Syntax: <instruction> {<condition>} {S} Rd , N
Suffix S – Updates the flags in the CPSR
Rd – Destination register
N – Register value or Immediate value
Types:
MOV Move a 32-bit value into a destination Rd = N
register
MVN Move NOT(negation) of the 32-bit value Rd = ~ N
into a destination register
Prashanth Kumar A P., Asst. Professor, Dept. of CSE., MRIT, Mandya. 98448 59950 1
4th Sem CSE. Microcontrollers (Course Code: BCS 402) 2026
Example:
Pre r1=2
r2=3
MOV r2, r1
Post r1=2
r2=2
2) Arithmetic instructions:
Arithmetic instructions are used to perform addition & subtraction of 32-bit
signed and unsigned values.
Syntax: <instruction> {<condition>} {S} Rd , Rn , N
Suffix S – Updates the flags in the CPSR
Rd – Destination register
Rn – Source register
N – Register value or Immediate value
Types:
ADD Add two 32-bit values Rd = Rn + N
SUB Subtract two 32-bit values Rd = R n – N
ADC Add two 32-bit values with carry Rd = Rn + N + carry
SBC Subtract two 32-bit values with carry Rd = Rn – N -- carry
Examples:
Pre r1= 0x00000000
r2= 0x00000003
r3= 0x00000002
ADD r1, r2, r3
Post r1= 0x00000005
Prashanth Kumar A P., Asst. Professor, Dept. of CSE., MRIT, Mandya. 98448 59950 2
4th Sem CSE. Microcontrollers (Course Code: BCS 402) 2026
Pre r1= 0x00000000
r2= 0x00000003
r3= 0x00000002
SUB r1, r2, r3
Post r1= 0x00000001
3) Logical instructions:
Logical instructions are used to perform bitwise logical operations on two
source registers.
Syntax: <instruction> {<condition>} {S} Rd , Rn , N
Suffix S – Updates the flags in the CPSR
Rd – Destination register
Rn – Source register
N – Register value or Immediate value
Types:
AND Logical bitwise AND of two 32-bit Rd = R n & N
values
ORR Logical bitwise OR of two 32-bit Rd = R n | N
values
EOR Logical bitwise EX-OR of two Rd = R n ^ N
32-bit values
BIC Logical bit clear (AND NOT) Rd = Rn & ~N
Examples:
Pre r1= 0x00000000
r2= 0x00000003
r3= 0x00000002
AND r1, r2, r3
Post r1= 0x00000006
Prashanth Kumar A P., Asst. Professor, Dept. of CSE., MRIT, Mandya. 98448 59950 3
4th Sem CSE. Microcontrollers (Course Code: BCS 402) 2026
Pre r1= 0x00000000
r2= 0x00000003
r3= 0x00000002
ORR r1, r2, r3
Post r1= 0x00000005
4) Comparison instructions:
Comparison instructions are used to compare two 32-bit values or test a 32-bit
value.
These instructions update the CPSR flag bits according to the result.
Syntax: <instruction> {<condition>} {S} Rn , N
Suffix S – Updates the flags in the CPSR
Rn – Source register
N – Register value or Immediate value
Types:
CMP Compare two 32-bit values Flags set as a result of Rn - N
CMN Compare negation of two Flags set as a result of Rn + N
32-bit values
TEQ Test equality of two 32-bit Flags set as a result of Rn ^ N
values
TST Test bits of a 32-bit value Flags set as a result of Rn & N
Example:
Pre cpsr = nzcv
r1= 0x00000003
r2= 0x00000003
CMP r1, r2
Post cpsr=nZcv
Prashanth Kumar A P., Asst. Professor, Dept. of CSE., MRIT, Mandya. 98448 59950 4
4th Sem CSE. Microcontrollers (Course Code: BCS 402) 2026
5) Multiply instructions:
These instructions are used to multiply the contents of a pair of registers(two
32-bit registers).
Syntax: MUL {<condition>} {S} Rd , Rm , Rs
MLA {<condition>} {S} Rd , Rm , Rs , Rn
Suffix S – Updates the flags in the CPSR
Rd – Destination register
Rm , Rs , Rn – Source registers
Types:
MUL Multiply two 32-bit values Rd = R m * Rs
MLA Multiply and accumulate two 32-bit Rd = (Rm * Rs) + Rn
values
Example:
Pre r1= 0x00000000
r2= 0x00000003
r3= 0x00000002
MUL r1, r2, r3
Post r1= 0x00000006
r2= 0x00000003
r3= 0x00000002
Prashanth Kumar A P., Asst. Professor, Dept. of CSE., MRIT, Mandya. 98448 59950 5
4th Sem CSE. Microcontrollers (Course Code: BCS 402) 2026
Branch instructions:
Branch instructions are used to change the flow of execution or used to call a
subroutine.
Branch instructions allow the programs consists of subroutines, loops and if-
then-else structures.
Syntax: B {<condition>} label
BL {<condition>} label
BX {<condition>} Rm
BLX {<condition>} label | Rm
Label – Loop name or subroutine name
Rm – Source register
Types:
B Branch pc = label
BL Branch with link pc = label
lr = address of the next
instruction after the BL
BX Branch exchange pc = Rm & 0xfffffffe
BLX Branch exchange with link pc = label
pc = Rm & 0xfffffffe
lr = address of the next
instruction after the BLX
Example:
B forward
ADD r1, r2, r3
ADD r4, r5, #5
forward
SUB r1, r2, #4
Prashanth Kumar A P., Asst. Professor, Dept. of CSE., MRIT, Mandya. 98448 59950 6
4th Sem CSE. Microcontrollers (Course Code: BCS 402) 2026
Load-Store instructions:
Load-store instructions are used to transfer data between memory and
processor registers.
There are 3 types of load-store instructions,
1) Single Register Transfer instructions
2) Multiple Register Transfer instructions
3) SWAP instructions
1) Single Register Transfer Instructions:
These instructions are used to for moving a single data in and out of a register.
These instructions support the datatype of unsigned words(32-bits), unsigned
halfwords(16-bits) and unsigned bytes(8-bits).
Syntax: LDR {<condition>} Rd , addressing
STR {<condition>} Rd , addressing
Rd – Destination register
Addressing—Memory address
Types:
LDR Load a word into a register Rd mem 32[address]
STR Save or Store a word from a Rd mem32[address]
register
LDRH Load a halfword into a register Rd mem 16[address]
STRH Save or Store a halfword from Rd mem 16[address]
a register
LDRB Load a byte into a register Rd mem 8[address]
STRB Save or Store a byte from a Rd mem 8[address]
register
Prashanth Kumar A P., Asst. Professor, Dept. of CSE., MRIT, Mandya. 98448 59950 7
4th Sem CSE. Microcontrollers (Course Code: BCS 402) 2026
Example:
LDR r0, [r1]
Load register r0 with the contents of the memory whose address is pointed by
register r1.
STR r0, [r1]
Save or Store the contents of register r0 to the memory whose address is
pointed by register r1.
2) Multiple Register Transfer Instructions:
These instructions are used to transfer multiple registers values between
memory and the processor in a single instruction.
Syntax: instruction {<condition>} <addressing mode> Rn{!}, <registers>{^}
Rd – Destination register
Addressing modes—Increment After (IA)
Increment Before (IB)
Decrement After (DA)
Decrement Before (DB)
Types:
LDM Load multiple Rd mem 32[ start address + 4*N]
registers
STM Save or Store Rd mem 32[ start address + 4*N]
multiple registers
Prashanth Kumar A P., Asst. Professor, Dept. of CSE., MRIT, Mandya. 98448 59950 8
4th Sem CSE. Microcontrollers (Course Code: BCS 402) 2026
3) SWAP Instructions:
These instructions are used to swap the contents of memory with the contents
of a register.
The swap instruction is a special case of load-store instruction.
Syntax: SWP {<condition>} Rd, Rm, [Rn]
Rd – Destination register
Rm ,Rn – Source registers
Types:
SWP Swap a word(32-bits) between tmp = mem 32[Rn]
memory and a register mem 32[Rn] = Rm
Rd = tmp
SWPB Swap a byte(8-bits) between memory tmp = mem 8[Rn]
and a register mem 8[Rn] = Rm
Rd = tmp
Example:
Pre mem 32[0x00000001] = 0x12345678
r0= 0x00000000
r1= 0x11223344
r2= 0x00000001(memory address)
SWP r0, r1, [r2]
Post mem 32[0x00000001] = 0x11223344
r0= 0x12345678
r1= 0x11223344
r2= 0x00000001(memory address)
Prashanth Kumar A P., Asst. Professor, Dept. of CSE., MRIT, Mandya. 98448 59950 9
4th Sem CSE. Microcontrollers (Course Code: BCS 402) 2026
Software Interrupt Instructions:
A software interrupt instruction (SWI) causes a software interrupt.
This instruction is commonly used in operating systems (OS) to call sub
routines.
Syntax: SWI {<condition>} SWI_number
Types:
SWI Software Interrupt pc = vector + 0x00000008
cpsr mode = SVC (supervisor mode)
The SWI_number is determined by,
SWI_number = <SWI instruction> AND NOT(0xff000000)
SWI instruction is handled by ‘SWI handler’.
Prashanth Kumar A P., Asst. Professor, Dept. of CSE., MRIT, Mandya. 98448 59950 10
4th Sem CSE. Microcontrollers (Course Code: BCS 402) 2026
Program Status Register Instructions:
These instructions are used to directly control program status registers(psr).
Syntax: MRS {<condition>} Rd , <cpsr | spsr>
MSR {<condition>} <cpsr | spsr>, Rm
Rd – Destination register
Rm – Source register
Types:
MRS Move the contents of program Rd = psr
status register (cpsr or spsr)
into destination register Rd
MSR Move the contents of input psr= Rm
register Rm into program status
register (cpsr or spsr)
Example:
Pre cpsr = 0x12345678 nzcv
r0= 0x00000000
MRS r0, cpsr
Post cpsr = 0x12345678 nzcv
r0= 0x12345678
Prashanth Kumar A P., Asst. Professor, Dept. of CSE., MRIT, Mandya. 98448 59950 11
4th Sem CSE. Microcontrollers (Course Code: BCS 402) 2026
Coprocessor Instructions:
These instructions are used to extend the instruction set.
The processor can share the work with the coprocessor.
A coprocessor can provide additional computational capability or control the
memory.
There are 16 coprocessors p0--p15.
Syntax:
CDP {<condition>} cp, opcode1, Cd, Cn {,opcode2}
<MRC | MCR> {<condition>} cp, opcode1, Rd, Cn, Cm {,opcode2}
<LDC | STC> {<condition>} cp, Cd, addressing
cp – Coprocessor number
Types:
CDP Coprocessor Data Processing
MRC | MCR Coprocessor Register Transfer
LDC | STC Coprocessor Memory Transfer
Example:
MRC cp15, 0, r1, c0, c0, 0
Here cp15 is the coprocessor number
Prashanth Kumar A P., Asst. Professor, Dept. of CSE., MRIT, Mandya. 98448 59950 12
4th Sem CSE. Microcontrollers (Course Code: BCS 402) 2026
Loading Constants:
These instructions are used to move a 32-bit constant or 32-bit value into a
register.
Syntax:
LDR Rd , =constant
ADR Rd , label
Types:
LDR Load 32-bit constant into a register Rd = 32-bit constant
ADR Load 32-bit address into a register Rd = 32-bit address
Example:
LDR r0, #0xffffffff
Prashanth Kumar A P., Asst. Professor, Dept. of CSE., MRIT, Mandya. 98448 59950 13
4th Sem CSE. Microcontrollers (Course Code: BCS 402) 2026
Question Bank with Approximate Expected Marks
1) Explain different arithmetic instructions in ARM processor with an example.
(10 Marks, VTU Model Paper)
2) Explain single register load store addressing mode syntax, table, index mode with an
example.
(10 Marks, VTU Model Paper)
3) Examine data processing instructions requirement in the manipulation of data
register? Explain in brief data processing instructions.
(10 Marks, June/July 2024)
4) Explain with examples the following 32-bit instruction of ARM processor
i) CMN ii) MLA iii) MRS iv) BIC v) LDR
(10 Marks, June/July 2024)
5) Explain arithmetic and logical data processing instructions with syntax, examples and
code snippet for each.
(10 Marks, June/July 2024 Supplementary)
6) Explain four stepls of stack implementation in ARM with examples for each.
(10 Marks, June/July 2024 Supplementary)
7) Explain barrel shifter instructions in ARM with suitable example.
(10 Marks, VTU Model Paper)
8) Explain different Logical instructions in ARM processor with an example.
(10 Marks, VTU Model Paper)
9) Explain the following with example:
i)Stack operation ii) Swap instructions
(10 Marks, June/July 2024)
10) Explain Branch instructions in ARM with suitable example. Demonstrate Branch
instruction usage flow of execution with an example program.
(10 Marks, June/July 2024)
11) Write a note on:
i) Coprocessor Instructions ii) Software Interrupt instructions
(10 Marks, June/July 2024 Supplementary)
Prashanth Kumar A P., Asst. Professor, Dept. of CSE., MRIT, Mandya. 98448 59950 14
4th Sem CSE. Microcontrollers (Course Code: BCS 402) 2026
12) Develop ARM ALP to find largest number in an array of 32 bit numbers. Program
should be neatly commented.
(10 Marks, June/July 2024 Supplementary)
13) Explain different move instructions in ARM processor with an example. (10M).
14) Explain different comparison instructions in ARM processor with an example. (10M)
15) Explain different multiply instructions in ARM processor with an example. (10M)
16) Explain different branch instructions in ARM processor with an example. (10M)
17) Explain different single register transfer instructions in ARM processor with an
example. (10M)
18) Explain different multiple register transfer instructions in ARM processor with an
example. (10M)
19) Explain different swap instructions in ARM processor with an example. (10M)
20) Explain different software interrupt instructions in ARM processor with an example.
(10M)
21) Explain different program status register instructions in ARM processor with an
example. (10M)
22) Explain different coprocessor instructions in ARM processor with an example.
(10M)
23) Explain different loading constants in ARM processor with an example. (10M)
Prashanth Kumar A P., Asst. Professor, Dept. of CSE., MRIT, Mandya. 98448 59950 15