B.E.

COMPUTER ENGINEERING · THIRD YEAR

Microprocessor and
Interfacing
Unit 1

Introduction to Microprocessor • Components (Registers, ALU, Control & Timing) • System Bus • Bus Organization
 OVERVIEW

Topics Covered in This Unit

Introduction to Microprocessor Components of a Microprocessor

01 Definition, historical evolution, basic functions and
02 Registers, Arithmetic & Logic Unit, Control Unit and
applications timing signals

System Bus Microprocessor System with Bus

03 Data bus, address bus and control bus — roles and
04 Organization
How CPU, memory and I/O interconnect and
characteristics communicate

Overview Microprocessor and Interfacing | Unit 1 1

 FOUNDATIONS

Microprocessor vs Microcontroller

MICROPROCESSOR MICROCONTROLLER

A general-purpose device, called a CPU A dedicated chip, called a single chip

Microprocessor-based system design is complex Microcontroller-based system design is simple

Flexible — we can change the size Not flexible

Does not have power-saving features Has power-saving mode

Size of RAM / ROM can vary Size of RAM / ROM is fixed

Does not contain internal memory Contains internal memory

Cost is high Cost is low

E.g. 8085, Intel Core i5, AMD Ryzen E.g. 8051, ESP32 (industrial / IoT automation)

Devices — Server, Smartphone, Laptop Devices — Microwave oven, Refrigerator

1. Introduction Microprocessor and Interfacing | Unit 1 2

 FOUNDATIONS

At a Glance: Chips & Internal Blocks

1. Introduction Microprocessor and Interfacing | Unit 1 3

 1 Introduction to
Microprocessor

Definition · Historical Evolution · Basic Functions · Applications

1. Introduction Microprocessor and Interfacing | Unit 1 4

 1.1 DEFINITION

What Is a Microprocessor?

A microprocessor is a single integrated circuit (IC) chip that Fetch

contains the arithmetic, logic, and control circuitry required to
carry out the functions of a computer's central processing unit Retrieve instructions from memory
(CPU).

It fetches instructions from memory, decodes them, and Decode

executes them — acting as the “brain” of a digital system such as
a computer, embedded controller, or microprocessor-based Interpret the instruction
instrument.
A programmable electronic chip with computing and decision-making capability
similar to a computer's CPU: it reads binary instructions from memory, interprets them,
and performs arithmetic, logical, and control operations as specified by the instruction Execute
set.
Perform the operation

1. Introduction Microprocessor and Interfacing | Unit 1 5

 1.2 HISTORICAL EVOLUTION

Generations of Microprocessors

Generation Example Processor Year Data Width / Key Feature

1st Generation Intel 4004 1971 4-bit, PMOS technology

2nd Generation Intel 8085, Zilog Z80 1974-76 8-bit, NMOS technology

3rd Generation Intel 8086 / 8088 1978 16-bit, HMOS technology

4th Generation Intel 80386 1985 32-bit, HCMOS technology

64-bit, superscalar, pipelined, multi-

5th Generation Pentium series and beyond 1993-present
core

1. Introduction Microprocessor and Interfacing | Unit 1 6

 1.2 HISTORICAL EVOLUTION

Timeline of Microprocessor Generations

1. Introduction Microprocessor and Interfacing | Unit 1 7

 1.3 BASIC FUNCTIONS

The Fetch – Decode – Execute Cycle

1 2 3 4
Fetch Decode Execute Store / Write-back

Retrieve an instruction → Interpret the fetched → Carry out the operation → Save the result back to
(machine code) from instruction using the — this may involve the a register or memory
the memory location instruction decoder to ALU, registers, memory, location, if required.
pointed to by the determine the or I/O devices.
Program Counter. operation to perform.

This repeated sequence is called the Fetch–Decode–Execute cycle (or instruction cycle) — the fundamental operating principle of every microprocessor.

1. Introduction Microprocessor and Interfacing | Unit 1 8

 1.4 APPLICATIONS

Where Microprocessors Are Used

1 General-purpose computers (desktops, laptops, 2 Embedded systems (washing machines, microwave

servers) ovens, automotive ECUs)

3 4 Communication systems (routers, modems, mobile

Industrial automation and process control
handsets)

5
Instrumentation and measurement equipment

1. Introduction Microprocessor and Interfacing | Unit 1 9

 2 Components of a
Microprocessor

Registers · Arithmetic & Logic Unit · Control Unit & Timing Signals

2. Components Microprocessor and Interfacing | Unit 1 10

 2. INTERNAL ORGANIZATION

Three Principal Functional Blocks

Internally, a microprocessor is organized into three principal functional blocks that work together under a common clock:

Functional Block Primary Role

Register Array Temporary, high-speed storage of data, addresses, and status information

ALU Performs arithmetic and logical operations on data

Control Unit Generates timing and control signals; sequences fetch – decode – execute

2. Components Microprocessor and Interfacing | Unit 1 11

 2. INTERNAL ORGANIZATION

Block Diagram of Microprocessor

Fig. 1 — Block Diagram of Microprocessor

2. Components Microprocessor and Interfacing | Unit 1 12

 2. INTERNAL ORGANIZATION

System Bus & Internal Architecture

Fig. 2 — Block Diagram of System Bus & Internal Architecture

2. Components Microprocessor and Interfacing | Unit 1 13
 2.1 REGISTERS

Fast, On-Chip Storage

Registers are small, extremely fast storage locations built

directly into the microprocessor chip, used to hold data,
addresses, and status flags temporarily during program
execution. Because they lie inside the CPU itself, access to a
register is far faster than access to main memory.

Fig. 3 — Register Architecture of 8085 Microprocessor

2.1 Registers Microprocessor and Interfacing | Unit 1 14

 2.1 REGISTERS

General-Purpose Registers & Accumulator

(a) (b)
General-Purpose Registers Accumulator (A Register)

Used by the programmer/compiler to hold data A special-purpose register that holds one of the
temporarily during computation (e.g., B, C, D, E, H, L operands before an ALU operation and stores the
register pairs in the Intel 8085). They provide result after the operation. Most arithmetic and
flexible, fast intermediate storage and reduce the logical instructions implicitly use the accumulator,
number of memory accesses needed. making it the most frequently accessed register in
the CPU.

2.1 Registers Microprocessor and Interfacing | Unit 1 15

 2.1 REGISTERS

Program Counter & Stack Pointer

(c) (d)
Program Counter (PC) Stack Pointer (SP)

A 16-bit (or wider, depending on architecture) Holds the address of the top of the stack — a
register that always holds the memory address of reserved area of read/write memory used to store
the next instruction to be fetched. After each fetch, return addresses (during subroutine calls) and
the PC is automatically incremented so that it register contents (during PUSH/POP operations),
points to the subsequent instruction, unless operating on a Last-In-First-Out (LIFO) basis.
modified by a jump, call, or interrupt.

2.1 Registers Microprocessor and Interfacing | Unit 1 16

 2.1 REGISTERS

Instruction Register & Other Internal Registers

(e) (g)
Instruction Register (IR) MAR, MBR/MDR & Others

Temporarily holds the instruction opcode fetched Depending on the specific architecture, additional
from memory while it is being decoded by the internal registers such as a Memory Address
instruction decoder. The programmer cannot Register (MAR), Memory Buffer/Data Register
directly access this register; it is used internally by (MBR/MDR), and in advanced processors an
the control unit. Instruction Pointer, segment registers, and index
registers may also be present to support memory
addressing and pipelining.

2.1 Registers Microprocessor and Interfacing | Unit 1 17

 2.1 REGISTERS

(f) Flag (Status) Register

A register composed of individual flip-flops, each representing the outcome of the most recent ALU operation. Flags are tested by conditional branch
instructions (e.g., Jump if Zero) to alter the normal sequential flow of the program.

CY Z S P AC
Carry Flag Zero Flag Sign Flag Parity Flag Auxiliary Carry Flag

Set when an Set when the result Reflects the state Set if the result has Set when a carry is
arithmetic of an operation is of the most an even number of generated from bit
operation zero significant bit, 1-bits 3 to bit 4 (used
generates a carry indicating the sign chiefly in BCD
out of, or borrow of a signed result arithmetic)
into, the most
significant bit

2.1 Registers Microprocessor and Interfacing | Unit 1 18

 2.2 ARITHMETIC AND LOGIC UNIT

The Computational Heart of the CPU

The ALU is the computational heart of the microprocessor. It is a digital circuit built from combinational logic (adders,
comparators, shifters, and gates) that performs all arithmetic and logical operations required by an instruction.

Arithmetic Logical
Addition, subtraction, increment, decrement AND, OR, XOR, NOT, complement
(multiplication/division via repeated addition/subtraction
or dedicated hardware)

Bit Manipulation Comparison

Shift left/right, rotate left/right (through or without Comparing two operands and setting flags
the carry flag) accordingly

Note: The ALU itself has no memory of its own — it is a purely combinational circuit. All operands must be brought to it via registers, and results must be stored back into a register
immediately after each operation.

2.2 ALU Microprocessor and Interfacing | Unit 1 19

 2.3 CONTROL UNIT

Directing Every Activity in the CPU

The Control Unit (CU) directs and coordinates all activities inside the microprocessor and between the microprocessor
and the outside world. It does not process data itself; instead, it generates the sequence of control and timing signals
that tell every other block exactly what to do and when.

• Generate signals to fetch instructions from memory in correct sequence

• Decode the fetched opcode with the help of the instruction decoder
• Generate control signals for reading from / writing to memory and I/O ports (e.g., MEMR, MEMW, IOR, IOW)
• Enable appropriate internal registers and the ALU at the correct time so data flows correctly
• Manage interrupts, DMA requests, and reset operations

2.3 Control Unit Microprocessor and Interfacing | Unit 1 20

 2.3 CONTROL UNIT

Timing Signals & the Clock

All operations inside a microprocessor are synchronized to a master clock signal generated by an external crystal
oscillator. In the Intel 8085, an opcode fetch cycle normally takes 4 T-states, while a memory read/write cycle takes 3 T-
states; a complete instruction such as MOV or ADD may take 1–3 machine cycles.

Term Definition

T-state One clock period; the smallest unit of processor timing

Time needed for the CPU to complete one basic operation (fetch, memory
Machine Cycle
read/write, I/O read/write)
Total time to fetch and execute one complete instruction (comprises one or more
Instruction Cycle
machine cycles)

Also generated: ALE (Address Latch Enable), RD (Read), WR (Write), IO/M (I/O or Memory select), READY — coordinating data transfer along the system buses.

2.3 Control Unit Microprocessor and Interfacing | Unit 1 21

 3 System Bus

Data Bus · Address Bus · Control Bus

3. System Bus Microprocessor and Interfacing | Unit 1 22

 3. SYSTEM BUS

Connecting CPU, Memory & I/O

A bus is a group of conducting lines that carries related information — data, addresses, or control signals — from one
part of a microprocessor-based system to another. Because the CPU, memory, and I/O devices are physically separate
units, buses provide the common electrical pathway that connects and lets them exchange information.

Working of System Bus

3. System Bus Microprocessor and Interfacing | Unit 1 23
Instruction Cycle
 3.1 – 3.3

Data Bus, Address Bus & Control Bus

3.1 3.2 3.3

Data Bus Address Bus Control Bus

• Bidirectional group of lines • Unidirectional — used • Carries timing & control

transferring actual data exclusively by the CPU to signals: MEMR, MEMW, IOR,
(instructions/operands) specify a memory/I-O location IOW, Reset, INTR/INTA, Ready
• Width determines • An n-bit address bus can • Individual lines are
classification: typical widths 8, address 2ⁿ distinct locations unidirectional; collectively
16, 32, 64 bits • 8085: 16-bit address bus → signals flow both ways
• Wider bus → more data 2¹⁶ = 65,536 (64K) locations • Tells devices whether the
moved per cycle → higher operation is read/write,
processing speed memory/I-O

3. System Bus Microprocessor and Interfacing | Unit 1 24

 3.4 COMPARISON

Data Bus vs Address Bus vs Control Bus

Feature Data Bus Address Bus Control Bus

Unidirectional (CPU → Signals flow both ways

Direction Bidirectional
Memory/IO) (individually unidirectional)

Carries actual data / Carries the address of Carries timing & control
Purpose
instructions memory/IO location signals

Varies by number of control

Width (typical) 8 / 16 / 32 / 64 bits 16 / 20 / 32 bits
signals

Maximum addressable Type & timing of operation

Determines Data transferred per cycle
memory (2ⁿ) (read/write, memory/IO)

3. System Bus Microprocessor and Interfacing | Unit 1 25

 4 Microprocessor System
with Bus Organization

How CPU, Memory and I/O Work Together

4. Bus Organization Microprocessor and Interfacing | Unit 1 26

 4.1 BLOCK-LEVEL ORGANIZATION

Conceptual System Structure

A complete microprocessor-based system connects the CPU, memory (ROM/RAM), and I/O devices through the three
system buses. Because all devices share the same bus lines, only one device may place data on the data bus at any
instant — enforced through tri-state buffers and control signals.

Block Connected via Function

Address Bus (out), Data Bus (in/out), Fetches, decodes and executes instructions;
Microprocessor (CPU)
Control Bus (out/in) generates addresses and control signals

Memory Unit (ROM + Address Bus (in), Data Bus (in/out), Stores program instructions and data; responds
RAM) Control Bus (in) to MEMR/MEMW signals

Interfaces the system with the outside world

Address Bus (in), Data Bus (in/out),
Input/Output Devices (keyboard, display, sensors, actuators);
Control Bus (in)
responds to IOR/IOW signals

4. Bus Organization Microprocessor and Interfacing | Unit 1 27

 4.2 BUS ACTIVITY

A Typical Memory-Read Cycle

1 The CPU places the 16-bit address of the memory location to be read onto the Address Bus.

2 The CPU activates the control signal — IO/M is set low (memory operation) and MEMR is asserted on the
Control Bus.

3 The addressed memory chip decodes the address, places the requested byte of data onto the Data Bus, and
the CPU reads it in.

4 Once the data has been latched by the CPU, the control signal is de-asserted, completing the machine cycle.

An analogous sequence — using MEMW, IOR, or IOW in place of MEMR — governs memory-write and I/O read/write cycles.

4. Bus Organization Microprocessor and Interfacing | Unit 1 28

 4.3 BUS ORGANIZATION

Key Characteristics

• Common (shared) bus structure — all devices share the same physical bus lines, reducing wiring complexity
• Tri-state operation — only one device drives the bus at a time; others remain high-impedance
• Address decoding — decoder circuitry ensures only the intended chip/device responds to a given address
• Bus arbitration — logic (e.g., HOLD/HLDA in the 8085) decides which device controls the bus when there are
multiple masters
• Scalability and modularity — memory/I-O modules can be added or replaced without redesigning the system

KEY TAKEAWAY
The data bus carries “what” is being transferred, the address bus specifies “where”, and the control bus specifies “when” and “how”. Together, driven by
the control unit's timing signals, these three buses form the backbone of every microprocessor-based system.

4. Bus Organization Microprocessor and Interfacing | Unit 1 29

 REFERENCE

Features of the Intel 8085

• 8-bit general-purpose microprocessor Internal Registers

• 40-pin dual-in-line package (DIP) single-chip IC • One 8-bit Accumulator (ACC) register A
• Single +5V power supply; operates with a 3 MHz single- • Six 8-bit general-purpose registers: B, C, D, E, H, L
phase clock • One 16-bit Stack Pointer (SP)
• Provides Serial Input Data (SID) and Serial Output Data • One 16-bit Program Counter (PC)
(SOD) lines for simple serial interfacing • Instruction Register
• Temporary Register

Reference Microprocessor and Interfacing | Unit 1 30

 40 pin
Diagram
of 8085

Courtesy : [Link]
 WRAP-UP

Summary

• A microprocessor is a programmable IC that performs the fetch–decode–execute cycle to run stored programs.
• Its three principal internal blocks are the register array, the ALU, and the control unit.
• Registers (accumulator, PC, SP, IR, flag register, general-purpose registers) provide fast temporary storage.
• The ALU performs all arithmetic and logic operations and updates the flag register.
• The control unit generates timing signals (T-states, machine cycles, instruction cycles) and control signals that sequence every operation.
• The system bus — data, address, and control buses — connects the CPU to memory and I/O, enabling coordinated data transfer.
• Bus organization allows a microprocessor system built from separate chips to operate as a single, synchronized computing system.

Summary Microprocessor and Interfacing | Unit 1 31

 REFERENCE DIAGRAM

8085 Microprocessor Architecture

Fig. 5 — 8085 Microprocessor Architecture

Reference Microprocessor and Interfacing | Unit 1 32
 SELF-ASSESSMENT

Review Questions
1. Define a microprocessor and describe its four basic functions. 2. Explain the role of the accumulator, program counter, and stack pointer with
suitable examples.

3. List and explain any five flags found in the flag register of a typical 8-bit 4. Differentiate between a T-state, a machine cycle, and an instruction cycle.
microprocessor.

5. Compare the data bus, address bus, and control bus in terms of direction, 6. With a neat block diagram, explain how the CPU, memory, and I/O devices are
width, and function. interconnected through the system bus.

7. Describe the sequence of bus activity that takes place during a memory-read 8. Why are tri-state buffers essential in a common-bus system organization?
machine cycle.

Review Questions Microprocessor and Interfacing | Unit 1 33

Thank You
Courtesy / References
• Electronics Engineering Study Center
• [Link]
• Microprocessor & Interfacing — By Ramesh Gaonkar
• EEEGUIDE
• Tutorialpoints
• Learncomputerscienceonline

GTU | Information Technology Department | Microprocessor and Interfacing — Unit 1