Electronic Interlocking Design Process

New Design
 Electronic Interlocking Design
Electronic Interlocking Design process consists of:

Application Interlocking Program Design:

Complete Interlocking program, further converted in conventional circuit for which is
easy to understand.

Interface Circuit Design:

Wiring diagram of relays, panels, CT racks, Power supply, EI Circuits etc.
(Mainly external to EI)
 Electronic Interlocking Design

Interface Circuit Design: Application Interlocking Program Design:

Wiring diagram of
1. Complete Interlocking program,
1. Relays,
2. Panels, 2. Converted in conventional circuit for
3. CT racks, which is easy to understand.
4. Power supply,
5. EI circuits etc.
6. (Mainly external to ei)
 Design & Verification Process

START

Inputs
SIP, ToC, PD, Typical
Circuits etc.,
Received from
Customer

Review the Inputs

Interface Circuit Application Logic

Design Design
 Design & Verification Process
D
SIP, ToC, IO
Interface Circuit Bitchart, System Application
Design Config, PD, Typical Logic Design
circuits, Standard
Documents, etc.,

Interface Circuit Application Logic

Production Check Production Check/Test

YES YES
Review Review
Comments Comments

NO NO
Design O/P, SIP, ToC, IO
Interface Circuit Bitchart, System Application Logic
Verification Config, PD, Typical Verification
circuits, Standard
Documents, Checklist
etc.,
YES Design Design YES
Error Error
Log Log
NO NO
Inputs for Interface Circuit Design

[Link] Signal Interlocking Plan

[Link] Front Plate Drawing

[Link] supply scheme

[Link] room building layout

[Link] Configuration

[Link] rack termination details

[Link] of any additional interlocking equipment interfaced

with MLKII
 Outputs of Interface Circuit Design

• Interface Drawings consist of:

1. Index
2. Relay Room Floor Plan
3. Configuration drawing
4. Serial Ports wiring details
5. Address select PCB, Jumper settings and Keying plug details
6. CPU & PS PCB wiring detail
7. I/O Bit charts
8. Nonvital & Vital board wiring
9. All field gear driving circuit
10. Power supply distribution drawing
11. Fuse chart
12. Rack assembly drawings
13. Interconnection details
14. Contact analysis
Interface Circuit O/P
(Click Here)
Inputs for Application Logic Design

• Inputs required are:

1. Approved Signal Interlocking Plan

2. Approved Table of control

3. Approved Point control table

4. System Configuration
 Outputs of Application Logic Design
• Application Logic circuit Design consist of:
20. UCR Logic
1. Revision history 21. TSR Logic
2. Program title
22. Signal ALSR, JSLR, UYR Logic
3. Local i/o
4. Communication section 23. Point WLR Logic
5. Boolean section 24. Signal HR & DR Logic
6. Timer section 25. Crank Handle & Siding Control Logic
7. Log bit section 26. Level Crossing Control Logic
8. Numeric section 27. Block Logic
9. Panel PC Change over Logic
28. Axle Counter Reset Logic
10. Operator PC Serial Input Timer Logic
11. Push Button Logic 29. Signal Indication Logic
12. Emergency Operation Push Button Logic 30. Point & Overlap Indication Logic
13. EGNR & UCSR Logic 31. Track Circuit Indication Logic
14. Signal NNR & NRR Logic 32. Signal Failure Alarm Logic
15. Overlap Logic 33. Point Failure & Button Stuck Alarm Logic
16. Point NLR & RLR Logic
34. System Initialization & Link Status Logic
17. Point Chain Logic Application Logic O/P
18. Point WNR & WRR Logic 35. FCOR Logic
(Click Here)
19. Point Detection Logic 36. Card file Identification Logic
 Logic Compilation

•logic compiler - PC-based tool checks application source file for errors and generates
application file for transfer to CPU flash EPROMs and also generate listings &
installation information.
 Logic Compilation
MLK II LOGIC COMPILER DEFAULT EXTENSIONS
➢ application source ML2 or TXT
➢ listing MLL
➢ application MLP

• Program saved as “PROGRAM.ML2” or “[Link]” file name

• Compilation carried out by MLKIICOMP
• Result of compilation will be two files viz. “[Link]” & “[Link]”
• “MLL” - listing file gives errors, warnings, no. of BITs used, no. of time one bit used and also unique
identification called as “CHECKSUM” & “CRC”
• “MLP” - data file to load in memory of CPU using MLK II Maintenance tool

TXT FILE MLL FILE

(Click Here) (Click Here)
 Factory Acceptance Test Process

What is FAT?
• FAT is Factory Acceptance Test and shall be tested in Factory environment with
simulation setup

Purpose of FAT
• Ensures the Electronic Interlocking system fulfils the station interlocking
requirements & station control Table
• It reduces the error & risks at Site and save time at site testing

12
Inputs:
• Station SIP, RCC,CCIP & Cross table
• Microlok II files (.ml2,.mll,.mlp, As designed)
• Simulation Setup
Outputs:
• Station Interlocking Software (As tested)
• FAT certificate

13
 Factory Acceptance Test Process

Interface Circuit Customer

Delivery to Interface Circuits Approved
release for Site
Customer Application Logic

Internal FAT
Site Wiring
Completion

YES
ATIR D
Wiring Test
NO
Customer FAT

YES
ATIR D

NO
 Following Test are carried out as part of Control table Test

1. Signal & route - clear

2. Signal & route – Indication
3. Point Indication
4. CH & LC indication
5. Track Occupied Indication
6. Break test and Mid stroke test – Point (Control and Indication)
7. Break test – Track
8. Break test – Ahead signal aspect, CH, LC etc.
Maintenance Operator
PC VDU 9. Conflict signals and routes
Microlok II
10. Reverse move
11. Jump moves
Simulator
Panel
12. Normal release

Simple Block Diagram (FAT Setup)

 Following Test are carried out as part of Control table Test

13. Emergency release

14. Approach release
15. Overlap release
16. Sequential route release (Train move)
17. Sectional route release (applicable to major stations/Yards)
18. Back lock test
19. Signal Replacement track test
20. SM’s control
Maintenance Operator
PC VDU 21. Cross test with all other elements
Microlok II 22. Special Tests

Simulator
Panel

Simple Block Diagram (FAT Setup)

 Results
All the above test results shall be logged and signed off in a marked up copy of the:
• Control Table
• Activities Event log
• Acceptance Test Incident Report (ATIR) if required

Click Here to see all FAT

Documents
 Site Acceptance Test Process

What is SAT?
• SAT is Site Acceptance Test and shall be tested at site with Full functional equipment
and simulation panel

Purpose of SAT
• Ensures that all the equipments installed at site are functional correctly as per
approved system configuration & station interlocking requirements
• SAT mainly involves the System integrity and functional testing of all equipments
• Ensures overall system safety and error free system is delivered to client
Inputs:
• Station SIP, RCC,CCIP & Crosstable
• Microlok II files (.ml2,.mll,.mlp, As designed)
• Wiring Design

Outputs:
• Provide Error Free System (Ready for Commissioning)
• SAT certificate
• .

19
 Site Acceptance Test Process

Pre SAT Checklist,

Site Integrity Test Pre Comm Checklist, SAT
Checksum CRC
Certificate, etc.,

YES
ATIR D

NO

Commissioning
Commissioning Certificate
Control table Validation ensure the following Test are carried out from

• Signal & route - clear

• Signal & route – Indication
• Point Indication
• CH & LC indication
• Track Occupied Indication
• Break test and Mid stroke test – Point (Control and Indication)
• Break test – Track
• Break test – Ahead signal aspect, CH, LC etc.
• Conflict signals and routes
• Reverse move
• Jump moves
• Normal release
Control table Validation ensure the following Test are carried out from

• Emergency release
• Approach release
• Overlap release
• Sequential route release (Train move)
• Sectional route release (applicable to major stations/Yards)
• Back lock test
• Signal Replacement track test
• SM’s control
• Cross test with all other elements
• Special Tests
 Results
All the above test results shall be logged and signed off in a marked up copy of the:
• Control Table
• Activities Event log
• Acceptance Test Incident Report (ATIR) if required

Click Here to see all SAT Documents

Electronic Interlocking Design -Modification
 START

Modified Inputs Modified

SIP, ToC, PD, Typical Received from
Circuits etc., Customer Input
Customer (Click Here)

Review the Inputs

Interface Circuit Application Logic

Design Design
 Design & Verification Process

D
SIP, ToC, IO
Interface Circuit Bitchart, System Application
Design Config, PD, Typical Logic Design
circuits, Standard
Documents, etc.,
Interface Circuit Application Logic
Production Production
Check Check/Test

YES Review Review YES

Comme Comme
nts nts
NO Design O/P, SIP, NO
ToC, IO Bitchart,
Interface Circuit System Config, PD, Application Logic
Verification Typical circuits, Verification
Standard
Documents,
Checklist etc.,
YES Design Design YES
Error Error
Log Log
NO NO
Inputs for Interface Circuit Modification

[Link] Signal Interlocking Plan

[Link] Front Plate Drawing

[Link] I/O Bitchart

 Changes in Interface Circuit

1. I/O Circuits
2. Signal repeater relay & lighting circuit
3. Point & crank handle control circuit
4. Relay rack layout
5. Terminal chart
6. Power Circuits
7. Fuse & terminal chart
8. Contact analysis
9. Control panel led identification layout

Modified
Interface Circuit
(Click Here)
Inputs for Application Logic Design

• Inputs required are:

1. Modified Signal Interlocking Plan

2. Modified Table of control

3. Modified Point control table

 Outputs of Application Logic Design
• Application Logic circuit Design consist of:

1. File Naming Change

2. Revision History
3. Program Title Modification
4. Local I/o Modification
5. Communication Section Modification
6. Boolean Section Modification
7. Timer Section Modification
8. Log Bit Section Modification
9. Numeric Section Modification
10. Panel Pc Change Over Logic – No Change
11. Operator Pc Serial Input Timer Logic
12. Push Button Logic
13. Emergency Operation Push Button Logic
14. Egnr & Ucsr Logic
15. Signal Nnr & Nrr Logic
16. Overlap Logic – No Change
17. Point Nlr & Rlr Logic
18. Point Chain Logic – No Change
19. Point Wnr & Wrr Logic
20. Point Detection Logic – No Change
Outputs of Application Logic Design
20. Ucr Logic
21. Tsr Logic
22. Signal Alsr, Jslr, Uyr Logic
23. Point Wlr Logic
24. Signal Hr & Dr Logic
25. Crank Handle & Siding Control Logic
26. Level Crossing Control Logic – No Change
27. Block Logic – No Change
28. Axle Counter Reset Logic - No Change
29. Signal Indication Logic
30. Point & Overlap Indication Logic – No Change
31. Track Circuit Indication Logic
32. Signal Failure Alarm Logic
33. Point Failure & Button Stuck Alarm Logic
34. System Initialization & Link Status Logic
35. Fcor Logic
36. Card File Identification Logic – No Change Modified
Application Logic
(Click Here)
 Comparison of Application Logic Modification

Before starting the internal testing, the updated logic is to be compared with the comparator and the
highlighted section shall be verified internally to ensure the logic has been modified only for the Input
Modification. Any updates and modifications found shall be updated in the design and the revision
history is also to be updated in the program.

Compared Application Logic reference file

(Click Here)
 Factory Acceptance Test Process

Customer
Design Delivery Interface Circuits Approved
to Customer release for Site
Application Data

Internal FAT
Site Wiring

Can Be Done
During NI
YES
ATIR D
Wiring Test
NO

Customer FAT

YES
ATIR D
Click Here to see all FAT
Documents NO
 Site Acceptance Test Process

Site Integrity Test SAT

Can Be Done During NI

Commissioning

Click Here to see all SAT Documents