Full IC Design Flow Tutorial

1. Cadence Launch
Run the following command to start virtuoso:
Right click on the desktop and select open terminal; Type cd at the
cursor on the terminal command line, and then click Enter，and then follow :
mkdir xxx(your number)
cd xxx(your number)
virtuoso &
This will open Cadence! which is also known as the CIW window.

2. Creating a Schematic View

In Cadence, there is a relatively straightforward hierarchical organizational
structure. Libraries (the furthest left column in the library manager) are collections
of Cells, and Cells are collections of Views.
The first thing that you will need is a new library. To do this, go to the CIW click
File → New → Library. A new window will pop up. Type lib1 in the name
field and press OK.
 At this point, Cadence will prompt you for something called a Technology File.
The technology file is a library or group of libraries that all cell views inside of your
new library will automatically reference. This basically means that you will not have
to import models every time you run a new simulation.
To import the technology file for this class, click the “Attach to an
existing techfile” button, press ok, and use the drop down menu to select
“gpdk045”. This stands for generic process design kit, 45nm refers to the
minimum feature size available.

Now that you have a library, you can create your first schematic. In CIW click
File → New → CellView. When prompted, name the new cell view inverter
and select “schematic” from the drop-down menu and "schematic" should
auto-fill under View. Click OK, and the schematic editor should open up. Now we
can build a virtual representation of our circuit at the transistor level.

To instantiate circuit elements in the schematic, press the ‘I’ key. This will
bring up the Add Instance window and the Component Browser. To put an NMOS
transistor into your schematic, go to Component Browser, change Library to
gpdk045, tick the “Flatten” box, and scroll down to nmos1v. This selection
should auto-fill in the Add Instance window. You can also type these references
into the fields manually. As soon as you do this, you will be prompted with lots of
new options. What you are actually doing at this point is instantiating a
parameterized cell, or P-cell for short. You can parameterize the transistor gate
width, length, and fingers. Your choices will be reflected in the schematic. For now,
let’s stick with a minimum-sized transistor with a Length of 45nm and a Width of
120nm. Press the “hide” button or hit the Enter key in the Add Instance menu
and click down the transistor into your schematic. Press the ‘Esc’ key to stop
adding components. If you ever want to change a p-cell’s properties after placing
it in the schematic, click on it and press the ‘q’ key.

Following those same instructions, instantiate a PMOS transistor (pmos1v)

with a 45nm length and a 120nm width. In addition, instantiate global symbols
“vdda” and “gnd” from the analogLib library.
Now that all of our components are in the schematic, you will need to connect
them together. Press the ‘w’ key to open up the “Add Wire” window. This will
allow you to make connections between nodes. Simply click on the red squares
(the contacts) in the schematic view, and make the connections needed for an
inverter circuit. Remember to connect the bulk terminals of the NMOS and PMOS
devices to gnd and vdda respectively. You can use ‘s’ to snap the wire to the
nearest contact, indicated by a diamond on the schematic.
 To navigate the schematic, use the arrow keys on the keyboard to pan around.
You can zoom in/out by clicking the magnifying glass buttons on the toolbar, or
with the hotkeys control-Z/shift-Z. You can also zoom to a specific area by click-
dragging a square with the right mouse button around the region of interest. If the
circuit ever disappears, or if you want to take a look at the whole circuit, press the
‘f’ key.
The last thing that you need is two pins to indicate the input and output of your
inverter. This way you cell view can interface with higher level schematics (more
on this later). Press the ‘p’ key to open up the “Add Pins” window, type the
names of your pins with spaces between them (I used in and out here, you can
use whatever you like). Make sure that you select “input” in the direction drop-
down menu for “in” Add pin windows, and“Output in the direction drop-
down menu for “out” Add pin windows. click “Hide”, place your pins in the
schematic, and wire them up.

If you followed the instructions carefully, your schematic should look

something like this:
 When it does, press the “Check and Save” button (it looks like a box with
a check mark). Leave the schematic editor open for now; we’ll need it for the later
portions of the lab.
One more quick thing to note before you create a symbol. Sometimes it is
useful to label nodes instead of directly connecting them with a wire. To connect
two nodes, just label them with the same name! To create a label, press the ‘L’
key, type in the desired node name, and click on the wire in the schematic.
3. Creating a Symbol View
Now that your schematic is finished, we need create a symbol for it.
Click Create → Cellview → From Cellview
A pop to create symbol appears. After you press OK, a new pop-up title
"Symbol Generation Options" shows up. Press OK here too.

Notice that vdda and gnd do not show up here. As mentioned earlier, those
are global pins that are shared throughout the design automatically.
After you press OK, you will have the opportunity to place the missing pins in
the symbol editor. Click to place the pins, rotating by clicking the right mouse button
if needed. Note that the red dot is the actual point where a wire will connect, so put
it towards the edge of the symbol. Draw various shapes using the shape buttons
at the top to make your symbol look like an actual inverter. Save your symbol view
when finished.
4. Circuit Simulation with ADE
Before you simulate anything, you will need to build a test bench for your
inverter. To do this, create a schematic called “inverter_tb” in the lib1 library.
Once you do that, instantiate a cell called “vpulse” from the analogLib library.
When you instantiate the voltage source, enter the string “Vin” for the “DC
Voltage” property. Assigning parameters to variables allows you to change them
easily and sweep them in the simulator. Set the two vpulse voltage levels to 0V
and 1V, and set the rise and fall times to 10ps. The pulse width should be 10ns
and the period should be 20ns. Now, instantiate the inverter symbol that you
created only moments ago. Don’t forget to connect vdda to a 1V supply! The
“vdc” source in the analogLib library should be used here. Finally, connect all
the circuit components together properly with wires. You should also label the input
and output nets to easily identify them when viewing the simulation results (again,
press ‘l’). Your testbench schematic should look something like this:

Hit check and save like before. You will get a few warnings that you can
safely ignore.
Now you can finally set up the simulation for your inverter. Click Launch →
ADE L to open up the legendary Virtuoso Analog Design Environment (ADE). This
tool is a little bit obtuse but extremely powerful. Let’s start with two simple
simulations: a dc simulation to determine our inverter’s voltage transfer
characteristic, and a transient simulation to determine its propagation delay.
Let’s first begin by setting the design variables. Click on Variables → Edit
to open up the Design Variable Editor. Then click the “Copy From” button at the
bottom. Remember how you set the DC voltage of the vpulse source to a variable?
Here is where you can use it in your simulation. Set the default value to 1V so that
your variable window looks like this:

Now we can set up the simulation. Click on Analyses → Choose to open

the analysis window. Select “dc”, set the sweep variable to “Design
Variable”, and use “vin” as the variable name. Sweep vin from 0V to 1V with
a step size of 10mV. Click OK. Follow the same procedure to create a transient
simulation with a duration of 100ns.

To make the simulator automatically plot the desired waveforms, click

Outputs→ To Be Plotted → Select on Schematic, and click on the input
and output nodes that you labeled earlier. Remember to press ‘Esc’ after you
are done selecting the wires. Afterwards, your ADE window should look like this:
 To run the simulation, click the green “play” icon on the right side. Close
the “What’s New” popup box and the simulation will run. The input and output
waveforms should be plotted automatically.

5. Creating a Layout View

Go back to the CIW window and create a new inverter cell view in lib1 library，
as you did previously. This time, select the “layout” option as the tool. This will
create an empty layout editing view.
First, press the ‘e’ key to get to the display options menu. We will need to
change the snap spacing so we can move our cursor with sufficient resolution.
Make sure your grid matches 5nm requirement. A layout that does not comply grid
will not pass DRC checks and will require re-layout. You can change display levels
to stop at 10 so that we don’t run into any problems. As shown in the figure below.
 First, we’ll draw rulers to specify the outline of the inverter. Press the ‘k’ key
to draw rulers, and make a 0.8 x 1.4 micron rectangle.
Then, we’ll make metal lines for the power supply. To specify the material,
we can go to the “Layers” toolbox on the left side. Find “Metal1” and click on
the layer whose purpose is drawing. Now press the ‘p’ key to create a path. A
“create path” dialog box should pop up; if it doesn’t, hit ‘F3’ on your
keyboard. Change the path width to 0.2 microns. Now draw the paths so that
they are flush with the top and bottom of your rulers. Click once to start a path,
double click to end a path.
 Now press the ‘i' key to instantiate some transistors. Find the layout view
of the NMOS and PMOS you drew in schematic, set the length and width to match,
and place the devices in your layout.
This may be the first time you’ve seen a MOSFET laid out! Figure out what
the different layers mean. Where are the source, gate, and drain? Where is the
channel?
Draw 0.06 micron Metal1 traces to connect the drains of the transistors
together, and to connect the sources to the power rails. Draw a 0.045 micron
“Poly” trace to connect the transistor gates together.
Polysilicon is quite resistive; we’d want to switch to metal traces as soon as
possible. To do this, there needs to be a via between polysilicon and metal lines.
To do this, go to the menu and click Create → Via. Make sure the “via
definition” is “M1_PO”. Rotate it and place it onto the layout. After you’ve
finished the steps, your layout should look like this:

Remember that MOSFETs are 4-terminal devices. We’ve connected the

source, drain, and gates – what happens to the bulk terminal?
In an NMOS, the bulk is the substrate, which is implicitly shown in black. A
PMOS must be placed in an N-well to operate properly. The N-well is automatically
placed with the PMOS, but is too small to make any connections to.
 To fix this, we need to draw a bigger N-well. Find the “Nwell” drawing layer
and press the ‘r’ key to draw a rectangle that includes the PMOS and the top
metal line.
To make the bulk connections, we must connect the top power rail to the N-
well, and the bottom power rail to the substrate. In a MOSFET, a connection to
the substrate requires four things:
1) Initial thinning down of the oxide (layer “Oxide”).
2) Cutting a hole through the oxide (layer “Cont”).
3) Doping the substrate to reduce resistance (layer “Nimp”/”Pimp”).
4) Depositing metal for a connection (layer “Metal1”).

Fortunately, this pdk provides a utility for connections to the [Link] way
to make contact to the terminal is to use the properties of Nmos and Pmos. After
you’ve finished the steps, your setting should look like two picture below:
Bodytie Type—Detached---Top Tap (Bottom Tap)

Finally, we draw 0.12 micron metal paths extending the inverter input and
output connections to the far left and far right of the cell boundary. If you wish, you
may delete the rulers used to specify the distances between contacts for the
substrate connections.

6. Adding Pins to the Layout View

Remember that, in the schematic and symbol, we had pins for the input and
output of the inverter. Select the “Metal1” layer, then on the menu bar, click
Create → Pin. Type “in” for the terminal names and setting should look like
follow picture, then type “out” for the terminal names and setting should look like
following next picture.
Now you can draw two metal squares onto the input and output of the inverter.

We also need to label the pins and global nodes. Press the ‘l’ key to create
labels. In the text box, type in “vdda! gnd!”, change the height to 0.06, and
change the layer to Metal1. Now you can label the terminals.
7. Design Rule Checking (DRC)
The DRC checker verifies that your drawn layers obey all of the design rules.
These design rules are provided by the IC foundry to ensure that the IC devices
perform to specification. The design rules document can be found in gpdk45:
From the Virtuoso layout menu bar, click Assura → Technology. In the
“Assura Technology File” dialog box, enter the following:
/mnt/pdk/analog/gpdk045_v3_5/assura_tech.lib

Click OK. In the Virtuoso menu bar, click Assura → Run DRC. Switch the
“Technology” option to “gpdk045_av”. Your “Run Assura DRC” menu
should look like this:

Now click OK to run the DRC checker! The results should be displayed in
the Virtuoso window. You’ll probably have some problems – the errors may be
really difficult to understand. Try to decode what needs to be fixed (usually has
to do with spacing between components and paths not flush with each other).
Ask your GSI if you’re stuck. When there are no errors, your Virtuoso window
should look like this:

8. Layout versus Schematic Verification

Now, we need to check to see whether the transistors we placed here actually
match up with the transistors we placed in schematic. To do this, we run a layout
vs. schematic (LVS) checker.
Click OK. In the Virtuoso menu bar, click Assura → Run LVS. Switch the
“Technology” option to “gpdk045”. Your “Run Assura LVS” menu should
look like this:

Click OK to run LVS. If your layout matches your schematic, you will see the
following message:
 If you have any LVS errors, please correct them by making the appropriate
adjustments to your layout. Remember to run DRC check again to verify that the
update doesn’t violate any design rules.
At this point, your layout now passes DRC and LVS – a huge milestone in
the IC design process. Next, we will examine how the physical placement of
transistors (layout) impacts circuit performance.
9. Parasitic Extraction with Assura
This tool allows us to extract parasitic resistances and capacitances from the
layout view. From the menu, click Assura → Open Run, and make sure “Run
Name” lists the current cell you are working on (“inverter”). Click OK.
Fill-up the form as below and press. Make sure you are pointing to you local
gpdk and not to the one in the staff folder. You do not have permission to access
it.
Now, click Assura → Quantus QRC. If you don’t see this tab make sure
your cadence_setup described on page-1. Adjust the settings in the setup,
extraction, and netlisting tabs to match the screenshots below.
 _____

Make sure you have entered gnd! as the REF node. Else the extraction will result
in dangling nodes.
 Click OK to run the parasitic extractor. A successful extraction should give
you this message:

Return to the library manager, and your inverter cell should have a new view
named “av_extracted”. You can zoom in and see all the little parasitics! The
extracted view looks something like below:
Once you zoom-in you will find tiny capacitors as below:

10. Parasitic Extracted Circuit Simulation

After extracting the layout note that a new cell view named “av_extracted”
was added in the Library manager. To show the summation of capacitance
associated with each node go to the schematic editor window and go to <Launch
-> Plugins -> Parasitics>. In the Parasitics menu go to Setup. In the “Setup
Parasitics” window, make sure that all the fields are set similar to Figure below
and press OK.
 Go to <Parasitics -> Show Parasitics>. Note that the tool added the
summation of capacitance associated with each node to the schematic as shown
in Figure above.
We would like to simulate the extracted layout. First, create a new cell view
for your “inverter_tb” cell in lib1 library. This time, select the “config” tool,
making sure the option says “Hierarchy Editor”.

In the “New Configuration” window, click the “Use Template” button

and select “spectre” as the template. Change the “Top Cell View” field
from “myView” to “schematic”. Now click OK. In the resultant window’s menu
bar, click View → Update. Your windows should look like the screenshots below.

Now, right click on the inverter cell and select Set Cell View →
av_extracted. Update the hierarchy again, then save the configuration.
 Go back to the CIW window and select File → open inverter_tb “config”
cell view. This prompts you to open the hierarchy configuration (which is what we
just edited) and/or the top cell view. If you kept the configuration window open,
just open the top cell view.
You should now see your “inverter_tb” config view. Click on the inverter
symbol, then press the ‘shift+e’ key to descend into the inverter cell. Your
regular layout has now been replaced with the extracted one. Press the ‘b’ key
to ascend one level back to the top level schematic.
Launch “ADE L” again. Configure ADE to run the DC sweep and transient
simulation again. Find the DC gain and the propagation delays. Are the
simulation results different now?