COA Answer Key

Solved according to marks for all questions in the uploaded question bank

Computer Organization and Architecture

Prepared from the uploaded file COA_Topics_Questions.html

This document gives mark-wise answers for all 83 questions found in the file. Numerical answers include the
final result and the working needed for exam writing.
Module 1 - Computer Fundamentals
 Q1. Convert (255.75)₁₀ to Binary, Octal, and Hexadecimal. Show all division/multiplication steps. (5M)
 Q2. Convert (178.625)₁₀ to Binary, Octal, and Hexadecimal. (5M)
 Q3. Convert (3F8.A4)₁₆ to Binary and Decimal. Also convert to Octal. (5M)
 Q4. Represent +75 and −75 using 8-bit Sign Magnitude, 1's Complement, and 2's Complement notation.
(5M)
 Q5. Add (+63) and (−30) using 8-bit 2's complement. Check for overflow and verify the result. (5M)
 Q6. Subtract (−45) − (+28) using 2's complement method with 8-bit representation. (5M)
 Q7. Compare Sign Magnitude, 1's Complement, and 2's Complement methods. State why 2's complement
is preferred in ALUs. (5M)
 Q8. Draw logic symbols and write truth tables for NAND, NOR, and EX-OR gates. Show how NAND gate
can implement AND, OR, and NOT operations. (5M)
 Q9. Draw and explain the Von Neumann model of a computer. State its key characteristics and limitations.
(5M)
 Q10. Explain the basic organization of a computer system. Describe the role of each component: ALU, CU,
Memory, I/O. (5M)

Module 2 - ALU Operations

 Q11. Perform the following: (a) (10110101)₂ + (11001011)₂ (b) (10110101)₂ − (01101010)₂ (5M)
 Q12. Perform: (a) (357)₈ + (462)₈ (b) (A3F)₁₆ + (7C8)₁₆. Show all carry operations. (5M)
 Q13. Multiply (13)₁₀ × (6)₁₀ using Booth's algorithm. Show the table with all 4 steps and verify the result.
(7M)
 Q14. Multiply (12)₁₀ × (−5)₁₀ using Booth's algorithm (5-bit representation). Verify: result should be −60.
(7M)
 Q15. Multiply (−7)₁₀ × (−4)₁₀ using Booth's algorithm. Show all intermediate values of A, Q, and Q[-1]. (7M)
 Q16. Multiply (−15)₁₀ × (7)₁₀ using Booth's algorithm. State the operation applied at each step. (7M)
 Q17. Draw the flowchart for Booth's multiplication algorithm and explain why it is more efficient than simple
binary multiplication. (5M)
 Q18. Divide (21)₁₀ by (5)₁₀ using the Restoring Division algorithm. Show each step with A and Q values.
(8M)
 Q19. Compare Restoring and Non-Restoring division algorithms. Explain which is faster and why. (5M)
 Q20. Draw flowchart for Non-Restoring Division algorithm and implement for (13)₁₀ ÷ (3)₁₀. Verify your
result. (8M)
 Q21. Apply Non-Restoring Division to divide (25)₁₀ by (5)₁₀ using 4-bit representation. Show all step-by-step
operations. (8M)
 Q22. Divide (17)₁₀ by (3)₁₀ using Non-Restoring Division. State the action taken at each step (shift+add or
shift+subtract). (8M)
 Q23. Represent (−35.625)₁₀ in IEEE 754 Single Precision format. Give the final 32-bit binary string and hex
equivalent. (5M)
 Q24. Represent (+118.625)₁₀ in IEEE 754 Single Precision format. Show the sign, biased exponent, and
mantissa fields. (5M)
 Q25. Find the decimal value of the IEEE 754 single precision bit pattern: 0 10000010
10100000000000000000000 (5M)
 Q26. Explain IEEE 754 Double Precision format. Compare with Single Precision in terms of range,
precision, and bit fields. (5M)
Module 3 - Processor Organization & Control Unit Design
 Q27. Draw and explain the internal architecture of the 8086 microprocessor. Describe the functions of BIU
and EU. (8M)
 Q28. Explain the register organization of 8086. Classify registers and state the special purpose of each
general-purpose register. (5M)
 Q29. If CS = 2500H and IP = 0300H, what is the physical address of the next instruction? Explain the
concept of segmentation. (5M)
 Q30. Explain the instruction formats of 8086. Draw the general instruction format and explain each field:
opcode, MOD, REG, R/M. (5M)
 Q31. Describe the instruction execution cycle of 8086 with a diagram. How do BIU and EU overlap their
operations? (5M)
 Q32. Explain all addressing modes of 8086 with suitable assembly language examples. State the EA
formula for each mode. (8M)
 Q33. Differentiate between Register Indirect, Based, and Based Indexed addressing modes with examples.
When would you use each? (5M)
 Q34. Explain Microprogrammed Control Unit with a neat block diagram. Describe all components and
explain the working sequence. (8M)
 Q35. Explain Hardwired Control Unit with a diagram. State its advantages over microprogrammed CU. (5M)
 Q36. Compare Hardwired and Microprogrammed Control Units on: speed, design complexity, flexibility,
ease of modification, and cost. (5M)
 Q37. Differentiate Horizontal and Vertical Microinstructions with examples. State the trade-off between word
length and parallelism. (5M)
 Q38. Explain microinstruction sequencing and execution. How does the μPC determine the next
microinstruction address? (5M)
 Q39. Compare RISC and CISC architectures in detail. State design principles, advantages, and one real-
world example of each. (5M)
 Q40. Explain the design issues of RISC architecture. Why is RISC preferred for embedded systems? (5M)

Module 4 - Memory Systems Organization

 Q41. Explain Memory Hierarchy with a neat pyramid diagram. Describe the characteristics (speed, cost,
capacity) at each level. (7M)
 Q42. Cache access time = 10 ns, main memory = 100 ns, hit ratio = 0.95. Find (a) effective access time (b)
speedup compared to no cache. (5M)
 Q43. Explain memory parameters: capacity, access time, cycle time, bandwidth, and cost per bit. How do
they affect system design? (5M)
 Q44. Compare Static RAM (SRAM) and Dynamic RAM (DRAM) in terms of construction, speed, cost,
refresh requirement, and applications. (5M)
 Q45. Explain the different types of ROM: PROM, EPROM, EEPROM, and Flash ROM. State how data is
written/erased in each. (5M)
 Q46. A computer has 64MB main memory, 32KB cache, and block size 8 bytes. Find the memory address
format for: (a) Direct Mapping (b) Fully Associative Mapping. (8M)
 Q47. A system has 16MB main memory, 64KB cache, and 16-byte blocks. Find address format for: (a)
Direct Mapping (b) 2-Way Set-Associative Mapping. (8M)
 Q48. For a system with 32MB MM, 16KB cache, 8B block size, derive the address format for all three:
Direct, 4-Way Set-Associative, and Fully Associative. (10M)
 Q49. Explain and compare Direct Mapping, Set-Associative Mapping, and Fully Associative Mapping cache
techniques with diagrams. (8M)
 Q50. Explain write-through and write-back (copy-back) cache write policies. What is the advantage of write-
back over write-through? (5M)
 Q51. Explain the paging mechanism for virtual memory with a neat diagram. Define: page, frame, page
table, page fault, TLB. (8M)
 Q52. A system uses 32-bit virtual address with 4KB page size. (a) How many pages can the virtual address
space hold? (b) How many bits are used for page number and offset? (5M)
 Q53. Explain LRU, FIFO, and Optimal page replacement algorithms. Give an example with a reference
string to show page faults. (7M)
 Q54. Explain segmentation in virtual memory. Describe the segment table structure and physical address
translation. (5M)
 Q55. Compare Paging and Segmentation in terms of: unit size, fragmentation type, sharing, protection, and
hardware support. (5M)
 Q56. Explain the cache coherency problem in multiprocessor systems. Describe any two techniques to
resolve it. (5M)
 Q57. Explain the MESI cache coherency protocol. Describe the four states and state transitions with
examples. (Self-Study) (5M)
 Q58. Explain interleaved memory organization. Differentiate between low-order and high-order interleaving
with diagrams. (5M)
 Q59. Explain Associative Memory (Content Addressable Memory). Draw its structure and state its
applications in cache and TLB. (5M)

Module 5 - I/O Organization

 Q60. Explain the types of buses in a computer system. Describe the function of the Address, Data, and
Control buses. (5M)
 Q61. Explain ISA, PCI, and USB bus standards. Compare them with respect to speed, data width, plug-
and-play, and hot-plug capability. (5M)
 Q62. Explain Bus Arbitration. Describe Daisy Chain, Counter-Based (Polling), and Independent Request
methods with diagrams. (5M)
 Q63. Compare centralized and distributed bus arbitration techniques. State the advantages of Independent
Request method. (5M)
 Q64. Explain the I/O module structure and its role in interfacing I/O devices with CPU and memory. (5M)
 Q65. What is an I/O Channel? How does it differ from a simple I/O controller? Explain selector and
multiplexor channel types. (5M)
 Q66. Explain I/O processor architecture. How does it offload I/O management from the main CPU? (5M)
 Q67. Explain and compare Programmed I/O, Interrupt-driven I/O, and DMA. Draw block diagrams for
Interrupt and DMA. State the best use case for each. (7M)
 Q68. Explain DMA (Direct Memory Access) in detail. Draw the DMA controller block diagram and describe
Cycle Stealing mode. (7M)
 Q69. Explain Interrupt-driven I/O. Describe the steps from interrupt request to interrupt service routine
completion. What is interrupt vectoring? (5M)

Module 6 - Parallel Processing

 Q70. Explain the three operating modes of the 80386DX processor: Real Mode, Protected Mode, and
Virtual 8086 Mode. State key features of each. (5M)
 Q71. Explain the 5-stage instruction pipeline (IF, ID, EX, MEM, WB) with a timing diagram. Derive the
speedup formula for an n-stage pipeline. (7M)
 Q72. Explain Superscalar architecture. How does it achieve IPC > 1? Compare with a simple single-
pipeline processor. (5M)
 Q73. Draw and explain all three types of pipeline hazards with examples. State the methods to resolve
each type. (8M)
 Q74. Explain data forwarding (bypassing) technique to resolve RAW hazards. Draw a diagram showing
data path from EX stage to EX stage input. (5M)
 Q75. Explain branch prediction techniques: static (always not-taken) and dynamic (2-bit saturating counter).
What is Branch Target Buffer (BTB)? (5M)
 Q76. A 5-stage pipeline has a clock cycle of 2 ns. For 100 instructions with 10 data hazards (each requiring
2 stall cycles) and 5 branch hazards (3 stall cycles each), find total execution time. (5M)
 Q77. 80% of a program can be parallelized. Find the speedup when using (a) 4 processors (b) 8 processors
(c) infinite processors. What is the maximum achievable speedup? (5M)
 Q78. A program takes 100 seconds. 60 seconds of it can be parallelized. Find the speedup with 4
processors. How many processors needed for speedup of 3? (5M)
 Q79. State and explain Amdahl's Law. What does it imply about the limits of parallel processing? Explain
with a graph. (5M)
 Q80. Explain Flynn's classification of computer architectures. Draw diagrams for all four types (SISD, SIMD,
MISD, MIMD) and give one real-world example each. (5M)
 Q81. Compare SIMD and MIMD parallel architectures. State why MIMD is the most commonly used model
in modern computers. (5M)
 Q82. Explain the concept of parallel processing. What are its advantages? Describe the types of
parallelism: bit-level, instruction-level, task-level. (5M)
 Q83. Write a short note on Superscalar architecture with reference to the Pentium processor as a case
study. (Self-Study topic) (5M)
Module 1 - Computer Fundamentals
Q1. Convert (255.75)₁₀ to Binary, Octal, and Hexadecimal. Show all division/multiplication
steps.
Marks: 5M | Type: Numerical
255.75_10 = 255 + 0.75.
Integer part:
255 / 2 = 127 r1
127 / 2 = 63 r1
63 / 2 = 31 r1
31 / 2 = 15 r1
15 / 2 = 7 r1
7 / 2 = 3 r1
3 / 2 = 1 r1
1 / 2 = 0 r1
So 255_10 = 11111111_2.
Fractional part:
0.75 x 2 = 1.50 -> 1
0.50 x 2 = 1.00 -> 1
So .75_10 = .11_2.
Binary = 11111111.11_2.
Octal by grouping 3 bits: 111 111 111 . 110 = 377.6_8.
Hex by grouping 4 bits: 1111 1111 . 1100 = FF.C_16.
Final answer: 11111111.11_2 = 377.6_8 = FF.C_16.

Q2. Convert (178.625)₁₀ to Binary, Octal, and Hexadecimal.

Marks: 5M | Type: Numerical
178.625_10 = 178 + 0.625.
178 = 10110010_2 (128 + 32 + 16 + 2).
0.625 x 2 = 1.250 -> 1
0.250 x 2 = 0.500 -> 0
0.500 x 2 = 1.000 -> 1
So .625_10 = .101_2.
Binary = 10110010.101_2.
Octal: 101 100 101 . 101 = 262.5_8.
Hex: 1011 0010 . 1010 = B2.A_16.
Final answer: 10110010.101_2 = 262.5_8 = B2.A_16.

Q3. Convert (3F8.A4)₁₆ to Binary and Decimal. Also convert to Octal.

Marks: 5M | Type: Numerical
3F8.A4_16 to binary:
3 = 0011, F = 1111, 8 = 1000, A = 1010, 4 = 0100.
So 3F8.A4_16 = 0011 1111 1000.1010 0100_2 = 1111111000.10100100_2.
Decimal value:
3F8_16 = 3 x 16^2 + 15 x 16 + 8 = 1016.
.A4_16 = 10/16 + 4/256 = 0.625 + 0.015625 = 0.640625.
So decimal = 1016.640625_10.
Octal:
1016_10 = 1770_8 and 0.640625_10 = 0.51_8.
Final answer: 3F8.A4_16 = 1111111000.10100100_2 = 1016.640625_10 = 1770.51_8.

Q4. Represent +75 and −75 using 8-bit Sign Magnitude, 1's Complement, and 2's
Complement notation.
Marks: 5M | Type: Numerical
75_10 = 01001011_2.
+75 in 8-bit sign magnitude = 01001011, -75 = 11001011.
+75 in 1's complement = 01001011, -75 = 10110100.
+75 in 2's complement = 01001011, -75 = 10110101.
Key point: sign magnitude keeps sign bit separate, 1's complement flips all bits for negative numbers, and 2's
complement is 1's complement + 1.

Q5. Add (+63) and (−30) using 8-bit 2's complement. Check for overflow and verify the
result.
Marks: 5M | Type: Numerical
+63 = 00111111_2
-30 = 11100010_2 (2's complement)
Addition:
00111111
+ 11100010
-----------
1 00100001
Discard carry out of MSB -> 00100001_2 = 33_10.
Overflow: No, because the operands have different signs.
Final answer: 33_10.

Q6. Subtract (−45) − (+28) using 2's complement method with 8-bit representation.
Marks: 5M | Type: Numerical
-45 - (+28) = -45 + (-28).
45 = 00101101_2, so -45 = 11010011_2.
28 = 00011100_2, so -28 = 11100100_2.
Addition:
11010011
+ 11100100
-----------
1 10110111
Discard carry -> 10110111_2 = -73_10.
Final answer: -73_10, no overflow.
Q7. Compare Sign Magnitude, 1's Complement, and 2's Complement methods. State why
2's complement is preferred in ALUs.
Marks: 5M | Type: Theory
Sign magnitude, 1's complement, and 2's complement are all ways to represent signed numbers.
Sign magnitude uses one sign bit and the remaining bits for magnitude. It has two zeros (+0 and -0) and
arithmetic is awkward.
1's complement forms the negative number by inverting all bits. It also has two zeros and needs end-around
carry in addition.
2's complement forms the negative number by inverting bits and adding 1. It has a single zero, easier
subtraction, simple hardware, and no end-around carry.
That is why 2's complement is preferred in ALUs.

Q8. Draw logic symbols and write truth tables for NAND, NOR, and EX-OR gates. Show
how NAND gate can implement AND, OR, and NOT operations.
Marks: 5M | Type: Theory
Truth tables:
NAND: output is 0 only when both inputs are 1.
NOR: output is 1 only when both inputs are 0.
XOR: output is 1 when inputs are different.
Universal gate property:
NAND can implement NOT by tying inputs together, AND by NAND followed by NOT, and OR by using De
Morgan's law.
So NAND and NOR are called universal gates because any logic function can be built from them.

Q9. Draw and explain the Von Neumann model of a computer. State its key characteristics
and limitations.
Marks: 5M | Type: Theory
Von Neumann model has a single memory that stores both instructions and data. The main units are Input,
Output, Memory, ALU, and Control Unit.
The stored-program concept means instructions are kept in memory just like data.
Advantages: simple design and easy programming.
Limitation: the same bus is used for instructions and data, so the CPU can suffer from the Von Neumann
bottleneck.

Q10. Explain the basic organization of a computer system. Describe the role of each
component: ALU, CU, Memory, I/O.
Marks: 5M | Type: Theory
A basic computer system is organized around five units:
1) Input unit: accepts data and instructions.
2) Memory unit: stores programs, data, and intermediate results.
3) ALU: performs arithmetic and logical operations.
4) Control Unit: directs all operations and coordinates data flow.
5) Output unit: presents the processed result.
The CPU is mainly ALU + Control Unit + registers, while memory and I/O support the processor.
Module 2 - ALU Operations
Q11. Perform the following: (a) (10110101)₂ + (11001011)₂ (b) (10110101)₂ − (01101010)₂
Marks: 5M | Type: Numerical
(a) Binary addition:
10110101
+ 11001011
-----------
1 10000000
Result = 10000000_2 with carry out 1. If treated as 8-bit unsigned, the full sum is 110000000_2.
(b) Binary subtraction:
10110101 - 01101010 = 10110101 + 10010110 (2's complement of subtrahend)
10110101
+ 10010110
-----------
1 01001011
Result = 01001011_2 = 75_10.

Q12. Perform: (a) (357)₈ + (462)₈ (b) (A3F)₁₆ + (7C8)₁₆. Show all carry operations.
Marks: 5M | Type: Numerical
(a) Octal addition:
357_8
+ 462_8
-------
1041_8
because 357_8 = 239_10 and 462_8 = 306_10, so total = 545_10 = 1041_8.
(b) Hex addition:
A3F_16
+ 7C8_16
-------
1207_16
because A3F_16 = 2623_10 and 7C8_16 = 1992_10, so total = 4615_10 = 1207_16.

Q13. Multiply (13)₁₀ × (6)₁₀ using Booth's algorithm. Show the table with all 4 steps and
verify the result.
Marks: 7M | Type: Numerical
Use 5-bit Booth multiplication because 13 needs 5 bits in signed form.
M = 01101, Q = 00110, A = 00000, Q-1 = 0
Step 1: No-op; A=00000 Q=00011 Q-1=0
Step 2: A = A - M; A=11001 Q=10001 Q-1=1
Step 3: No-op; A=11100 Q=11000 Q-1=1
Step 4: A = A + M; A=00100 Q=11100 Q-1=0
Step 5: No-op; A=00010 Q=01110 Q-1=0
Product = 0001001110_2 = 78_10
Final answer: 13 x 6 = 78.
Q14. Multiply (12)₁₀ × (−5)₁₀ using Booth's algorithm (5-bit representation). Verify: result
should be −60.
Marks: 7M | Type: Numerical
Use 5-bit Booth multiplication.
M = 01100, Q = 11011, A = 00000, Q-1 = 0
Step 1: A = A - M; A=11010 Q=01101 Q-1=1
Step 2: No-op; A=11101 Q=00110 Q-1=1
Step 3: A = A + M; A=00100 Q=10011 Q-1=0
Step 4: A = A - M; A=11100 Q=01001 Q-1=1
Step 5: No-op; A=11110 Q=00100 Q-1=1
Product = 1111000100_2 = -60_10
Final answer: 12 x (-5) = -60.

Q15. Multiply (−7)₁₀ × (−4)₁₀ using Booth's algorithm. Show all intermediate values of A, Q,
and Q[-1].
Marks: 7M | Type: Numerical
Use 4-bit Booth multiplication because -7 and -4 fit in 4-bit 2's complement.
M = 1001, Q = 1100, A = 0000, Q-1 = 0
Step 1: No-op; A=0000 Q=0110 Q-1=0
Step 2: No-op; A=0000 Q=0011 Q-1=0
Step 3: A = A - M; A=0011 Q=1001 Q-1=1
Step 4: No-op; A=0001 Q=1100 Q-1=1
Product = 00011100_2 = 28_10
Final answer: (-7) x (-4) = 28.

Q16. Multiply (−15)₁₀ × (7)₁₀ using Booth's algorithm. State the operation applied at each
step.
Marks: 7M | Type: Numerical
Use 5-bit Booth multiplication because -15 needs 5 bits in 2's complement.
M = 10001, Q = 00111, A = 00000, Q-1 = 0
Step 1: A = A - M; A=00111 Q=10011 Q-1=1
Step 2: No-op; A=00011 Q=11001 Q-1=1
Step 3: No-op; A=00001 Q=11100 Q-1=1
Step 4: A = A + M; A=11001 Q=01110 Q-1=0
Step 5: No-op; A=11100 Q=10111 Q-1=0
Product = 1110010111_2 = -105_10
Final answer: (-15) x 7 = -105.

Q17. Draw the flowchart for Booth's multiplication algorithm and explain why it is more
efficient than simple binary multiplication.
Marks: 5M | Type: Theory
Booth's algorithm multiplies signed binary numbers by examining Q0 and Q-1.
Rules:
00 or 11 -> no operation
01 -> A = A + M
10 -> A = A - M
After each step, perform an arithmetic right shift on A, Q, and Q-1.
Why it is efficient:
- It handles signed numbers directly.
- It reduces the number of additions/subtractions when the multiplier has consecutive 1s.
- It is faster than simple repeated addition.
Flowchart idea: initialize -> check Q0,Q-1 -> add/sub/no-op -> shift -> decrement counter -> repeat -> product.

Q18. Divide (21)₁₀ by (5)₁₀ using the Restoring Division algorithm. Show each step with A
and Q values.
Marks: 8M | Type: Numerical
Divide 21 by 5 using restoring division with 5-bit registers.
A=0, Q=10101, M=00101
Step 1: Sub, negative -> restore, Q0=0; A=00001 Q=01010
Step 2: Sub, negative -> restore, Q0=0; A=00010 Q=10100
Step 3: Sub, positive -> keep, Q0=1; A=00000 Q=01001
Step 4: Sub, negative -> restore, Q0=0; A=00000 Q=10010
Step 5: Sub, negative -> restore, Q0=0; A=00001 Q=00100
Quotient = 00100_2 = 4_10
Remainder = 00001_2 = 1_10
Final answer: quotient = 4, remainder = 1.

Q19. Compare Restoring and Non-Restoring division algorithms. Explain which is faster
and why.
Marks: 5M | Type: Theory
Restoring division subtracts the divisor and, if the result becomes negative, it restores the value by adding the
divisor back.
Non-restoring division avoids the immediate restore step. Instead, it decides the next operation based on the
sign of A, so it usually performs fewer operations.
Therefore non-restoring division is faster in practice, although it is slightly more complex to understand and
implement.
Both methods produce the same quotient and remainder.

Q20. Draw flowchart for Non-Restoring Division algorithm and implement for (13)₁₀ ÷ (3)₁₀.
Verify your result.
Marks: 8M | Type: Numerical
Flowchart (text form):
Start -> Initialize A=0, Q=dividend, M=divisor, count=n
Repeat n times:
Shift left A,Q
If sign(A)=0 then A=A-M else A=A+M
If sign(A)=0 then set Q0=1 else set Q0=0
After loop, if A<0 then A=A+M
Stop

A=0, Q=1101, M=0011

Step 1: shift, A=A-M; A=1110 Q=1010
Step 2: shift, A=A+M; A=0000 Q=0101
Step 3: shift, A=A-M; A=1101 Q=1010
Step 4: shift, A=A+M; A=1110 Q=0100
Final correction: A = A + M
Quotient = 0100_2 = 4_10
Remainder = 0001_2 = 1_10
Final answer: 13 / 3 = 4 remainder 1.

Q21. Apply Non-Restoring Division to divide (25)₁₀ by (5)₁₀ using 4-bit representation.
Show all step-by-step operations.
Marks: 8M | Type: Numerical
Apply non-restoring division to 25 / 5 using 5-bit registers.
A=0, Q=11001, M=00101
Step 1: shift, A=A-M; A=11100 Q=10010
Step 2: shift, A=A+M; A=11110 Q=00100
Step 3: shift, A=A+M; A=00001 Q=01001
Step 4: shift, A=A-M; A=11101 Q=10010
Step 5: shift, A=A+M; A=00000 Q=00101
Quotient = 00101_2 = 5_10
Remainder = 00000_2 = 0_10
Final answer: quotient = 5, remainder = 0.

Q22. Divide (17)₁₀ by (3)₁₀ using Non-Restoring Division. State the action taken at each
step (shift+add or shift+subtract).
Marks: 8M | Type: Numerical
Apply non-restoring division to 17 / 3 using 5-bit registers.
A=0, Q=10001, M=00011
Step 1: shift, A=A-M; A=11110 Q=00010
Step 2: shift, A=A+M; A=11111 Q=00100
Step 3: shift, A=A+M; A=00001 Q=01001
Step 4: shift, A=A-M; A=11111 Q=10010
Step 5: shift, A=A+M; A=00010 Q=00101
Quotient = 00101_2 = 5_10
Remainder = 00010_2 = 2_10
Final answer: quotient = 5, remainder = 2.

Q23. Represent (−35.625)₁₀ in IEEE 754 Single Precision format. Give the final 32-bit binary
string and hex equivalent.
Marks: 5M | Type: Numerical
35.625_10 = 100011.101_2 = 1.00011101 x 2^5.
Sign bit = 1 because the number is negative.
Exponent = 5 + 127 = 132 = 10000100_2.
Mantissa = 00011101000000000000000.
IEEE 754 single precision = 1 10000100 00011101000000000000000.
Hex equivalent = C20E8000_16.

Q24. Represent (+118.625)₁₀ in IEEE 754 Single Precision format. Show the sign, biased
exponent, and mantissa fields.
Marks: 5M | Type: Numerical
118.625_10 = 1110110.101_2 = 1.110110101 x 2^6.
Sign bit = 0.
Exponent = 6 + 127 = 133 = 10000101_2.
Mantissa = 11011010100000000000000.
IEEE 754 single precision = 0 10000101 11011010100000000000000.

Q25. Find the decimal value of the IEEE 754 single precision bit pattern: 0 10000010
10100000000000000000000
Marks: 5M | Type: Numerical
Bit pattern: 0 10000010 10100000000000000000000.
Sign = 0, so the number is positive.
Exponent = 10000010_2 = 130, so actual exponent = 130 - 127 = 3.
Mantissa = 1.101_2 = 1 + 1/2 + 1/8 = 1.625.
Value = 1.625 x 2^3 = 13.0.
Final answer: 13_10.

Q26. Explain IEEE 754 Double Precision format. Compare with Single Precision in terms of
range, precision, and bit fields.
Marks: 5M | Type: Theory
IEEE 754 double precision uses 64 bits: 1 sign bit, 11 exponent bits, and 52 mantissa bits.
Bias = 1023.
Compared to single precision, double precision has a much larger range and higher precision because it uses
more exponent and fraction bits.
Single precision: 32 bits, bias 127, 23 fraction bits.
Double precision: 64 bits, bias 1023, 52 fraction bits.
So double precision is used when accuracy and range are more important.
Module 3 - Processor Organization & Control Unit Design
Q27. Draw and explain the internal architecture of the 8086 microprocessor. Describe the
functions of BIU and EU.
Marks: 8M | Type: Theory
8086 internal architecture is divided into the Bus Interface Unit (BIU) and Execution Unit (EU).
BIU contains the segment registers, instruction pointer, address adder, and the 6-byte prefetch queue.
EU contains the ALU, instruction decoder, general registers, and flag register.
BIU fetches instructions from memory while EU executes the current instruction, so both run in parallel.
Physical address = Segment x 16 + Offset.
This split improves speed because fetching and execution overlap.

Q28. Explain the register organization of 8086. Classify registers and state the special
purpose of each general-purpose register.
Marks: 5M | Type: Theory
8086 registers are classified as:
1) General purpose: AX, BX, CX, DX.
AX is accumulator, BX is base register, CX is count register, DX is data register.
2) Pointer and index: SP, BP, SI, DI.
SP points to top of stack, BP accesses stack data, SI and DI are used in string and indexed operations.
3) Segment registers: CS, DS, SS, ES.
4) Instruction pointer: IP.
5) Flag register: stores status and control flags.
Each register has a specific role in instruction execution and memory addressing.

Q29. If CS = 2500H and IP = 0300H, what is the physical address of the next instruction?
Explain the concept of segmentation.
Marks: 5M | Type: Numerical
Physical address = CS x 10H + IP.
CS = 2500H, IP = 0300H.
Physical address = 25000H + 0300H = 25300H.
Segmentation divides memory into 64 KB segments. The segment register gives the base and the offset gives
the location inside the segment.

Q30. Explain the instruction formats of 8086. Draw the general instruction format and
explain each field: opcode, MOD, REG, R/M.
Marks: 5M | Type: Theory
8086 instructions are variable length, usually 1 to 6 bytes.
General format contains: opcode, MOD, REG, R/M, displacement, and immediate data.
Opcode tells the operation.
MOD selects the addressing mode.
REG selects a register operand or extends opcode.
R/M selects register or memory operand.
Displacement and immediate fields are added when needed.
Q31. Describe the instruction execution cycle of 8086 with a diagram. How do BIU and EU
overlap their operations?
Marks: 5M | Type: Theory
Instruction cycle has five main steps: Fetch, Decode, Execute, Memory access, and Write back.
In 8086, BIU prefetches the next instructions into the queue while EU executes the current instruction.
This overlap is the internal pipeline of 8086.
When the queue is full, BIU waits; when the queue is empty, EU waits. This keeps the processor busy for more
of the time.

Q32. Explain all addressing modes of 8086 with suitable assembly language examples.
State the EA formula for each mode.
Marks: 8M | Type: Theory
8086 addressing modes with EA formula:
1) Immediate: operand is part of instruction.
2) Register: operand in register.
3) Direct: EA = displacement.
4) Register indirect: EA = [BX] or [BP] or [SI] or [DI].
5) Based: EA = base register + displacement.
6) Indexed: EA = index register + displacement.
7) Based indexed: EA = base + index.
8) Based indexed with displacement: EA = base + index + displacement.
Default segment is DS, but BP-based addressing uses SS.

Q33. Differentiate between Register Indirect, Based, and Based Indexed addressing modes
with examples. When would you use each?
Marks: 5M | Type: Theory
Register indirect addressing uses a register as a pointer to memory, for example MOV AL, [BX].
Based addressing uses BX or BP plus displacement, for example MOV AL, [BX+04H].
Based indexed addressing combines one base register and one index register, for example MOV AL, [BX+SI].
Use register indirect for simple pointers, based for structured data, and based indexed for arrays and table
lookups.

Q34. Explain Microprogrammed Control Unit with a neat block diagram. Describe all
components and explain the working sequence.
Marks: 8M | Type: Theory
Microprogrammed control unit uses a control store (ROM) to hold microinstructions.
Main parts: control store, microprogram counter (µPC), microinstruction register (µIR), and mapping logic.
Working: opcode is decoded -> mapping logic finds start address -> µIR fetches microinstruction -> control
signals are generated -> µPC selects next microinstruction.
Advantages: easy to modify, flexible, and suitable for complex instruction sets.
Disadvantage: slower than hardwired control.
Q35. Explain Hardwired Control Unit with a diagram. State its advantages over
microprogrammed CU.
Marks: 5M | Type: Theory
Hardwired control unit generates control signals using logic circuits, decoders, and flip-flops.
It is very fast because there is no microinstruction fetch from control memory.
Advantages over microprogrammed control: higher speed, lower instruction overhead, and efficient for simple
instruction sets.
Disadvantage: difficult to modify and redesign.

Q36. Compare Hardwired and Microprogrammed Control Units on: speed, design
complexity, flexibility, ease of modification, and cost.
Marks: 5M | Type: Theory
Hardwired CU vs Microprogrammed CU:
Speed: Hardwired is faster.
Flexibility: Microprogrammed is more flexible.
Design complexity: Hardwired becomes complex for large ISAs.
Modification: Microprogrammed is easier to change.
Cost: Microprogrammed uses control memory; hardwired uses more logic. The better choice depends on
whether speed or flexibility is more important.

Q37. Differentiate Horizontal and Vertical Microinstructions with examples. State the trade-
off between word length and parallelism.
Marks: 5M | Type: Theory
Horizontal microinstructions use a wide control word, often with one bit per control signal. They allow high
parallelism and do not need much decoding.
Vertical microinstructions are encoded, so the word is shorter and needs decoding logic.
Trade-off: horizontal format is faster but wider and costlier; vertical format is smaller but slower.
Horizontal is preferred when speed is important, while vertical is preferred when control memory size matters.

Q38. Explain microinstruction sequencing and execution. How does the μPC determine the
next microinstruction address?
Marks: 5M | Type: Theory
Microinstruction sequencing means selecting the next microaddress after the current microinstruction is
executed.
The µPC can move sequentially, branch to a new address, or follow a mapped entry from the opcode.
Execution flow: fetch microinstruction -> decode control field -> generate control signals -> update µPC ->
repeat until the machine instruction ends.

Q39. Compare RISC and CISC architectures in detail. State design principles, advantages,
and one real-world example of each.
Marks: 5M | Type: Theory
RISC uses simple, fixed-length instructions, load-store architecture, many registers, and hardwired control.
CISC uses more complex and variable-length instructions, memory-to-memory operations, and often
microprogrammed control.
Advantages of RISC: simpler pipeline, high speed, easier optimization.
Advantages of CISC: compact code and richer instruction set.
Examples: ARM or MIPS for RISC, x86 or 8086 for CISC.

Q40. Explain the design issues of RISC architecture. Why is RISC preferred for embedded
systems?
Marks: 5M | Type: Theory
RISC design aims to keep instructions simple and execute most of them in one clock cycle.
Important issues are fixed instruction length, large register set, load-store design, and efficient pipelining.
RISC is preferred in embedded systems because it gives good performance, lower power consumption, and
simpler hardware.
Module 4 - Memory Systems Organization
Q41. Explain Memory Hierarchy with a neat pyramid diagram. Describe the characteristics
(speed, cost, capacity) at each level.
Marks: 7M | Type: Theory
Memory hierarchy arranges storage from fastest/smallest to slowest/largest: registers, cache, main memory,
secondary storage, and backup storage.
Upper levels are faster and costlier per bit; lower levels are larger and cheaper.
This works because of locality of reference: programs reuse the same data (temporal locality) and nearby data
(spatial locality).
The goal is to get near-cache speed at near-memory cost.

Q42. Cache access time = 10 ns, main memory = 100 ns, hit ratio = 0.95. Find (a) effective
access time (b) speedup compared to no cache.
Marks: 5M | Type: Numerical
Effective access time (EAT) = h x Tc + (1 - h) x Tm
h = 0.95, Tc = 10 ns, Tm = 100 ns
EAT = 0.95 x 10 + 0.05 x 100 = 9.5 + 5 = 14.5 ns
Speedup over no cache = 100 / 14.5 = 6.90
Final answer: EAT = 14.5 ns, speedup = about 6.9x.

Q43. Explain memory parameters: capacity, access time, cycle time, bandwidth, and cost
per bit. How do they affect system design?
Marks: 5M | Type: Theory
Important memory parameters:
Capacity: total amount of data storage.
Access time: time to read/write one word.
Cycle time: minimum time between two memory operations.
Bandwidth: amount of data transferred per second.
Cost per bit: price of storing one bit.
A good memory should be fast, large, reliable, and cheap, but real designs balance these factors.

Q44. Compare Static RAM (SRAM) and Dynamic RAM (DRAM) in terms of construction,
speed, cost, refresh requirement, and applications.
Marks: 5M | Type: Theory
SRAM uses flip-flops to store each bit. It is very fast, expensive, and does not need refresh.
DRAM uses capacitors, so it is slower, cheaper, and needs periodic refresh.
SRAM is used in cache memory, while DRAM is used as main memory.
So SRAM gives speed and DRAM gives capacity.

Q45. Explain the different types of ROM: PROM, EPROM, EEPROM, and Flash ROM. State
how data is written/erased in each.
Marks: 5M | Type: Theory
PROM: programmable once by the user.
EPROM: can be erased by ultraviolet light and reprogrammed.
EEPROM: electrically erasable and programmable.
Flash ROM: a fast form of EEPROM that can erase blocks of memory at once.
These memories are non-volatile, so they keep data without power.

Q46. A computer has 64MB main memory, 32KB cache, and block size 8 bytes. Find the
memory address format for: (a) Direct Mapping (b) Fully Associative Mapping.
Marks: 8M | Type: Numerical
Main memory size = 64 MB = 2^26 bytes, so address length = 26 bits.
Cache size = 32 KB = 2^15 bytes.
Block size = 8 bytes = 2^3, so offset = 3 bits.
Number of cache lines = 2^15 / 2^3 = 2^12, so index = 12 bits.
Direct mapping address format = Tag(11) + Index(12) + Offset(3).
Fully associative mapping address format = Tag(23) + Offset(3).

Q47. A system has 16MB main memory, 64KB cache, and 16-byte blocks. Find address
format for: (a) Direct Mapping (b) 2-Way Set-Associative Mapping.
Marks: 8M | Type: Numerical
Main memory size = 16 MB = 2^24 bytes, so address length = 24 bits.
Cache size = 64 KB = 2^16 bytes.
Block size = 16 bytes = 2^4, so offset = 4 bits.
Number of cache lines = 2^16 / 2^4 = 2^12.
Direct mapping: Tag(8) + Index(12) + Offset(4).
2-way set associative: number of sets = 2^12 / 2 = 2^11, so Tag(9) + Set index(11) + Offset(4).

Q48. For a system with 32MB MM, 16KB cache, 8B block size, derive the address format
for all three: Direct, 4-Way Set-Associative, and Fully Associative.
Marks: 10M | Type: Numerical
Main memory = 32 MB = 2^25 bytes, so address length = 25 bits.
Cache = 16 KB = 2^14 bytes.
Block size = 8 bytes = 2^3, so offset = 3 bits.
Number of cache lines = 2^14 / 2^3 = 2^11.
Direct mapping: Tag(11) + Index(11) + Offset(3).
4-way set associative: sets = 2^11 / 4 = 2^9, so Tag(13) + Set index(9) + Offset(3).
Fully associative: Tag(22) + Offset(3).

Q49. Explain and compare Direct Mapping, Set-Associative Mapping, and Fully Associative
Mapping cache techniques with diagrams.
Marks: 8M | Type: Theory
Direct mapping places each memory block in exactly one cache line. It is simple and fast, but conflict misses
are higher.
Set-associative mapping allows a block to go to one of several lines in a set. It reduces conflict misses and still
keeps hardware reasonable.
Fully associative mapping allows a block to go anywhere in cache. It gives the fewest conflicts but needs more
hardware and search time.
So the choice is a trade-off between speed, cost, and miss rate.

Q50. Explain write-through and write-back (copy-back) cache write policies. What is the
advantage of write-back over write-through?
Marks: 5M | Type: Theory
Write-through updates cache and main memory at the same time. It is simple and keeps memory always
current, but it creates more memory traffic.
Write-back updates main memory only when the cache block is replaced. It reduces memory traffic and
improves performance.
Advantage of write-back: faster average write performance.
Advantage of write-through: easier consistency and simpler design.

Q51. Explain the paging mechanism for virtual memory with a neat diagram. Define: page,
frame, page table, page fault, TLB.
Marks: 8M | Type: Theory
Paging divides virtual memory into fixed-size pages and physical memory into frames of the same size.
Virtual address = page number + offset.
Page table translates page number into frame number.
If a referenced page is not in RAM, a page fault occurs and the OS loads it from disk.
TLB (Translation Lookaside Buffer) is a fast associative cache of page-table entries.
Paging removes external fragmentation and supports virtual memory.

Q52. A system uses 32-bit virtual address with 4KB page size. (a) How many pages can the
virtual address space hold? (b) How many bits are used for page number and offset?
Marks: 5M | Type: Numerical
Page size = 4 KB = 2^12 bytes, so offset = 12 bits.
Virtual address length = 32 bits, so page number bits = 32 - 12 = 20 bits.
Number of pages in virtual address space = 2^20 = 1,048,576 pages.
Final answer: page number = 20 bits, offset = 12 bits, total pages = 2^20.

Q53. Explain LRU, FIFO, and Optimal page replacement algorithms. Give an example with
a reference string to show page faults.
Marks: 7M | Type: Theory
LRU (Least Recently Used) replaces the page that has not been used for the longest time.
FIFO (First-In First-Out) replaces the oldest loaded page.
Optimal replacement replaces the page that will not be used for the longest future time, so it gives the minimum
page faults but is not practical.
In general, Optimal is best theoretically, LRU is a good practical choice, and FIFO is the simplest.

Q54. Explain segmentation in virtual memory. Describe the segment table structure and
physical address translation.
Marks: 5M | Type: Theory
Segmentation divides a program into logical units such as code, data, stack, and heap.
Each segment has a base address and a limit in the segment table.
Physical address = base + offset, but only if offset is within the limit.
Segmentation is useful for protection and sharing because each logical unit can be handled separately.

Q55. Compare Paging and Segmentation in terms of: unit size, fragmentation type,
sharing, protection, and hardware support.
Marks: 5M | Type: Theory
Paging uses fixed-size pages and frames, while segmentation uses variable-size logical segments.
Paging causes internal fragmentation; segmentation can cause external fragmentation.
Paging is better for memory management and hardware translation. Segmentation is better for logical view,
protection, and sharing.
Many systems combine both to get the benefits of each.

Q56. Explain the cache coherency problem in multiprocessor systems. Describe any two
techniques to resolve it.
Marks: 5M | Type: Theory
Cache coherency problem happens in multiprocessor systems when more than one cache holds a copy of the
same memory block and one copy becomes stale after a write.
Two common solutions are:
1) Snooping: caches watch the bus and invalidate or update copies when another processor writes.
2) Directory-based coherence: a directory keeps track of which caches have each block.
Both methods keep all processors seeing a consistent view of memory.

Q57. Explain the MESI cache coherency protocol. Describe the four states and state
transitions with examples. (Self-Study)
Marks: 5M | Type: Theory
MESI has four states:
Modified: block is changed and only in this cache.
Exclusive: block is clean and present in only one cache.
Shared: block is clean and may exist in multiple caches.
Invalid: block is not valid.
MESI reduces unnecessary memory writes and helps maintain coherence in multiprocessor caches.

Q58. Explain interleaved memory organization. Differentiate between low-order and high-
order interleaving with diagrams.
Marks: 5M | Type: Theory
Interleaved memory uses multiple memory modules so that consecutive addresses can be accessed in parallel.
Low-order interleaving distributes consecutive words across different modules, which is good for sequential
access.
High-order interleaving places blocks in different modules based on high-order bits.
Interleaving increases bandwidth and reduces memory access bottlenecks.
Q59. Explain Associative Memory (Content Addressable Memory). Draw its structure and
state its applications in cache and TLB.
Marks: 5M | Type: Theory
Associative memory, also called content-addressable memory (CAM), is accessed by content rather than by
address.
The search key is compared in parallel with all stored entries.
It is very fast and is used in cache tag comparison and TLB lookup.
Disadvantage: it is costly and hardware-intensive.
Module 5 - I/O Organization
Q60. Explain the types of buses in a computer system. Describe the function of the
Address, Data, and Control buses.
Marks: 5M | Type: Theory
The three bus types are:
Address bus: carries the address of the memory or I/O location; it is usually unidirectional.
Data bus: carries actual data; it is bidirectional.
Control bus: carries control signals like read, write, interrupt, and clock.
Together they connect the CPU, memory, and I/O devices.

Q61. Explain ISA, PCI, and USB bus standards. Compare them with respect to speed, data
width, plug-and-play, and hot-plug capability.
Marks: 5M | Type: Theory
ISA is an older bus standard with lower speed and limited data width.
PCI supports 32-bit or 64-bit transfer, plug-and-play, and higher speed than ISA.
USB is a serial bus, supports hot-plugging, and can connect many devices easily.
In general: ISA is legacy, PCI is faster and expandable, USB is best for external peripherals.

Q62. Explain Bus Arbitration. Describe Daisy Chain, Counter-Based (Polling), and
Independent Request methods with diagrams.
Marks: 5M | Type: Theory
Bus arbitration decides which device gets control of the bus when multiple devices request it.
Daisy chain: priority depends on physical position in the chain.
Counter-based (polling): the arbiter checks devices one by one.
Independent request: each device has its own request line, so arbitration is faster and more flexible.
The goal is to avoid bus conflict and give fair access.

Q63. Compare centralized and distributed bus arbitration techniques. State the advantages
of Independent Request method.
Marks: 5M | Type: Theory
Centralized arbitration uses one arbiter to control bus access. It is simple but can become a bottleneck.
Distributed arbitration does not rely on a single central controller; devices cooperate to decide bus ownership.
Independent request is advantageous because it gives faster response, supports priority control, and works
well in larger systems.

Q64. Explain the I/O module structure and its role in interfacing I/O devices with CPU and
memory.
Marks: 5M | Type: Theory
An I/O module is the interface between CPU/memory and peripheral devices.
It handles data buffering, status checking, control signals, and device-specific timing.
Typical parts: data register, status register, control register, and control logic.
Its job is to hide the differences between fast CPU operations and slow external devices.
Q65. What is an I/O Channel? How does it differ from a simple I/O controller? Explain
selector and multiplexor channel types.
Marks: 5M | Type: Theory
An I/O channel is a dedicated processor-like unit that manages I/O operations.
It differs from a simple I/O controller because it can execute its own I/O instructions and reduce CPU
involvement.
Selector channel handles one high-speed device at a time.
Multiplexor channel handles many slow devices by sharing the channel time among them.

Q66. Explain I/O processor architecture. How does it offload I/O management from the
main CPU?
Marks: 5M | Type: Theory
An I/O processor is a special processor dedicated to input/output control.
It executes I/O commands, manages data transfer, and reduces the load on the main CPU.
This improves system efficiency because the CPU can continue with computation while I/O processor handles
device communication.

Q67. Explain and compare Programmed I/O, Interrupt-driven I/O, and DMA. Draw block
diagrams for Interrupt and DMA. State the best use case for each.
Marks: 7M | Type: Theory
Programmed I/O: CPU repeatedly checks the device status, so CPU time is wasted in polling.
Interrupt-driven I/O: CPU does other work and is interrupted only when the device is ready.
DMA: a DMA controller transfers data directly between memory and device, with minimum CPU involvement.
Best use: programmed I/O for simple/slow devices, interrupt-driven I/O for medium-speed devices, DMA for
large block transfers and high-speed devices.

Q68. Explain DMA (Direct Memory Access) in detail. Draw the DMA controller block
diagram and describe Cycle Stealing mode.
Marks: 7M | Type: Theory
DMA allows direct transfer of data between memory and an I/O device without continuous CPU intervention.
DMA controller block diagram includes DMA request, bus arbitration logic, address register, count register, and
control logic.
Cycle stealing mode means DMA takes control of the bus for one memory cycle at a time, stealing cycles from
the CPU.
This keeps CPU delay small while still allowing fast data transfer.

Q69. Explain Interrupt-driven I/O. Describe the steps from interrupt request to interrupt
service routine completion. What is interrupt vectoring?
Marks: 5M | Type: Theory
Interrupt-driven I/O works like this: device requests interrupt -> CPU finishes current instruction -> interrupt is
acknowledged -> interrupt vector gives ISR address -> ISR transfers data and services the device -> return
from interrupt.
Interrupt vectoring means the CPU uses a vector table to directly find the address of the correct interrupt
service routine.
This is more efficient than polling because the CPU is not busy-waiting.
Module 6 - Parallel Processing
Q70. Explain the three operating modes of the 80386DX processor: Real Mode, Protected
Mode, and Virtual 8086 Mode. State key features of each.
Marks: 5M | Type: Theory
80386DX has three important modes:
Real mode: 8086 compatible, 1 MB address space, 20-bit addressing.
Protected mode: supports 4 GB address space, segmentation plus paging, and privilege levels (rings 0 to 3).
Virtual 8086 mode: lets the processor run multiple 8086-style programs inside protected mode.
These modes make 80386DX suitable for compatibility, protection, and multitasking.

Q71. Explain the 5-stage instruction pipeline (IF, ID, EX, MEM, WB) with a timing diagram.
Derive the speedup formula for an n-stage pipeline.
Marks: 7M | Type: Theory
A 5-stage pipeline has stages: IF, ID, EX, MEM, WB.
Idea: while one instruction executes in one stage, the next instruction enters the next stage.
For k stages and n instructions, total cycles = k + n - 1.
If each stage takes one clock cycle, pipeline speedup compared to non-pipelined execution is approximately:
Speedup = n x k / (k + n - 1)
For a large number of instructions, speedup approaches k.

Q72. Explain Superscalar architecture. How does it achieve IPC > 1? Compare with a
simple single-pipeline processor.
Marks: 5M | Type: Theory
Superscalar architecture has multiple execution units so that more than one instruction can be issued in the
same clock cycle.
This gives IPC greater than 1, but only when instructions are independent enough to execute in parallel.
Compared to a simple single-pipeline processor, superscalar processors have higher throughput, but also need
more complex instruction scheduling and hazard handling.

Q73. Draw and explain all three types of pipeline hazards with examples. State the
methods to resolve each type.
Marks: 8M | Type: Theory
Pipeline hazards are problems that stop ideal one-instruction-per-cycle execution.
Structural hazard: two instructions need the same hardware resource at the same time.
Data hazard: one instruction depends on the result of another (RAW, WAR, WAW).
Control hazard: branch or jump changes the next instruction address.
Solutions: duplicate resources or separate caches for structural hazards, forwarding/stalling for data hazards,
and branch prediction for control hazards.

Q74. Explain data forwarding (bypassing) technique to resolve RAW hazards. Draw a
diagram showing data path from EX stage to EX stage input.
Marks: 5M | Type: Theory
Data forwarding (bypassing) sends the result of an ALU operation directly to a later instruction without waiting
for write-back to register file.
This removes many RAW hazards and reduces stall cycles.
Example idea: the output of EX stage can be routed back to the input of the next EX stage through a forwarding
path.
Forwarding is one of the most important pipeline performance improvements.

Q75. Explain branch prediction techniques: static (always not-taken) and dynamic (2-bit
saturating counter). What is Branch Target Buffer (BTB)?
Marks: 5M | Type: Theory
Static branch prediction uses a fixed rule, for example always not-taken.
Dynamic branch prediction uses runtime history, such as a 2-bit saturating counter, to predict future branches
more accurately.
BTB (Branch Target Buffer) stores the target addresses of recently taken branches, so the processor can fetch
the next instruction quickly.
These techniques reduce control hazard stalls.

Q76. A 5-stage pipeline has a clock cycle of 2 ns. For 100 instructions with 10 data hazards
(each requiring 2 stall cycles) and 5 branch hazards (3 stall cycles each), find total
execution time.
Marks: 5M | Type: Numerical
Clock cycle = 2 ns.
Base execution time for 100 instructions in a 5-stage pipeline = (100 + 4) x 2 ns = 208 ns.
Data hazard stalls = 10 x 2 = 20 cycles.
Branch hazard stalls = 5 x 3 = 15 cycles.
Total cycles = 104 + 20 + 15 = 139 cycles.
Total execution time = 139 x 2 ns = 278 ns.
Final answer: 278 ns.

Q77. 80% of a program can be parallelized. Find the speedup when using (a) 4 processors
(b) 8 processors (c) infinite processors. What is the maximum achievable speedup?
Marks: 5M | Type: Numerical
Serial fraction f = 0.2 because 80% is parallelizable.
Speedup with 4 processors = 2.50.
Speedup with 8 processors = 3.33.
Speedup with infinite processors = 5.00.
Maximum achievable speedup = 5.00.

Q78. A program takes 100 seconds. 60 seconds of it can be parallelized. Find the speedup
with 4 processors. How many processors needed for speedup of 3?
Marks: 5M | Type: Numerical
Total time = 100 s.
Parallel part = 60 s, serial part = 40 s.
With 4 processors: time = 40 + 60/4 = 55 s, so speedup = 100/55 = 1.82.
To get speedup 3, required time would be 100/3 = 33.33 s, but the serial part alone takes 40 s.
So speedup 3 is impossible. The maximum speedup is 100/40 = 2.5.

Q79. State and explain Amdahl's Law. What does it imply about the limits of parallel
processing? Explain with a graph.
Marks: 5M | Type: Theory
Amdahl's Law states that the speedup of a program is limited by its serial part.
Formula: S = 1 / [f + (1 - f)/n], where f is the serial fraction and n is the number of processors.
As n increases, speedup improves only up to 1/f.
Meaning: even a huge number of processors cannot overcome the part of the program that must run
sequentially.
So parallel processing has diminishing returns.

Q80. Explain Flynn's classification of computer architectures. Draw diagrams for all four
types (SISD, SIMD, MISD, MIMD) and give one real-world example each.
Marks: 5M | Type: Theory
Flynn's classification groups computers by instruction and data streams.
SISD: one instruction stream, one data stream. Example: basic single-core processor.
SIMD: one instruction stream, many data streams. Example: vector processors / GPUs.
MISD: many instruction streams, one data stream. Rare in practice.
MIMD: many instruction streams, many data streams. Example: multicore CPUs and clusters.

Q81. Compare SIMD and MIMD parallel architectures. State why MIMD is the most
commonly used model in modern computers.
Marks: 5M | Type: Theory
SIMD executes the same instruction on many data items at the same time, so it is good for image, matrix, and
vector work.
MIMD allows different processors to run different instructions on different data, so it is more flexible.
MIMD is the most common model today because modern systems need general-purpose multitasking,
multicore execution, and scalable parallelism.

Q82. Explain the concept of parallel processing. What are its advantages? Describe the
types of parallelism: bit-level, instruction-level, task-level.
Marks: 5M | Type: Theory
Parallel processing means performing multiple operations simultaneously to improve speed and throughput.
Advantages: faster execution, better resource use, and ability to handle large workloads.
Types of parallelism:
Bit-level parallelism: process wider words at once.
Instruction-level parallelism: overlap or issue multiple instructions together.
Task-level parallelism: different tasks run at the same time.

Q83. Write a short note on Superscalar architecture with reference to the Pentium
processor as a case study. (Self-Study topic)
Marks: 5M | Type: Theory
Superscalar architecture can issue more than one instruction in a clock cycle by using multiple execution units.
Pentium processors are a common example because they used parallel execution paths to improve throughput.
The processor checks instruction dependencies, dispatches independent instructions together, and increases
IPC beyond 1.
This improves performance without relying only on a higher clock speed.