MICROPROCESSOR

(ARCHITECTURE AND PROGRAMMING)

8086 – 16 BIT MICROPROCESSOR

1. INTRODUCTION
• 8086 Microprocessor is an enhanced version of 8085 Microprocessor
designed by Intel in 1976.
• It is a 16-bit Microprocessor having 20 address lines and 16 data lines,
providing up to 1 MB of storage.
• It consists of a powerful instruction set, which supports operations like
multiplication and division easily.
• It supports two modes of operation: Maximum mode and Minimum
mode.
• Maximum mode is suitable for systems having multiple processors;
Minimum mode is for single-processor systems.
• 8086 uses a pipelined architecture: the Bus Interface Unit (BIU) fetches
instructions while the Execution Unit (EU) executes them simultaneously.
• It is fabricated using HMOS (High-speed Metal Oxide Semiconductor)
technology and is housed in a 40-pin DIP package.

2. FEATURES OF 8086 MICROPROCESSOR

• 16-bit microprocessor — can process 16-bit data in a single operation.
• 16-bit data bus: reads/writes 16-bit or 8-bit data from/to memory and
ports.
• 20-bit address bus: can access up to 2²■ = 1,048,576 memory
locations (1 MB).
• Supports up to 64K I/O ports.
• Provides 14 internal 16-bit registers.
• Multiplexed address and data bus: AD■–AD■■ and A■■–A■■.
• Requires a single-phase clock with 33% duty cycle for internal timing.
• Pre-fetches up to 6 instruction bytes from memory into a queue,
enabling instruction pipelining.
• Two stages of pipelining: Fetch Stage and Execute Stage.
• Three versions based on clock frequency:
– 8086 → 5 MHz
– 8086-2 → 8 MHz
– 8086-1 → 10 MHz
• Supports 256 vectored interrupts.
• Contains approximately 29,000 transistors on a single chip.
• Two independent on-chip units: Bus Interface Unit (BIU) and Execution
Unit (EU).
• Compatible with 8087 Numeric Co-Processor for floating-point
operations.
3. REGISTER ORGANIZATION
The 8086 microprocessor has 14 internal 16-bit registers. They are
classified into four groups:
– General Data Registers (AX, BX, CX, DX)
– Segment Registers (CS, DS, ES, SS)
– Pointer and Index Registers (IP, SP, BP, SI, DI)
– Flag Register

3.1 General Data Registers

All four data registers are 16-bit but can be split into two independent 8-bit
halves (High byte and Low byte).
• AX (Accumulator): Primary register for arithmetic, logic, and I/O
operations. AH = high byte; AL = low byte.
• BX (Base Register): Used as a base address register for memory
addressing. Can hold the offset of data in the data segment.
• CX (Count Register): Default counter in string operations and loop
instructions (LOOP, REP prefix).
• DX (Data Register): Used in I/O port addressing, and as an implicit
operand/destination in multiply and divide instructions.

16-bit Reg High Byte (8-bit)Low Byte (8-bit) Primary Use

AX AH AL Accumulator – arithmetic & I/O

BX BH BL Base – memory offset storage

CX CH CL Counter – loops and string ops

DX DH DL Data – I/O addressing, MUL/DIV

3.2 Segment Registers

8086 divides its 1 MB memory space into logical segments, each up to 64
KB. Each segment register holds the 16-bit base (starting) address of a
segment. The physical address is computed as:
Physical Address = Segment Register × 16 + Offset
Address
 • CS (Code Segment): Points to the segment containing the currently
executing program code. IP holds the offset.
• DS (Data Segment): Points to the segment where program data is
stored. SI/DI/BX provide the offset.
• SS (Stack Segment): Points to the segment used for the stack. SP/BP
provide the offset.
• ES (Extra Segment): An additional data segment — mainly used as
the destination segment in string operations.

3.3 Pointer and Index Registers

• IP (Instruction Pointer): Always used with CS. Points to the next
instruction to be fetched. Not directly accessible by the programmer.
• SP (Stack Pointer): Used with SS. Points to the top of the stack.
Automatically updated by PUSH/POP instructions.
• BP (Base Pointer): Used with SS to access parameters/local variables
on the stack.
• SI (Source Index): Used in string operations as the source offset in
DS.
• DI (Destination Index): Used in string operations as the destination
offset in ES.

Register Full Name Default SegmentPurpose

IP Instruction Pointer CS Next instruction offset

SP Stack Pointer SS Top of stack offset

BP Base Pointer SS Stack base / parameter access

SI Source Index DS String source offset

DI Destination Index ES String destination offset

4. FLAG REGISTER (PSW – PROCESSOR STATUS WORD)
The 8086 uses a 16-bit flag register (also called the Program Status Word).
Out of 16 bits, only 9 are used. They are divided into two categories:
– Status Flags (6) – reflect the result of the last ALU operation
– Control Flags (3) – control the behaviour of certain instructions

Flag Name Type Description

CF Carry Flag Status Set when there is a carry out of the MSB during addition,

PF Parity Flag Status Set to 1 if the lower byte of the result contains an even n

AF Auxiliary Carry Status Set when there is a carry from bit 3 to bit 4 (used in BCD

ZF Zero Flag Status Set when the result of a computation or comparison is ze

SF Sign Flag Status Set when the result of a computation is negative (equals

OF Overflow Flag Status Set when signed arithmetic result is too large for the des

TF Trap Flag Control When set, the CPU enters single-step (debug) mode — e

IF Interrupt Flag Control When set (STI), maskable hardware interrupts (INTR) ar

DF Direction Flag Control Controls string instruction direction. DF=0: auto-incremen

Flag Register Bit Layout (bit positions):

Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Flag: — — — — OF DF IF TF SF ZF — AF — PF — CF

Key notes:
• Bits 1, 3, 5 are always 1, 0, 0 respectively (reserved).
• Bits 12–15 are unused in 8086 (used later in 80286/386 for protection).
• LAHF instruction loads bits 0–7 of the flag register into AH. SAHF
stores AH back into the low flag byte.
• PUSHF/POPF push/pop the entire 16-bit flag register to/from the stack.
5. INTERNAL ARCHITECTURE OF 8086
The 8086 CPU is divided into two independent, simultaneously operating
functional units:

Unit Abbreviation Main Responsibility

Bus Interface Unit BIU Fetches instructions and data from memory; sends add

Execution Unit EU Decodes and executes instructions; performs arithmeti

5.1 Bus Interface Unit (BIU)

• Responsible for all memory and I/O bus operations (addresses, data,
control).
• Maintains a 6-byte instruction pre-fetch queue (FIFO).
• Feeds instructions into the queue whenever the bus is free and the
queue is not full.
• Sends the 20-bit physical address to the system bus using the segment
: offset calculation.
• Contains the Segment Registers (CS, DS, ES, SS) and the Instruction
Pointer (IP).
• When a branch or jump is taken, the BIU flushes the queue and begins
filling it from the new address.

5.2 Execution Unit (EU)

• Extracts instructions from the top of the BIU pre-fetch queue — never
accesses memory directly.
• Contains a 16-bit ALU capable of: ADD, SUB, MUL, DIV, AND, OR,
XOR, NOT, shift, rotate, increment, decrement.
• Holds all General Purpose Registers (AX, BX, CX, DX) and
Pointer/Index Registers (SP, BP, SI, DI).
• Contains the Flag Register and the internal temporary registers used
during execution.
• Decodes instructions and signals the BIU when memory/IO reads or
writes are required.
5.3 Pipelining in 8086
The separation of the BIU and EU allows two-stage pipelining:
• While the EU is executing the current instruction, the BIU is
simultaneously fetching the next instruction(s).
• The pre-fetch queue hides the memory access latency, increasing
throughput.
• Exception: JMP, CALL, RET, and conditional branch instructions cause
the BIU to flush the queue and restart fetching from the new address.

Clock Cycle BIU Activity EU Activity

T1 Fetch Instruction Byte 1 (idle / start)

T2 Fetch Instruction Byte 2 Decode Instruction 1

T3 Fetch Instruction Byte 3 Execute Instruction 1

T4 Fetch Instruction Byte 4 Decode Instruction 2

T5 Fetch Instruction Byte 5 Execute Instruction 2

6. PIN DIAGRAM AND PIN DESCRIPTION
The Intel 8086 is housed in a 40-pin DIP (Dual In-line Package). It operates
on +5V DC (Vcc). Address and data lines are time-multiplexed to reduce pin
count.

Pin / Signal Direction Description

AD■–AD■■ Bidirectional Multiplexed Address/Data bus. During T1 carry 16-bit address; then c

A■■–A■■ / S■–S■ Output During T1: upper 4 bits of 20-bit address. After T1: status signals S■

BHE′ / S■ Output Bus High Enable (active LOW during T1). Enables upper byte (D■–D

RD′ Output Read control (active LOW). Signals memory/IO to place data on bus.

WR′ Output Write control (active LOW). Signals memory/IO to accept data from b

M/IO′ Output Memory/IO select. HIGH = memory access; LOW = I/O access.

ALE Output Address Latch Enable. HIGH pulse during T1; used to latch address

DT/R′ Output Data Transmit/Receive. Determines data flow direction through 8286

DEN′ Output Data Enable. Active LOW; enables 8286/8287 transceivers during da

READY Input Active HIGH. Inserted by slow memory/IO to add wait states (Tw) unt

INTR Input Interrupt Request. Active HIGH; sampled at end of each instruction if

INTA′ Output Interrupt Acknowledge. Active LOW response to INTR; causes device

NMI Input Non-Maskable Interrupt. Rising-edge triggered. Generates Type-2 int

RESET Input Active HIGH (≥4 clocks). Reinitialises CPU: CS=FFFFH, all other reg

TEST′ Input Used by WAIT instruction. CPU idles until TEST′ goes LOW (used w

CLK Input Clock input. Asymmetric square wave, 33% duty cycle. Frequency: 5

MN/MX′ Input Minimum/Maximum mode select. HIGH = Minimum mode; LOW = Ma

HOLD / RQ′/GT′ Input Bus request from another bus master (DMA or another CPU in max m

HLDA / RQ′/GT′ Output Hold Acknowledge. CPU grants bus to requesting master.

LOCK′ Output (Max mode) Active LOW; prevents other bus masters from gaining th

S■′, S■′, S■′ Output (Max mode) Bus cycle status pins. Decoded by 8288 Bus Controller t

QS■, QS■ Output (Max mode) Queue status. Inform 8087 about queue state (empty, fir

Vcc — Power supply: +5V DC.

GND — Ground (0V). Two GND pins on the IC.

7. STATUS AND CONTROL TABLES
7.1 S■′, S■′, S■′ – Bus Cycle Status (Maximum Mode)
These three signals are decoded by the external 8288 Bus Controller to
generate the appropriate memory/IO read/write signals:

S■′ S■′ S■′ Bus Cycle Type

0 0 0 Interrupt Acknowledge

0 0 1 I/O Read

0 1 0 I/O Write

0 1 1 Halt

1 0 0 Code Fetch (Memory Read)

1 0 1 Memory Read

1 1 0 Memory Write

1 1 1 Passive / No bus cycle

7.2 QS■, QS■ – Queue Status (Maximum Mode)

QS■ QS■ Queue Status

0 0 No operation (queue inactive)

0 1 First byte of opcode fetched from queue

1 0 Queue was flushed (branch taken)

1 1 Subsequent byte of same instruction fetched

7.3 Minimum Mode vs Maximum Mode

The MN/MX′ pin selects one of two operating modes:

Feature Minimum Mode (MN/MX′ = HIGH)

Maximum Mode (MN/MX′ = LOW)

Target System Single processor Multi-processor / co-processor (e.g. 8087)

Control Signals Generated directly by 8086 Generated by external 8288 Bus Controller

Shared pins M/IO′, RD′, WR′, HOLD, HLDA,

S■′–S■′,
DEN, DT/R,
LOCK′,
ALE
RQ′/GT■′, RQ′/GT■′, QS■, Q
Feature Minimum Mode (MN/MX′ = HIGH)
Maximum Mode (MN/MX′ = LOW)

Complexity Simple, fewer chips Complex, more chips, higher performance

8. ADDRESSING MODES
Addressing modes specify how the operand(s) of an instruction are located.
8086 supports the following modes:

# Addressing Mode
Effective Address (EA) Calculation
Example

MOV AX, 1234H

1 Immediate Operand is part of instruction — no memory access needed.
MOV BL, 0FFH

MOV AX, BX
2 Register Operand is in a register — fastest mode, no bus cycle.
ADD CX, DX

Direct EA = 16-bit displacement given in

MOVinstruction.
AX, [0200H]
3
(Displacement) DS:disp MOV AX, [DATA]

Register EA = contents of BX, SI, or DI. MOV AX, [BX]

4
Indirect BX→DS; BP→SS MOV CL, [SI]

Based MOV AX, [BX+04H]

5 EA = [BX or BP] + 8/16-bit disp.
(Register + Disp) MOV CL, [BP+10H]

Indexed MOV AX, [SI+06H]

6 EA = [SI or DI] + 8/16-bit disp.
(Index + Disp) MOV BL, [DI+20H]

MOV AX, [BX+SI]

7 Based-Indexed EA = [BX or BP] + [SI or DI].
MOV CX, [BP+DI]

Based-Indexed MOV AX,[BX+SI+05H]

8 EA = [BX or BP] + [SI or DI] + disp.
+ Displacement ADD BL,[BP+DI+10H]

CLC, STC, STI

9 Implicit / InherentNo operand specified — register implied by instruction.
XLAT, AAA

Direct: 8-bit port in instruction. IN AL, 40H

10 I/O Port
Indirect: port no. in DX. OUT DX, AL
9. INSTRUCTION SET OF 8086
The 8086 instruction set contains approximately 117 basic instructions
which can be grouped into 7 categories:

Category Key Instructions Purpose

1. Data Transfer MOV, PUSH, POP, XCHG, XLAT,

Transfer
IN, OUT,
dataLEA,
between
LDS,registers,
LES memory and I/O

2. Arithmetic ADD, ADC, SUB, SBB, MUL, IMUL,

Perform
DIV,
arithmetic
IDIV, INC,
operations
DEC, NEG,on binary
CMP, CBW,
and BCD
CW

3. Logical / Bit AND, OR, XOR, NOT, TEST, SHL/SAL,

Bit manipulation
SHR, SAR,
and logical
ROL, ROR,
operations.
RCL, RCR

4. String MOVS, CMPS, SCAS, LODS, STOS

Operate
+ REP/REPE/REPNE
on byte/word stringsprefixes
in memory.

5. Control Transfer
JMP, Jcc (all conditionals), LOOP,
AlterLOOPE,
the flowLOOPNE,
of programCALL,
execution.
RET, INT, INTO, I

6. Processor Control
CLC, STC, CMC, CLD, STD, CLI,
Control
STI, flags
HLT, and
WAIT,
processor
NOP, LOCK,
state. ESC

7. Flag Operations
LAHF, SAHF, PUSHF, POPF Direct manipulation of the Flag register.

9.1 Data Transfer Instructions (Detail)

Instruction Syntax Action

MOV MOV dst, src Copy src to dst. Flags not affected.

PUSH PUSH src SP ← SP−2; [SS:SP] ← src (16-bit).

POP POP dst dst ← [SS:SP]; SP ← SP+2.

XCHG XCHG op1, op2 Exchange op1 and op2. Flags not affected.

IN IN AL/AX, port Read byte/word from I/O port into AL or AX.

OUT OUT port, AL/AX Write AL or AX to I/O port.

LEA LEA reg16, mem Load Effective Address of mem into reg16.

LDS LDS reg16, mem32 Load 32-bit far pointer: reg16 ← offset, DS ← segment.

LES LES reg16, mem32 Load 32-bit far pointer: reg16 ← offset, ES ← segment.

XLAT XLAT AL ← DS:[BX+AL]. Translates AL using a lookup table.

9.2 Arithmetic Instructions
Instruction Syntax Action / Notes

ADD ADD dst, src dst ← dst + src. Affects CF, OF, SF, ZF, PF, AF.

ADC ADC dst, src dst ← dst + src + CF. Used for multi-word addition.

SUB SUB dst, src dst ← dst − src. Affects all status flags.

SBB SBB dst, src dst ← dst − src − CF. Used for multi-word subtraction.

INC INC dst dst ← dst + 1. CF not affected.

DEC DEC dst dst ← dst − 1. CF not affected.

NEG NEG dst dst ← 0 − dst (two's complement negation).

CMP CMP op1, op2 op1 − op2, result discarded but flags updated.

MUL MUL src Unsigned: AX ← AL×src (byte), DX:AX ← AX×src (word).

IMUL IMUL src Signed multiplication. Same register usage as MUL.

DIV DIV src Unsigned: AL←AX÷src (quot), AH←remainder (byte).

IDIV IDIV src Signed division. Same register usage as DIV.

CBW CBW Sign-extend AL into AX (Convert Byte to Word).

CWD CWD Sign-extend AX into DX:AX (Convert Word to Double Word

9.3 Logical and Bit-Manipulation Instructions

Instruction Syntax Action

AND AND dst, src dst ← dst AND src (bitwise). CF=OF=0.

OR OR dst, src dst ← dst OR src (bitwise). CF=OF=0.

XOR XOR dst, src dst ← dst XOR src. CF=OF=0.

NOT NOT dst dst ← NOT dst (one's complement). Flags not affected.

TEST TEST op1, op2 op1 AND op2, result discarded; only flags updated.

SHL/SAL SHL dst, CL/1 Shift left; zeros fill from right. MSB → CF.

SHR SHR dst, CL/1 Logical shift right; zeros fill from left. LSB → CF.

SAR SAR dst, CL/1 Arithmetic shift right; sign bit replicated. LSB → CF.
Instruction Syntax Action

ROL ROL dst, CL/1 Rotate left; MSB wraps to LSB and to CF.

ROR ROR dst, CL/1 Rotate right; LSB wraps to MSB and to CF.

RCL RCL dst, CL/1 Rotate left through carry; CF inserted at LSB.

RCR RCR dst, CL/1 Rotate right through carry; CF inserted at MSB.
9.4 Control Transfer Instructions
Unconditional Jumps / Calls:
Instruction Syntax Action

JMP JMP label/reg/mem Unconditional jump. Short (±128B), near (±32KB), or far.

CALL CALL proc Call subroutine; pushes return address onto stack.

RET RET [n] Return from subroutine; pops IP (and optionally CS).

INT n INT n Software interrupt; pushes flags, CS, IP; jumps to IVT[n].

IRET IRET Return from interrupt; pops IP, CS, and Flags.

INTO INTO Interrupt on overflow (INT 4 if OF=1).

Conditional Jumps (Jcc):

Instruction Condition Tested Jump if…

JZ / JE ZF = 1 Result is zero / Equal

JNZ / JNE ZF = 0 Result non-zero / Not equal

JC / JB / JNAE CF = 1 Carry set / Below (unsigned)

JNC / JNB / JAE CF = 0 No carry / Above or equal

JS SF = 1 Sign negative

JNS SF = 0 Sign positive or zero

JO OF = 1 Overflow occurred

JNO OF = 0 No overflow

JP / JPE PF = 1 Even parity

JNP / JPO PF = 0 Odd parity

JL / JNGE SF ≠ OF Less (signed)

JGE / JNL SF = OF Greater or equal (signed)

JLE / JNG ZF=1 or SF≠OF Less or equal (signed)

JG / JNLE ZF=0 and SF=OF Greater (signed)

LOOP CX ≠ 0 Decrement CX; loop if CX ≠ 0

LOOPE/LOOPZ CX≠0 and ZF=1 Loop while equal and CX ≠ 0

Instruction Condition Tested Jump if…

LOOPNE/LOOPNZ CX≠0 and ZF=0 Loop while not equal and CX ≠ 0

9.5 String Instructions
String instructions operate on arrays (strings) of bytes or words. SI points to
the source in DS; DI points to the destination in ES. After each operation, SI
and/or DI are automatically incremented (DF=0) or decremented (DF=1).

Instruction Full Name Action

MOVS / MOVSB / MOVSWMove String Copy byte/word from DS:[SI] to ES:[DI]; update SI, DI.

CMPS / CMPSB / CMPSWCompare StringCompare DS:[SI] with ES:[DI]; update flags and SI, DI

SCAS / SCASB / SCASW Scan String Compare AL/AX with ES:[DI]; update flags and DI.

LODS / LODSB / LODSW Load String Load DS:[SI] into AL/AX; update SI.

STOS / STOSB / STOSW Store String Store AL/AX into ES:[DI]; update DI.

Repeat Prefixes:
Prefix Repeat Condition Common Use

REP CX ≠ 0 Repeat MOVS or STOS — copy/fill CX times.

REPE / REPZ CX ≠ 0 AND ZF = 1 Repeat CMPS/SCAS while equal.

REPNE / REPNZ CX ≠ 0 AND ZF = 0 Repeat CMPS/SCAS while not equal (e.g. find charac

String Example — Copy 100 bytes:

MOV CX, 100 ; set count = 100 bytes
LEA SI, SOURCE ; DS:SI → source array
LEA DI, DEST ; ES:DI → destination array
CLD ; clear DF → auto-increment
REP MOVSB ; repeat MOVSB until CX = 0

9.6 Processor Control Instructions

Instruction Action

CLC / STC / CMC Clear / Set / Complement the Carry Flag (CF).

CLD / STD Clear / Set the Direction Flag (DF).

CLI / STI Clear / Set the Interrupt Flag (IF) — disable/enable maskable interrupts.

HLT Halt CPU until a hardware interrupt or RESET occurs.

Instruction Action

NOP No operation — wastes one bus cycle (useful for timing/padding).

WAIT CPU idles until TEST′ pin goes LOW (used to synchronise with 8087).

LOCK Prefix that asserts LOCK′ signal for duration of next instruction (prevents

ESC op, src Escape to co-processor (8087). CPU puts src on bus; 8087 executes op.
10. INTERRUPT SYSTEM OF 8086
8086 supports 256 interrupt types (0–255). Each type has a 4-byte entry in
the Interrupt Vector Table (IVT), stored at physical addresses
00000H–003FFH. Each entry contains a 16-bit IP and 16-bit CS pointing to
the Interrupt Service Routine (ISR).

10.1 Types of Interrupts

Type Sub-type Description

Hardware NMI
Rising edge on NMI pin → Type 2 interrupt. Cannot be maske
(External) (Non-Maskable)

Hardware INTR
Level-triggered on INTR pin. Only serviced if IF=1 (STI). CPU
(External) (Maskable)

Software
INT n Explicit software interrupt. Pushes FLAGS, CS, IP; clears IF a
(Internal)

Software
INTO INT 4 if OF=1; otherwise no operation.
(Internal)

Software Single-Step
Generated after each instruction when TF=1. Used by debugg
(Internal) (INT 1)

Software Divide Error

Generated automatically when DIV or IDIV produces a quotien
(Internal) (INT 0)

10.2 Interrupt Sequence (INTR)

When an INTR is accepted, the 8086 performs the following steps in order:
1. Finish executing the current instruction.
2. If IF=1: send two INTA′ pulses to the interrupting device.
3. Device places the 8-bit interrupt type number on D■–D■.
4. CPU pushes FLAGS onto the stack; clears IF and TF.
5. CPU pushes CS then IP onto the stack.
6. CPU reads IVT entry at physical address = type × 4.
7. CS ← IVT[type+2]; IP ← IVT[type]; execution continues at ISR.
8. ISR ends with IRET: pops IP, CS, FLAGS from stack.
10.3 Predefined Interrupt Types (0–7)
Type Name Trigger

0 Divide Error DIV/IDIV overflow

1 Single-Step TF = 1 (after each instruction)

2 NMI Rising edge on NMI pin

3 Breakpoint INT 3 instruction (1-byte opcode = CCH)

4 Overflow INTO instruction when OF=1

5 Array Bounds (80186+) BOUND instruction violation

6 Invalid Opcode (80186+) Undefined instruction

7 No Co-processor (80186+) ESC instruction with no 8087

11. MEMORY ORGANISATION AND SEGMENTATION
The 8086 has a 20-bit physical address bus, enabling access to 1 MB
(1,048,576 bytes) of memory (addresses 00000H to FFFFFH). To manage
this large space with 16-bit registers, 8086 uses memory segmentation.

11.1 Segmentation Concept

• Memory is divided into logical segments of up to 64 KB each.
• A segment starts at any 16-byte boundary (paragraph boundary) — i.e.
its physical start address is always divisible by 16.
• A segment register holds the paragraph number (upper 16 bits of the
20-bit start address).
• An offset register holds the offset within the segment (0000H–FFFFH).
• Physical Address = Segment × 10H + Offset (i.e. shift segment left 4
bits and add offset).

Example:
CS = 1234H, IP = 0100H
Physical Address = 1234H × 10H + 0100H = 12340H + 0100H
= 12440H

11.2 Segment Defaults

Operation Default Segment
Default Offset
Override Possible?

Instruction Fetch CS IP No

Stack PUSH/POP SS SP No

Data read/write (general)DS EA Yes (CS/SS/ES)

String Source (LODS/MOVS)

DS SI Yes

String Destination (STOS/MOVS)

ES DI No

BP as base register SS EA Yes

BX, SI, DI as base/indexDS EA Yes

11.3 Memory Bank Organisation

8086 organises memory as two independent banks of 512 KB each:
• Even Bank (Bank 0): Connected to D■–D■ (low byte). Selected when
A■=0.
• Odd Bank (Bank 1): Connected to D■–D■■ (high byte). Selected
when BHE′=0.
• To read/write a 16-bit word, both banks are accessed simultaneously
(A■=0 and BHE′=0).
• To access only the even byte: A■=0, BHE′=1.
• To access only the odd byte: A■=1, BHE′=0.

A■ BHE′ Operation

0 0 16-bit word transfer (both banks)

0 1 Byte transfer — even bank (D■–D■)

1 0 Byte transfer — odd bank (D■–D■■)

1 1 No transfer (invalid)
12. BUS CYCLES AND TIMING
Every memory or I/O access by the 8086 takes place in a bus cycle. A
minimum bus cycle consists of 4 clock states: T1, T2, T3, T4. A wait state
(Tw) may be inserted between T3 and T4 when slow memory/IO is used.

State ALE AD■–AD■■ A■■–A■■ Control LinesActivity

T1 HIGH Address (A■–A■■) Address (A■■–A■■)

M/IO′ valid BIU outputs 20-bit address; ALE pulse

Floating (read)
T2 LOW Status (S■–S■)
RD′ or WR′ LOW
Bus direction set; address removed; re
Data driven (write)

Data valid (read from mem)

T3/Tw LOW Status RD′/WR′ LOWData placed on bus by memory/IO (rea
Data driven (write)

Data sampled (read)

T4 LOW Status RD′/WR′ HIGHBIU latches data (read) or releases bu
Data released (write)

Wait States (Tw):

• If READY input is LOW at end of T3, the CPU inserts one or more Tw
states (copies of T3).
• This allows slow memories (e.g. EPROM) to provide valid data without
errors.
• Fast SRAM typically needs 0 wait states at 5 MHz; DRAM and EPROM
may need 1–2.

12.2 Types of Bus Cycles

Bus Cycle Initiated by Description

Memory Read EU / BIU (fetch) BIU reads instruction byte or EU reads operand from me

Memory Write EU EU writes result/data to memory.

I/O Read EU (IN instruction) EU reads byte/word from I/O port address.

I/O Write EU (OUT instruction) EU writes byte/word to I/O port address.

Interrupt Ack CPU (on INTR) Two consecutive INTA′ cycles; device provides interrupt

Halt EU (HLT) CPU stops; ALE pulses once; bus goes idle until interrup

Idle BIU (queue full) No bus activity; BIU inserts idle (Ti) states.
13. INSTRUCTION SET QUICK REFERENCE
Mnemonic Full Name / Meaning Mnemonic Full Name / Meaning

MOV Move XCHG Exchange

ADD Add ADC Add with Carry

SUB Subtract SBB Subtract with Borrow

MUL Unsigned Multiply IMUL Signed (Integer) Multiply

DIV Unsigned Divide IDIV Signed (Integer) Divide

INC Increment DEC Decrement

NEG Negate (2's complement) CMP Compare (SUB without store)

AND Bitwise AND OR Bitwise OR

XOR Bitwise XOR NOT Bitwise NOT

TEST AND without store NOP No Operation

SHL/SAL Shift Left SHR Shift Right (logical)

SAR Shift Arithmetic Right ROL Rotate Left

ROR Rotate Right RCL Rotate Left through Carry

RCR Rotate Right through Carry PUSH Push onto Stack

POP Pop from Stack CALL Call Subroutine

RET Return from Subroutine JMP Unconditional Jump

JZ/JE Jump if Zero/Equal JNZ/JNE Jump if Not Zero/Not Equal

JC/JB Jump if Carry/Below JNC/JAE Jump if No Carry/Above-Equal

JL Jump if Less (signed) JG Jump if Greater (signed)

LOOP Loop while CX≠0 INT Software Interrupt

IRET Interrupt Return HLT Halt

CLC Clear Carry Flag STC Set Carry Flag

CMC Complement Carry CLI Clear Interrupt Flag

STI Set Interrupt Flag CLD Clear Direction Flag

STD Set Direction Flag PUSHF Push Flags to Stack

Mnemonic Full Name / Meaning Mnemonic Full Name / Meaning

POPF Pop Flags from Stack LAHF Load AH from Flags

SAHF Store AH into Flags CBW Convert Byte to Word

CWD Convert Word to Dword LEA Load Effective Address

LDS Load DS with far ptr LES Load ES with far ptr

IN Input from Port OUT Output to Port

MOVS Move String CMPS Compare String

SCAS Scan String LODS Load String

STOS Store String REP Repeat prefix

XLAT Translate AL via table WAIT Wait for TEST′ pin

LOCK Lock Bus prefix ESC Escape to Co-processor