MICROPROCESSOR (ARCHITECTURE AND PROGRAMMING)

8086 — 16 BIT MICROPROCESSOR

1. INTRODUCTION
• 8086 is an enhanced 16-bit microprocessor designed by Intel in 1976, as a successor
to the 8085.
• It has a 20-bit address bus (1 MB addressable memory) and a 16-bit data bus.
• Uses HMOS technology; housed in a 40-pin DIP package; operates on +5 V DC
supply.
• Supports Minimum mode (single processor) and Maximum mode (multi-processor /
co-processor).
• Contains approximately 29,000 transistors and supports 256 vectored interrupts.
• Two on-chip units — BIU (Bus Interface Unit) and EU (Execution Unit) — enable
pipelining.

2. FEATURES OF 8086
• 16-bit microprocessor: processes 16-bit data in one operation.
• 16-bit data bus: read/write 8-bit or 16-bit data from/to memory or I/O ports.
• 20-bit address bus: accesses up to 2²■ = 1,048,576 locations (1 MB).
• Supports up to 64K I/O ports; provides 14 internal 16-bit registers.
• Multiplexed address/data bus: AD■–AD■■ (address + data) and A■■–A■■ (address
+ status).
• Pre-fetches up to 6 instruction bytes into a FIFO queue for pipelined execution.
• Single-phase clock, 33% duty cycle; available in 5 MHz, 8 MHz, and 10 MHz versions.
• Compatible with 8087 Numeric Co-Processor for floating-point arithmetic.
3. REGISTER ORGANIZATION
8086 has 14 internal 16-bit registers in four groups: General Data, Segment, Pointer/Index,
and Flag.

3.1 General Data Registers

Each 16-bit data register splits into two independent 8-bit halves (High and Low byte).

16-bit High (8-bit) Low (8-bit) Primary Use

AX AH AL Accumulator — arithmetic, I/O, string ops

BX BH BL Base register — memory offset storage

CX CH CL Count register — LOOP, REP, shift count

DX DH DL Data register — I/O addressing, MUL/DIV

3.2 Segment Registers

8086 divides 1 MB into 64 KB segments. A segment register holds the paragraph number
(upper 16 bits of start address).
Physical Address = Segment Register × 16 + Offset

Register Name Default Offset Reg Purpose

CS Code Segment IP Points to segment containing executable code

DS Data Segment BX / SI / DI Points to segment containing program data

SS Stack Segment SP / BP Points to stack segment

ES Extra Segment DI (strings) Additional data segment; destination of string ops

3.3 Pointer and Index Registers

Reg Full Name Default Seg Purpose

IP Instruction Pointer CS Offset of next instruction to fetch (not directly accessible)

SP Stack Pointer SS Points to top of stack; updated by PUSH/POP automatically

BP Base Pointer SS Access parameters/local variables on stack

SI Source Index DS Source offset in string operations

DI Destination Index ES Destination offset in string operations

4. FLAG REGISTER (16-bit PSW)
9 of the 16 bits are used: 6 Status flags (reflect ALU result) and 3 Control flags (control
instruction behaviour).

Bit Flag Type Set when…

0 CF — Carry Status Carry out of MSB (add) or borrow (subtract)

2 PF — Parity Status Lower byte of result has even number of 1s

4 AF — Aux Carry Status Carry from bit 3 to bit 4 (BCD arithmetic)

6 ZF — Zero Status Result equals zero

7 SF — Sign Status Result is negative (equals MSB of result)

11 OF — Overflow Status Signed result too large for destination register

8 TF — Trap Control Single-step debug mode (INT 1 after each instruction)

9 IF — Interrupt Control Maskable interrupts enabled (STI sets; CLI clears)

10 DF — Direction Control String auto-decrement (1) or auto-increment (0)

Flag register bit layout:

Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Flag: — — — — OF DF IF TF SF ZF — AF — PF — CF

• PUSHF / POPF: push/pop entire 16-bit flag register to/from stack.

• LAHF: load bits 7–0 of flags into AH. SAHF: store AH back into low flag byte.
• Bits 1, 3, 5 are fixed (1, 0, 0); bits 12–15 are unused in 8086.

5. INTERNAL ARCHITECTURE OF 8086

The 8086 CPU is split into two concurrently operating units:

Unit Abbr. Key Components Responsibility

Bus Interface Unit BIU Seg. registers, IP, 6-byte queue

Fetch instructions/data; manage 20-bit address; fill pre-

Execution Unit EU ALU, GP registers, Flag reg. Decode & execute instructions; access BIU for memory

• BIU pre-fetches up to 6 bytes ahead into its FIFO queue whenever the bus is free.
• EU pulls instructions from the queue — never directly from memory — enabling
pipeline overlap.
• On JMP / CALL / branch taken: BIU flushes queue and refills from the new address.
6. PIN DIAGRAM AND PIN DESCRIPTION (40-pin DIP)
Address and data lines are time-multiplexed. During T1 they carry address; afterwards
they carry data or status.

Pin / Signal Dir. Description

AD■–AD■■ Bi Multiplexed Address (T1) / Data (T2–T4) bus — low 16 bits.

A■■–A■■/S■–S■ Out T1: upper 4 address bits. After T1: status signals S■–S■.

BHE′/S■ Out Bus High Enable (active LOW, T1) — enables D■–D■■ (odd bank).

ALE Out Address Latch Enable — HIGH pulse in T1 to latch address externally.

RD′ Out Read strobe (active LOW) — memory/IO places data on bus.

WR′ Out Write strobe (active LOW) — CPU drives data onto bus.

M/IO′ Out HIGH = memory access; LOW = I/O access.

DT/R′ Out Data Transmit/Receive — controls direction of 8286/8287 transceiver.

DEN′ Out Data Enable (active LOW) — enables 8286/8287 during data transfer.

READY In HIGH = memory/IO ready. LOW inserts Tw wait states.

INTR In Interrupt Request (active HIGH, level). Serviced if IF = 1.

INTA′ Out Interrupt Acknowledge (active LOW) — two pulses; device sends vector.

NMI In Non-Maskable Interrupt — rising-edge triggered; always serviced (Type 2).

RESET In Active HIGH (≥4 clocks) — resets CPU: CS=FFFFH, all others=0000H.

TEST′ In Used by WAIT instruction — CPU idles until TEST′ = LOW (sync with 8087).

CLK In Clock input — asymmetric square wave, 33% duty cycle (5/8/10 MHz).

MN/MX′ In HIGH = Minimum mode (single CPU); LOW = Maximum mode (multi-processor).

HOLD / RQ′/GT′ In Bus request from DMA or another master (Minimum / Maximum mode).

HLDA / RQ′/GT′ Out Hold Acknowledge — CPU surrenders bus to requesting master.

S■′,S■′,S■′ Out (Max mode) Bus cycle status — decoded by 8288 Bus Controller.

QS■, QS■ Out (Max mode) Queue status — informs 8087 about instruction queue state.

LOCK′ Out (Max mode) Prevents other masters from seizing bus (LOCK prefix).

Vcc / GND — +5 V DC supply and Ground (two GND pins).

7. STATUS AND CONTROL TABLES

7.1 S■′ S■′ S■′ — Bus Cycle Type (Maximum Mode)

S■′ S■′ S■′ Bus Cycle

0 0 0 Interrupt Acknowledge

0 0 1 I/O Read

0 1 0 I/O Write

0 1 1 Halt

1 0 0 Code Fetch (Memory Read)

1 0 1 Memory Read

1 1 0 Memory Write

1 1 1 Passive — no bus cycle

7.2 QS■ QS■ — Queue Status (Maximum Mode)

QS■ QS■ Meaning

0 0 No operation (queue idle)

0 1 First byte of opcode fetched from queue

1 0 Queue flushed (branch taken)

1 1 Subsequent byte of instruction fetched

7.3 Minimum Mode vs. Maximum Mode

Feature Minimum Mode (MN/MX′=HIGH) Maximum Mode (MN/MX′=LOW)

System type Single processor Multi-processor / 8087 co-processor

Control sigs Generated by 8086 directly Generated by external 8288 Bus Controller

Bus request HOLD / HLDA pins RQ′/GT■′ and RQ′/GT■′ pins

Status pins M/IO′, RD′, WR′, ALE, DEN, DT/R′ S■′–S■′, QS■, QS■, LOCK′

Complexity Simple — fewer chips Complex — higher performance, more chips

8. ADDRESSING MODES
An addressing mode specifies how an instruction's operand is located in memory or
registers.

# Mode EA Calculation Example

1 Immediate Operand is part of instruction. MOV AX, 1234H

2 Register Operand is in a register (fastest). MOV AX, BX

3 Direct EA = 16-bit displacement in instruction.

MOVDS:disp
AX, [0200H]

4 Reg Indirect EA = [BX], [SI], or [DI]. MOV AX, [BX]

# Mode EA Calculation Example

5 Based EA = [BX or BP] + 8/16-bit disp. MOV AX, [BX+04H]

6 Indexed EA = [SI or DI] + 8/16-bit disp. MOV AX, [SI+06H]

7 Based-Index EA = [BX/BP] + [SI/DI]. MOV AX, [BX+SI]

8 Based-Idx+D EA = [BX/BP] + [SI/DI] + disp. MOV AX,[BX+SI+05H]

9 Implicit Register implied by instruction. CLC, XLAT, AAA

10 I/O Port Direct: 8-bit port. Indirect: DX. IN AL,40H OUT DX,AL
9. INSTRUCTION SET OF 8086
8086 has ~117 base instructions grouped into 7 categories:

Category Key Instructions Purpose

Data Transfer MOV, PUSH, POP, XCHG, XLAT, IN, OUT,

Move LEA,
data between
LDS, LESregisters, memory, and I/O ports.

Arithmetic ADD, ADC, SUB, SBB, MUL, IMUL, DIV,

Arithmetic
IDIV, INC,
on DEC,
binaryNEG,
and BCD
CMP,
operands.
CBW, CWD, AAA, DAA

Logical / Bit AND, OR, XOR, NOT, TEST, SHL, SHR,

Bitwise
SAR,logic
ROL,and
ROR,
shift/rotate
RCL, RCR operations.

String MOVS, CMPS, SCAS, LODS, STOS +Operate

REP/REPE/REPNE
on byte/wordprefixes
arrays in memory.

Control Transfer JMP, Jcc, LOOP, LOOPE, LOOPNE, CALL,

Alter program
RET, INT,
execution
IRET, INTO
flow.

Processor Control CLC, STC, CMC, CLD, STD, CLI, STI,Control

HLT, NOP,
flagsWAIT,
and processor
LOCK, ESC
state.

Flag Operations LAHF, SAHF, PUSHF, POPF Direct access to the Flag register.

9.1 Data Transfer Instructions

Instr. Syntax Action

MOV MOV dst,src Copy src → dst. Flags not affected.

PUSH PUSH src SP←SP−2; [SS:SP]←src (16-bit push).

POP POP dst dst←[SS:SP]; SP←SP+2.

XCHG XCHG op1,op2 Exchange op1 and op2. Flags not affected.

IN IN AL/AX, port Read byte/word from I/O port into AL or AX.

OUT OUT port, AL/AX Write AL or AX to I/O port.

LEA LEA reg16,mem Load effective address of mem operand into reg16.

LDS LDS reg16,mem32 reg16←offset, DS←segment (load far pointer).

LES LES reg16,mem32 reg16←offset, ES←segment (load far pointer).

XLAT XLAT AL←DS:[BX+AL] — translate byte via lookup table.

9.2 Arithmetic Instructions
Instr. Syntax Action / Flags Affected

ADD ADD dst,src dst←dst+src. Affects CF OF SF ZF PF AF.

ADC ADC dst,src dst←dst+src+CF. Multi-word addition.

SUB SUB dst,src dst←dst−src. Affects all status flags.

SBB SBB dst,src dst←dst−src−CF. Multi-word subtraction.

INC INC dst dst←dst+1. CF not affected.

DEC DEC dst dst←dst−1. CF not affected.

NEG NEG dst dst←0−dst (two's complement negation).

CMP CMP op1,op2 op1−op2; result discarded, flags updated only.

MUL MUL src Unsigned: AX←AL×src(byte); DX:AX←AX×src(word).

IMUL IMUL src Signed multiply (same register usage as MUL).

DIV DIV src Unsigned: AL←AX÷src(quot), AH←remainder(byte).

IDIV IDIV src Signed division (same register usage as DIV).

CBW CBW Sign-extend AL into AX.

CWD CWD Sign-extend AX into DX:AX.

9.3 Logical and Bit-Manipulation Instructions

Instr. Syntax Action

AND AND dst,src dst←dst AND src (bitwise). CF=OF=0.

OR OR dst,src dst←dst OR src (bitwise). CF=OF=0.

XOR XOR dst,src dst←dst XOR src. CF=OF=0. XOR reg,reg clears reg.

NOT NOT dst dst←NOT dst (one's complement). Flags not affected.

TEST TEST op1,op2 op1 AND op2; result discarded; flags updated.

SHL/SAL SHL dst,CL Shift left; 0 fills from right; MSB→CF.

SHR SHR dst,CL Logical shift right; 0 fills from left; LSB→CF.

SAR SAR dst,CL Arithmetic shift right; sign bit replicated; LSB→CF.

ROL ROL dst,CL Rotate left; MSB wraps to LSB and to CF.

ROR ROR dst,CL Rotate right; LSB wraps to MSB and to CF.

RCL RCL dst,CL Rotate left through carry; CF inserted at LSB.

RCR RCR dst,CL Rotate right through carry; CF inserted at MSB.

9.4 Control Transfer Instructions

Unconditional / Subroutine:
Instr. Syntax Action

JMP JMP label/reg Unconditional jump (short ±128B, near ±32KB, or far).

CALL CALL proc Push return address; jump to subroutine.

RET RET [n] Pop IP (and CS if far); optionally pop n bytes from stack.

INT n INT n Push FLAGS, CS, IP; clear IF & TF; jump to IVT[n×4].

IRET IRET Pop IP, CS, FLAGS from stack (return from ISR).

INTO INTO INT 4 if OF=1; else no-op.

Conditional Jumps (Jcc):

Instruction Condition Jump if… Instruction Condition Jump if…

JZ / JE ZF=1 Zero / Equal JNZ / JNE ZF=0 Non-zero / Not equal

JC / JB CF=1 Carry / Below (unsign)JNC / JAE CF=0 No carry / Above-equal

JS SF=1 Negative result JNS SF=0 Positive result

JO OF=1 Overflow JNO OF=0 No overflow

JL / JNGE SF≠OF Less (signed) JGE / JNL SF=OF Greater-equal (signed)

ZF=1 ZF=0
JLE / JNG Less-equal JG / JNLE Greater (signed)
or SF≠OF and SF=OF

CX≠0
LOOP CX≠0 Decrement CX; loop LOOPE/Z Loop while equal
ZF=1

CX≠0
LOOPNE/NZ Loop while ≠equal — — —
ZF=0

9.5 String Instructions

SI → source in DS; DI → destination in ES. DF=0: auto-increment; DF=1: auto-decrement.

Instruction Action

MOVS / MOVSB / MOVSW Copy DS:[SI] → ES:[DI]; update SI and DI.

CMPS / CMPSB / CMPSW Compare DS:[SI] with ES:[DI]; update flags, SI, DI.

SCAS / SCASB / SCASW Compare AL/AX with ES:[DI]; update flags and DI.

LODS / LODSB / LODSW Load DS:[SI] into AL/AX; update SI.

STOS / STOSB / STOSW Store AL/AX into ES:[DI]; update DI.

REP Repeat while CX ≠ 0 (used with MOVS, STOS).

REPE / REPZ Repeat while CX ≠ 0 AND ZF = 1 (used with CMPS, SCAS).

REPNE/REPNZ Repeat while CX ≠ 0 AND ZF = 0 (find non-matching byte).

10. INTERRUPT SYSTEM OF 8086
8086 supports 256 interrupt types (0–255). Each has a 4-byte entry in the Interrupt Vector
Table (IVT) at physical addresses 00000H–003FFH. Entry = 2-byte IP + 2-byte CS of the
ISR.

10.1 Classification of Interrupts

Class Sub-type Description

Hardware
NMI (Non-Maskable) Rising edge on NMI pin → Type 2. Cannot be masked. Always serviced.
(External)

Hardware
INTR (Maskable) Level HIGH on INTR pin. Serviced only if IF=1. CPU reads type # from bus.
(External)

Software
INT n Explicit instruction. Pushes FLAGS, CS, IP; clears IF & TF; jumps to IVT[n].
(Internal)

Software
INTO Generates INT 4 if OF=1; otherwise no action.
(Internal)

Software
Single-Step (INT 1) Generated after each instruction when TF=1. Used by debuggers.
(Internal)

Software
Divide Error (INT 0) Auto-generated when DIV/IDIV quotient overflows destination register.
(Internal)

10.2 Interrupt Acknowledge Sequence (INTR)

1. CPU finishes current instruction.
2. Sends two INTA′ pulses to the requesting device.
3. Device places 8-bit interrupt type number on D■–D■.
4. CPU pushes FLAGS onto stack; clears IF and TF.
5. CPU pushes CS then IP onto stack.
6. CPU reads IVT: physical addr = type × 4.
7. CS ← IVT[type+2]; IP ← IVT[type]; jump to ISR.
8. ISR ends with IRET: pops IP, CS, FLAGS from stack.

10.3 Predefined Interrupt Types

Type Name Triggered by

0 Divide Error DIV or IDIV overflow (quotient too large)

1 Single-Step TF = 1 (after each instruction)

2 NMI Rising edge on NMI pin

3 Breakpoint INT 3 instruction (1-byte opcode = CCH)

4 Overflow INTO instruction when OF = 1

11. MEMORY ORGANISATION AND SEGMENTATION
20-bit address bus → 1 MB (00000H–FFFFFH). Managed via segmentation: memory is
divided into logical 64 KB segments.

11.1 Segmentation
• Every segment starts at a paragraph boundary (address divisible by 16).
• Segment register holds the paragraph number; offset register holds position within
segment.
• Physical Address = Segment × 10H + Offset.
Example:
CS = 1234H, IP = 0100H
Physical Address = 12340H + 0100H = 12440H

11.2 Segment Defaults

Operation Default Segment Default Offset Override?

Instruction Fetch CS IP No

Stack PUSH / POP SS SP No

General data read/write DS EA Yes (CS/SS/ES)

String source (LODS/MOVS) DS SI Yes

String destination (STOS/MOVS)ES DI No

BP as base register SS EA Yes

BX, SI, DI as index DS EA Yes

11.3 Memory Bank Organisation

8086 organises 1 MB into two independent 512 KB banks to support both 8-bit and 16-bit
accesses:
• Even Bank (Bank 0): Connected to D■–D■. Selected when A■ = 0.
• Odd Bank (Bank 1): Connected to D■–D■■. Selected when BHE′ = 0.

A■ BHE′ Operation

0 0 16-bit word transfer (both banks simultaneously)

0 1 8-bit byte — even bank only (D■–D■)

1 0 8-bit byte — odd bank only (D■–D■■)

1 1 No transfer (invalid combination)

12. BUS CYCLES AND TIMING

Every memory/IO access is a bus cycle consisting of at least 4 clock states (T1–T4). Slow
devices insert wait states (Tw) between T3 and T4.
State ALE AD■–AD■■ Control Activity

T1 HIGH Address A■–A■■ M/IO′ valid BIU drives 20-bit address; ALE latches it externa

T2 LOW Float (read) / Data (write) RD′ or WR′ LOW Address removed; bus direction set; RD′/WR′ ass

T3/Tw LOW Data (mem→CPU or CPU→mem)

RD′/WR′ LOW Data on bus; READY sampled at end of T3. Tw a

T4 LOW Data latched (read) RD′/WR′ HIGH BIU latches incoming data or CPU releases bus.
13. INSTRUCTION QUICK REFERENCE
Mnemonic Meaning Mnemonic Meaning

MOV Move XCHG Exchange

ADD Add ADC Add with Carry

SUB Subtract SBB Subtract with Borrow

MUL Unsigned Multiply IMUL Signed Multiply

DIV Unsigned Divide IDIV Signed Divide

INC Increment (+1) DEC Decrement (−1)

NEG Negate (2's complement) CMP Compare (SUB, no store)

AND Bitwise AND OR Bitwise OR

XOR Bitwise XOR NOT Bitwise NOT (1's comp)

TEST AND without store NOP No Operation

SHL Shift Left SHR Shift Right (logical)

SAR Shift Arithmetic Right ROL Rotate Left

ROR Rotate Right RCL Rotate Left thru Carry

RCR Rotate Right thru Carry PUSH Push onto Stack

POP Pop from Stack CALL Call Subroutine

RET Return from Subroutine JMP Unconditional Jump

JZ/JE Jump if Zero / Equal JNZ Jump if Not Zero

JC/JB Jump if Carry / Below JNC Jump if No Carry

JL Jump if Less (signed) JG Jump if Greater (signed)

LOOP Loop while CX≠0 INT Software Interrupt

IRET Interrupt Return INTO INT 4 if OF=1

CLC Clear Carry Flag STC Set Carry Flag

CMC Complement Carry CLI Clear Interrupt Flag

STI Set Interrupt Flag CLD Clear Direction Flag

STD Set Direction Flag HLT Halt CPU

PUSHF Push Flags to Stack POPF Pop Flags from Stack

LAHF Load AH ← Flags low byte SAHF Store AH → Flags low byte

CBW Convert Byte→Word (AX) CWD Convert Word→DWord (DX:AX)

LEA Load Effective Address XLAT Translate AL via DS:[BX+AL]

IN Input from I/O Port OUT Output to I/O Port

MOVS Move String CMPS Compare String

SCAS Scan String LODS Load String

Mnemonic Meaning Mnemonic Meaning

STOS Store String REP Repeat String Prefix

LDS Load DS far pointer LES Load ES far pointer

WAIT Wait for TEST′ pin LOW LOCK Lock Bus prefix

ESC Escape to Co-processor BOUND Check array bounds (80186+)

14. SAMPLE ASSEMBLY PROGRAMS

Program 1 — Add two 16-bit numbers:

MOV AX, 1234H ; load first number into AX
MOV BX, 0AB5H ; load second number into BX
ADD AX, BX ; AX ← AX + BX (result in AX)
MOV [RESULT], AX ; store result in memory
HLT ; halt

Program 2 — Copy a block of 10 bytes:

MOV CX, 10 ; counter = 10
LEA SI, SOURCE ; DS:SI → source buffer
LEA DI, DEST ; ES:DI → destination buffer
CLD ; DF=0 → auto-increment
REP MOVSB ; move CX bytes
HLT

Program 3 — Find largest number in an array (5 elements):

MOV CX, 4 ; compare CX times
MOV SI, OFFSET ARR
MOV AL, [SI] ; AL ← first element (assume max)
NEXT: INC SI
CMP AL, [SI] ; compare AL with next element
JAE SKIP ; if AL >= [SI], skip
MOV AL, [SI] ; else update max
SKIP: LOOP NEXT
MOV [MAX], AL ; store largest value
HLT

15. SUMMARY — KEY FACTS AT A GLANCE

Parameter Value / Detail

Data bus width 16 bits

Address bus width 20 bits

Addressable memory 1 MB (00000H – FFFFFH)

I/O ports supported 64K ports (0000H – FFFFH)

Internal registers 14 × 16-bit registers

Pre-fetch queue 6 bytes (FIFO)

Pipelining stages 2 (Fetch in BIU + Execute in EU)

Interrupt types 256 (Types 0–255); IVT at 00000H–003FFH

Operating modes Minimum (single CPU) / Maximum (multi-CPU)

Clock frequencies 5 MHz (8086) / 8 MHz (8086-2) / 10 MHz (8086-1)

Supply voltage +5 V DC
Parameter Value / Detail

Package 40-pin DIP

Technology HMOS (High-speed MOS)

Transistor count ~29,000

Co-processor 8087 Numeric Data Processor (floating-point)

Physical address formula Segment × 10H + Offset