MICROPROCESSOR ARCHITECTURE AND

PROGRAMMING
Intel 8086 — 16-Bit Microprocessor

1. Introduction
• The 8086 is an enhanced version of the 8085 Microprocessor, designed by Intel in 1976.
• It is a 16-bit Microprocessor with 20 address lines and 16 data lines, providing up to 1 MB of
storage.
• It features a powerful instruction set supporting multiplication and division.
• It supports two modes of operation:
◦ Maximum Mode — suitable for systems with multiple processors.
◦ Minimum Mode — suitable for systems with a single processor.

2. 8086 Microprocessor Features

Feature Description
Data Bus Width 16-bit (reads/writes 8 or 16 bits at a time)
Address Bus 20-bit (accesses up to 1 MB memory)
I/O Ports Supports up to 64K I/O ports
Registers 14 registers, each 16-bit wide
Bus Type Multiplexed address/data bus (AD0–AD15, A16–A19)
Clock Single phase, 33% duty cycle
Pipeline Stages Fetch Stage + Execute Stage
Instruction Queue Pre-fetches up to 6 bytes
Interrupts 256 vectored interrupts
Transistor Count 29,000 transistors
Operating Modes Minimum mode & Maximum mode
Frequency Versions 8086 → 5 MHz | 8086-2 → 8 MHz | (c)8086-1 → 10 MHz

3. Register Organization
The 8086 has a powerful set of registers. All are 16-bit registers, classified into:
• General Data Registers
• Segment Registers
• Pointers and Index Registers
• Flag Register
3.1 General Data Registers (AX, BX, CX, DX)
These can function as either 8-bit or 16-bit registers.
• AX — 16-bit accumulator. Lower 8 bits = AL; Higher 8 bits = AH. AL is used as 8-bit
accumulator.
• BX — Used as offset storage for physical address in certain addressing modes. BL = lower 8
bits; BH = higher 8 bits.
• CX — Default counter for string and loop instructions.
• DX — General-purpose register; may be used as implicit operand or destination in certain
instructions.

3.2 Segment Registers (CS, DS, ES, SS)

There are 4 segment registers. The 8086 uses segmented memory — 1 MB divided into 16 logical
segments of 64 KB each.
• CS (Code Segment) — Used for addressing the code segment where the executable
program is stored.
• DS (Data Segment) — Points to the data segment where program data is stored.
• ES (Extra Segment) — Refers to another data segment in memory.
• SS (Stack Segment) — Addresses the stack segment used to store stack data.
Physical Address Calculation:
Physical Address = Segment Address + Offset Address

3.3 Pointers and Index Registers

• IP (Instruction Pointer) — Stores memory location of the next instruction to be executed.
• BP (Base Pointer) — Contains offset within the data segment.
• SP (Stack Pointer) — Contains offset within the stack segment.
• SI (Source Index) — Stores offset of source data in the data segment.
• DI (Destination Index) — Stores offset of destination in data or extra segment.
Index registers are especially useful for string manipulation and indexed addressing modes.

3.4 Flag Register

The 8086 uses a 16-bit flag register divided into two parts:
• Condition Code (Status) Flags — lower byte, identical to 8085 flags plus an Overflow flag.
• Machine Control Flags — higher byte; contains Direction (D), Interrupt (I), and Trap (T) flags.

Flag Name Description

SF Sign Flag Set when result of computation is negative; equals MSB of result
ZF Zero Flag Set when result of computation or comparison is zero
Parity
PF Set to 1 if lower byte of result contains even number of 1s
Flag
Carry
CF Set on carry out of MSB (addition) or borrow (subtraction)
Flag
Auxiliary
AF Carry Set on carry from bit 3 (BCD arithmetic)
Flag
 Overflow
OF Set when signed result is too large for destination register
Flag
TF Trap Flag Enables single-step execution mode; transfers control to Trap ISR
Interrupt
IF When set, maskable interrupts are recognized by CPU
Flag
Direction
DF 0 = auto-increment (low to high); 1 = auto-decrement (high to low)
Flag

4. Architecture of 8086
The 8086 CPU is divided into two independent functional units:
• Bus Interface Unit (BIU)
• Execution Unit (EU)
Dividing work between these two units speeds up processing.

4.1 Execution Unit (EU)

• Tells the BIU where to fetch instructions or data, decodes instructions, and executes them.
• Contains control circuitry that directs all internal operations.
• Has a decoder that translates fetched instructions into a series of actions.
• Has a 16-bit ALU capable of ADD, SUB, AND, OR, XOR, increment, decrement,
complement, and shift.
EU Steps:
◦ Extracts instructions from the top of the queue in BIU.
◦ Decodes the instructions.
◦ Generates operands if necessary.
◦ Passes operands to BIU and requests read/write bus cycles to memory or I/O.
◦ Performs the specified operation on operands.

4.2 Bus Interface Unit (BIU)

• Sends out addresses, fetches instructions from memory, reads data from ports and memory,
and writes data to ports and memory.
• Handles all data and address transfers on buses for the EU.
• EU has no direct connection with system buses — all operations go through BIU via the
Internal Bus.

4.3 Pipelining Architecture

• While EU decodes/executes instructions not requiring the buses, BIU pre-fetches up to 6
instruction bytes.
• Pre-fetched bytes are stored in a FIFO register set called a queue.
• When EU is ready, it reads its next instruction from the queue — much faster than fetching
from memory.
• Exception: JMP and CALL instructions cause the queue to be dumped and reloaded from a
new address.
Fetching the next instruction while the current instruction executes is called pipelining.
5. Pin Diagram of 8086
Intel 8086 is a 16-bit HMOS microprocessor available in a 40-pin DIP chip. It uses a 5V DC supply.
The 20 address bus lines operate in multiplexed mode. The 16 low-order address bus lines are
multiplexed with data and 4 high-order lines are multiplexed with status signals.

5.1 Pin Descriptions

• AD0–AD15 — Address/Data bus (low-order, multiplexed with data). When used as address:
A0–A15. When used as data: D0–D15.
• A16–A19 — High-order address bus; multiplexed with status signals.
• S2, S1, S0 — Status pins, active during T4, T1, and T2 states.

S2 S1 S0 Characteristics
0 0 0 Interrupt Acknowledge
0 0 1 Read I/O Port
0 1 0 Write I/O Port
0 1 1 Halt
1 0 0 Code Access / Read Memory
1 1 0 Write Memory
1 1 1 Passive State

• A16/S3, A17/S4, A18/S5, A19/S6 — 4 address/status buses. Carry 4-bit address during first
clock cycle, then status signals.
• BHE'/S7 — Bus High Enable/Status. Active low during T1. Enables data on D8–D15.
Multiplexed with status signal S7.
• RD' — Read signal (active low output). Used for read operations.
• READY — Acknowledgement from memory/slow device that data transfer is complete.
Active high (1).
• INTR — Interrupt Request. Sampled during last clock cycle of each instruction.
• NMI — Non-Maskable Interrupt. Edge-triggered; triggers a Type II interrupt.
• INTA — Interrupt Acknowledge. Active low during T2, T3, and Tw of interrupt acknowledge
cycle.
• MN/MX' — Minimum/Maximum. Indicates which mode the processor operates in.
• RQ'/GT1', RQ'/GT0' — Request/Grant signals for multiprocessor bus control. RQ/GT0 has
higher priority.
• LOCK' — Active low. Prevents other bus masters from gaining system bus control.
• RESET — Forces processor to terminate current activity immediately. Must be active high
(1) for at least 4 clock cycles.
• TEST' — Examined by WAIT instruction. If TEST goes low (0), execution continues; else
processor idles.
• CLK — Clock Input. Asymmetric square wave with 33% duty cycle for timing.
• Vcc — Power Supply (+5V DC).
• GND — Ground.
• QS1, QS0 — Queue Status signals indicating status of internal 8086 instruction queue.
 QS0 QS1 Status
0 0 No operation
0 1 First byte of opcode fetched from queue
1 0 Empty the queue
1 1 Subsequent byte fetched from queue

• DT/R — Data Transmit/Receive. Controls data flow direction through 8286/8287 transceiver.
• DEN — Data Enable. Output enable for 8286/8287; active low during memory/IO access and
INTA cycles.
• HOLD/HOLDA — HOLD (active high) signals another master requests local bus. Processor
issues HLDA as acknowledgement during T4 or T1.
• ALE — Address Latch Enable. Active high pulse during T1 to latch address into 8282/8283.
Never floated.

6. Addressing Modes
Addressing modes specify how the data operand for an instruction is located — whether it is
immediate data, an address, a register, or a register pair.

Mode Description Example

Data operand is part of the
1. Immediate MOV AX, 05H
instruction itself
2. Register Both operands are registers MOV CX, AX | ADD BX, AX
3. Displacement / Effective address given directly
MOV AX, [DISP] | MOV AX, [0500]
Direct in instruction
Address held in register (BP,
4. Register Indirect MOV AX, [BX] | ADD CX, [BX]
BX, DI, SI)
Offset = BX/BP register + 8/16- MOV DX, [BX+04] | ADD CL,
5. Based
bit displacement [BX+08]
Offset = SI/DI register + 8/16-bit MOV BX, [SI+16] | ADD AL,
6. Indexed
displacement [DI+16]
ADD AX, [BX+SI] | MOV CX,
7. Based-Index Offset = [BX/BP] + [SI/DI]
[BX+SI]
8. Based-Index + Offset = [BX/BP] + [SI/DI] + MOV AX, [BX+SI+05] | MOV AL,
Displacement 8/16-bit displacement [SI+BP+2000]

7. Instruction Set
The 8086 instructions are categorized into the following main types:
• Data Transfer Instructions
• Arithmetic Instructions
• Program Control Transfer Instructions
• Machine Control Instructions
 • Shift / Rotate Instructions
• Flag Manipulation Instructions
• String Instructions

8. Key Terminologies

Abbreviation Full Form / Meaning

AH 16-bit Accumulator (Higher byte)
AL 8-bit Accumulator (Lower byte)
MOV Move data
SI Source Index Register
DI Destination Index Register
INT Interrupt
INC Increment
ADD Addition
SUB Subtraction
MUL Multiplication
DIV Division
JNC Jump if No Carry
JZ Jump if Zero
ROL Rotate Left
CMP Compare
NEG Negate
ORG Origin
DB Define Byte
DW Define Word
NMI Non-Maskable Interrupt