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Tutorial 6

This tutorial focuses on hands-on experience with logic optimization using Yosys in the VLSI design flow. It outlines the requirements, including necessary files and previous tutorials for installation. The experiment involves running Yosys to observe resource sharing and its impact on area reduction.

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d.k.mahi05
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3 views1 page

Tutorial 6

This tutorial focuses on hands-on experience with logic optimization using Yosys in the VLSI design flow. It outlines the requirements, including necessary files and previous tutorials for installation. The experiment involves running Yosys to observe resource sharing and its impact on area reduction.

Uploaded by

d.k.mahi05
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

VLSI Design Flow: RTL To GDS (NPTEL Course)

Tutorial 6

Objective: To gain a hands-on experience on Logic Optimization using Yosys

Requirement:

• Yosys: The installation and how to run Yosys is described in Tutorial 5. Please refer to
it if you do not have Yosys installed on your machine.
• Files:
o Design file: top.v
o Yosys script files: [Link], not_opt.tcl
o Technology library: [Link]
All the above files are available on the NPTEL website as study material for Week 6

Optimization:

From Lecture 13 (Resource Sharing):

if (sel == 1’b0) z = a*b;


else z = x*y;

Experiment: Run Yosys and observe resource sharing and how it leads to decrease in area.

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