8085
GUEST LECTURE · UG ENGINEERING
8085 Microprocessor
Internal Architecture · Pin Diagram · Timing Diagrams
A first course in Microprocessors & Microcontrollers
8085 MICROPROCESSOR 1
LECTURE ROADMAP
What We'll Cover Today
01 02 03 04
Internal Pin Diagram Bus & Signal Roles Timing Diagrams
Architecture
ALU, registers, flags, All 40 pins grouped by Address/data multiplexing, T-states, machine cycles, and
instruction decoder & function — buses, control, control & status signals in how instructions actually
control unit power, interrupts action execute
8085 MICROPROCESSOR 2
PART 1
Internal Architecture
ALU, registers, flags, and the control unit that ties them together
8085 MICROPROCESSOR 3
INTRODUCTION
The Intel 8085 at a Glance
8-bit CPU 40-pin DIP
• •
8-bit data bus, 16-bit address bus — addresses up to 64 KB of
Single +5V supply, NMOS technology, packaged as a 40-pin IC
memory
Single clock cycle 6 general registers
• •
On-chip clock generator — needs only an external crystal (X1, X2) B, C, D, E, H, L — usable singly or as register pairs BC, DE, HL
5 hardware interrupts Multiplexed AD bus
• •
TRAP, RST 7.5, RST 6.5, RST 5.5, INTR with vectored/non-vectored
Lower 8 address lines are time-shared with the data bus (AD0–AD7)
types
PART 1 · ARCHITECTURE 4
INTERNAL ARCHITECTURE
8085 Block Diagram
ACCUMULATOR (8-bit) GENERAL PURPOSE REGISTERS
B–C D–E H–L
TEMP. REGISTER
STACK POINTER (SP) — 16 bit
ALU
PROGRAM COUNTER (PC) — 16 bit
INTERNAL DATA BUS
Arithmetic & Logic Unit
FLAG REGISTER INCREMENTER / DECREMENTER
S Z AC P CY
INTERRUPT CONTROL
INSTRUCTION REGISTER
TRAP RST7.5 RST6.5 RST5.5 INTR
& DECODER
SERIAL I/O CONTROL
SID / SOD
TIMING & CONTROL UNIT
generates ALE, RD, WR, IO/M ADDRESS BUFFER (A8–A15)
Address Bus (16) → A0–A15 Data Bus (8) → D0–D7
PART 1 · ARCHITECTURE 5
INTERNAL ARCHITECTURE
Arithmetic & Logic Unit (ALU)
What the ALU does Data Path into the ALU
• Performs all arithmetic operations: addition, subtraction, increment,
decrement REGISTER / MEMORY ACCUMULATOR
• Performs logical operations: AND, OR, XOR, NOT, compare
• Performs bit-shift and rotate operations on the accumulator
• One operand always comes from the Accumulator; result is stored
ALU
back in it
• The second operand comes from a register, memory, or the
Temporary Register
• Every operation updates the Flag Register (S, Z, AC, P, CY)
ACCUMULATOR FLAGS (SZ AC P CY)
Result Status
PART 1 · ARCHITECTURE 6
INTERNAL ARCHITECTURE
General-Purpose Registers
Six 8-bit registers — B, C, D, E, H, L — usable individually, or paired for 16-bit operations.
B C D E H L
8 bit 8 bit 8 bit 8 bit 8 bit 8 bit
BC pair DE pair HL pair (also a memory pointer)
Combine → 16-bit register pair for double operations Combine → 16-bit register pair for double operations Combine → 16-bit register pair for double operations
(LXI, DAD, PUSH, POP) (LXI, DAD, PUSH, POP) (LXI, DAD, PUSH, POP)
Note: the Accumulator (A) is also a register, but it always works with the ALU and cannot pair up with another register.
PART 1 · ARCHITECTURE 7
INTERNAL ARCHITECTURE
Special-Purpose Registers & the Flag Register
Program Counter The Flag (Status) Register — 8 bits
PC D7 D6 D5 D4 D3 D2 D1 D0
16-bit — holds the address of the NEXT instruction to be fetched
S Z — AC — P — CY
Stack Pointer CY — Carry: set when an arithmetic op generates/borrows a carry out of D7
SP
P — Parity: set when the result has an even number of 1-bits
16-bit — holds the address of the top of the stack in memory
AC — Auxiliary Carry: carry out of bit 3 — used internally for BCD (decimal)
arithmetic
Z — Zero: set when the result of an operation is zero
Instruction Register
S — Sign: copies the MSB (D7) of the result — 1 means negative
Holds the opcode byte fetched from memory while it is being decoded by the
instruction decoder — invisible to the programmer.
PART 1 · ARCHITECTURE 8
INTERNAL ARCHITECTURE
Instruction Decoder & Timing / Control Unit
Instruction Register Instruction Decoder Timing & Control Unit
Latches the opcode byte fetched from Decodes the opcode into the specific micro- Generates all control & status signals: ALE,
memory in the first machine cycle operations the CPU must perform RD̄ , WR̄ , IO/M̄, S0, S1 — synchronized to the
clock
Why this matters for timing diagrams
Once the decoder identifies the instruction, the Timing & Control Unit knows exactly how many machine cycles and T-states are needed — and drives ALE,
RD̄, WR̄ and IO/M̄ at the precise clock edges we will trace in Part 3.
PART 1 · ARCHITECTURE 9
PART 2
Pin Diagram
All 40 pins of the 8085, grouped by function
8085 MICROPROCESSOR 10
PIN DIAGRAM
40-Pin Package — Signal Groups
The 8085 is packaged as a 40-pin DIP. Every pin belongs to one of five functional groups — knowing the group tells you what the pin does before you
memorize its name.
Address / Data Bus Control & Status Power, Clock & Interrupts Serial I/O &
Reset Handshake
AD0–AD7 ALE, RD̄, WR̄, Vcc, Vss, X1, X2, TRAP, RST SID, SOD, HOLD,
(multiplexed), A8– IO/M̄, S0, S1 CLK OUT, RESET 7.5/6.5/5.5, INTR, HLDA, READY
A15 IN/OUT INTA
21 pins 6 pins 7 pins 6 pins 5 pins
PART 2 · PIN DIAGRAM 11
PIN DIAGRAM
8085 — Complete Pin Configuration
4
X1 1
0
Vcc
3
X2 2
9
HOLD
3
RESET OUT 3
8
HLDA
3
SOD 4
7
CLK (OUT)
3
SID 5
6
RESET IN
3
TRAP 6 READY
8085 5
3
RST 7.5 7
4
IO/M̅
3
RST 6.5 8
3
S1
3
RST 5.5 9
2
RD̅
1 3
INTR 0 1
WR̅
1 3
INTA 1 0
ALE
1 2
AD0 2 9
S0
1 2
AD1 3 8
A15
1 2
AD2 4 7
A14
1 2
AD3 5 6
A13
1 2
AD4 6 5
A12
1 2
AD5 7 4
A11
1 2
AD6 8 3
A10
1 2
AD7 9 2
A9
2 2
Vss 0 1
A8
PART 2 · PIN DIAGRAM 12
PIN DIAGRAM
Address / Data Bus & Control-Status Signals
Address / Data Bus (21 pins) Control & Status Signals (6 pins)
AD0 – AD7 ALE
Address Latch Enable — high pulse in T1 tells external latch to capture A0–A7 from the
Multiplexed bus: carries the LOW-order address (A0–A7) during T1, then the
AD bus.
8-bit data byte during T2/T3.
RD̅ / WR̅
A8 – A15 Active-low Read / Write strobes — tell memory or I/O when to place data on, or accept
data from, the bus.
Dedicated HIGH-order address lines — remain valid for the entire machine
cycle (not multiplexed). IO/M̅
High = I/O operation, Low = memory operation. Combines with RD̄ /WR̄ to select one of
4 operations.
Why multiplex? It keeps the package to 40 pins instead of 44+, at the cost of
S1, S0
needing an external latch (driven by ALE) to demultiplex AD0–AD7 into a stable
address. Status lines that encode the type of machine cycle in progress (opcode fetch, memory
read/write, I/O, halt, etc.).
PART 2 · PIN DIAGRAM 13
PIN DIAGRAM
Power, Clock, Reset & Interrupts
Power, Clock & Reset Interrupts — priority high to low
Vcc / Vss TRAP
+5V supply and ground reference. Highest priority, non-maskable — used for critical events like power failure.
X1, X2
RST 7.5 / 6.5 / 5.5
Connect an external crystal (or RC/LC network) — internally divided by 2 to give the
operating frequency. Vectored, maskable interrupts — each jumps to a fixed memory address.
CLK (OUT)
INTR
Buffered clock output, available for driving other peripheral ICs in the system.
General-purpose, maskable interrupt — the interrupting device supplies the instruction
RESET IN via INTA̅ .
INTA̅
Active-low input — resets PC to 0000H and disables interrupts when asserted.
RESET OUT Acknowledge output — tells the interrupting device its request was recognized.
Indicates the CPU is being reset; used to reset other devices on the bus.
PART 2 · PIN DIAGRAM 14
PIN DIAGRAM
Serial I/O & Bus Handshake Signals
SOD Serial Output Data — bit-serial data output line, set/cleared under program control (SIM instruction).
SID Serial Input Data — bit-serial data input line, read under program control (RIM instruction).
HOLD Input from another bus master (e.g. DMA controller) requesting control of the address/data bus.
HLDA Hold Acknowledge — output confirming the CPU has released the bus in response to HOLD.
READY Input used to synchronize with slow memory/peripherals — CPU waits (inserts wait states) while READY is low.
PART 2 · PIN DIAGRAM 15
PART 3
Timing Diagrams
How T-states and machine cycles drive real instruction execution
8085 MICROPROCESSOR 16
TIMING DIAGRAMS
T-States, Machine Cycles & Instruction Cycles
The Hierarchy
T-state Machine cycle Instruction cycle
1–6 machine cycles — the time to fetch & execute one
one clock period — the smallest unit of time 3–6 T-states — one bus transaction (e.g. one memory read)
instruction
Example: MVI A, 45H (2 machine cycles, 7 T-states total)
M1: Opcode Fetch T1 T2 T3 T4
M2: Memory Read T1 T2 T3
Fetch the opcode (MVI A) in M1, then read the immediate data byte 45H from the next memory location in M2.
PART 3 · TIMING DIAGRAMS 17
TIMING DIAGRAMS
The 8085's Machine Cycles
Machine Cycle T-States IO/M̄ S1 S0 Purpose
Opcode Fetch 4 (or 6) 1 0 0 Fetches the instruction byte from memory
Memory Read 3 1 1 0 Reads a data byte from memory
Memory Write 3 0 1 0 Writes a data byte to memory
I/O Read 3 1 1 1 Reads a data byte from an I/O port
I/O Write 3 0 1 1 Writes a data byte to an I/O port
Interrupt Ack. 3 (or more) 1 0 1 Acknowledges an INTR interrupt request
Bus Idle varies — No data transfer — CPU busy internally (e.g. DAD) or waiting
PART 3 · TIMING DIAGRAMS 18
TIMING DIAGRAMS
Timing Diagram — Opcode Fetch Machine Cycle
CLK
ALE
A8–A15 High-order Address (A8–A15)
AD0–AD7 Address (A0–A7) Hi-Z Data (Opcode)
(memory op)
IO/M̅
RD̅
PART 3 · TIMING DIAGRAMS 19
T1 T2 T3 T4
TIMING DIAGRAMS
Timing Diagram — Memory Read & Write Cycles
Memory Read Cycle (3 T-states)
ALE
AD0–AD7 Address Hi-Z Data In
RD̅
T1 T2 T3
Memory Write Cycle (3 T-states)
ALE
AD0–AD7 Address Data Out
WR̅
PART 3 · TIMING DIAGRAMS 20
T1 T2 T3
WRAP-UP
Key Takeaways
Architecture ALU + accumulator + flags form the compute core; 6 GP registers pair up for 16-bit data
Pin Diagram 40 pins fall into 5 groups: bus, control/status, power/clock/reset, interrupts, serial/handshake
Multiplexing AD0–AD7 carry address in T1 and data afterward — ALE tells external logic when to latch it
Timing T-states build machine cycles, machine cycles build instruction cycles — RD̄ /WR̄ /IO/M̄ drive every transfer
8085 MICROPROCESSOR 21
8085
Thank You
Questions & Discussion
8085 MICROPROCESSOR 22