ELECTRICAL & ELECTRONICS

ENGINEERING WORKSHOP
 PART A: ELECTRICAL ENGINEERING LAB

LIST OF EXPERIMENTS:

1. Verification of KCL and KVL

2. Verification of Superposition theorem
3. Measurement of Resistance using Wheat stone bridge
4. Magnetization Characteristics of DC shunt Generator
5. Measurement of Power and Power factor using Single-phase wattmeter
6. Measurement of Earth Resistance using Megger
7. Calculation of Electrical Energy for Domestic Premises

PART B: ELECTRONICS ENGINEERING LAB

LIST OF EXPERIMENTS:

1. Plot V-I characteristics of PN Junction diode A) Forward bias B) Reverse bias.

2. Plot V-I characteristics of Zener Diode and its application as voltage Regulator.
3. Implementation of half wave and full wave rectifiers
4. Plot Input & Output characteristics of BJT in CE and CB configurations
5. Frequency response of CE amplifier.
6. Simulation of RC coupled amplifier with the design supplied
7. Verification of Truth Table of AND, OR, NOT, NAND, NOR, Ex-OR, Ex-NOR gates
using ICs.
8. Verification of Truth Tables of S-R, J-K& D flip flops using respective ICs.
 [Link] VERIFICATION OF KVL AND KCL

AIM:To verify Kirchhoff’s Voltage Law and Kirchhoff’s Current Law theoretically and practically

APPARATUS:
1. KVL and KCL kit
2. Connecting wires
3. Digital multimeter

THEORY:

Ohms Law: The ratio of potential difference(V) between any two points on a conductor to the
current (I) flowing between them is constant, provided the temperature of the conductor does not
change.

KVL: The algebraic sum of the products of current and resistances in each of the conductors in any
closed path (or mesh) in a network plus the algebraic sum of the emf’s in a path is zero.

IR + emf=0

KCL: In any circuit, the algebraic sum of the currents meeting at a point(or junction) is zero.

Circuit Diagram of Ohms Law:

Circuit Diagram of KVL:

Circuit Diagram of KCL

PROCEDURE:

1. To verify ohms’ law, Connections are made as shown in theFig-1

2. Supply is given to the circuit and the readings of the voltmeters and ammeter are
noteddown
3. Ohms law can be verified by V=IR

4. To verify KVL, Connections are made as shown in theFig-2

5. Supply is given to the circuit and the readings of the voltmeters are noteddown.

6. Kirchhoff’s Voltage law can be verified byVs=V1+V2+V3.

7. To verify KCL, Connections are made as shown in theFig-3.

8. Supply is given to the circuit and the readings of the Ammeters are noteddown.

9. Kirchhoff’s Current law can be verified byI=I1+I2

THEORETICAL CALCULATIONS:

Observations Table:

Vs V1 V2 V3 V1+V2+V3 I I1 I2 I1 +I2
Theoretical
Values

Practical
Values

PRECAUTIONS:
1. Making loose connections are to beavoided.

2. Readings should be taken carefully without parallaxerror

RESULT:
 [Link] VERIFICATION OF SUPERPOSITION

AIM: Verification of the Superposition and Reciprocity Theorems.

APPARATUS:
1. Superposition Theorems trainer kit.
2. Voltmeter (0-20) V
3. Ammeter (0-200) mA.
4. Multimeter.
5. Connecting wires

Superposition Theorem:

THEORY:

“In a linear network with several independent sources which include equivalent sources due
to initial conditions and linear dependent sources, the overall response in any part of the
network is equal to the sum of the individual responses due to each independent source,
considered separately, with all other independent sources reduced to zero.”

Note: 1. the sources which are considered one at a time making all other sources zero, are
the independent sources including sources due to initial conditions only. The dependent
sources are retained as they are in the network.

2. When one independent source is considered & all other independent sources are reduced
to zero means that all the other independent voltage source is replaced with short circuit
and all the other independent current sources are replaced with open circuit. If the sources
contain internal impedances, that sources are replaced by their internal impedances.
CIRCUIT DIAGRAM:

PROCEDURE:

1. Connect the circuit as shown in the circuit diagram figure.

2. Set V1=15V, for this connect fixed 15V supply.
3. Set V2=10V, for this adjust the variable supply to 10V.
4. Note the current (I) through E&F, when both V1 and V2 are applied.
5. For the same circuit apply voltage V1 and make sure that the V2 to be shorted (V2=0) and
note down the current (I1) through E&F.
6. For the same circuit apply voltage V2 and make sure that the V1 to be shorted (V1=0) and
note down the current (I2) through E&F.
7. The Superposition Theorem is verified i.e. I=I1+I2.
8. Repeat the above procedure for different variable supplies.

OBSERVATIONS:

[Link] V1 V2 I
(volt) (volt) (mA)
 [Link] V1 I1
(volt) (mA)

[Link] V2 I2
(volt) (mA)

PRECAUTIONS:

1. Avoid loose connections.

2. Take readings without the parallax error.

RESULT:
 Expt. No:1 P-NJUNCTIONDIODECHARACTERISTICS

AIM: To plot V-I Characteristics of Silicon P-N junction Diode

APPARATUS:

[Link] Name of the apparatus Range Quantity

1 Regulator power supply (0-30 V) 1
2 Resistor 1KΩ,10KΩ 1
3 Diode (1N4007) Germanium &Silicon 1
4 Dc Ammeter (0-200)μA,(0-20)mA 2
5 DC Voltmeter (0-20) V 1
6 Bread Board 1
7 Connecting wires

THEORY:
A p-n junction diode conducts only in one direction. The V-I characteristics of the diode
are curve between voltage across the diode and current through the diode. When external voltage
is zero, circuit is open and the potential barrier does not allow the current to flow. Therefore, the
circuit current is zero. When P-type (Anode)is connected to +ve terminal and n- type (cathode) is
connected to –ve terminal of the supply voltage, is known as forward bias. The potential barrier
is reduced when diode is in the forward biased condition. At some forward voltage, the potential
barrier altogether eliminated and current starts flowing through the diode and also in the circuit.
The diode is said to be in ON state. The current increases with increasing forward voltage. When N-
type (cathode) is connected to +ve terminal and P-type (Anode) is connected to –ve terminal of the
supply voltage is known as reverse bias and the potential barrier across the junction increases.
Therefore, the junction resistance becomes very high and a very small current (reverse saturation
current) flows in the circuit. The diode is said to be in OFF state. The reverse bias current due to
minority charge carriers.
CIRCUIT DIAGRAM:

(i) FORWARD BIAS:

(ii) REVERSE BIAS:

V-I CHARACTERISTICS:
PROCEDURE:

(i) FORWARD BIAS :

1. Connections are made as per the circuit diagram.
2. For forward bias, the RPS +ve is connected to the anode of the diode and RPS –ve is
connected to the cathode of the diode,
3. Switch ON the power supply and increases the input voltage (supply voltage) in Steps.
4. Note down the corresponding current flowing through the diode and voltage across the diode
for each and every step of the input voltage.
5. The readings of voltage and current are tabulated.
6. Graph is plotted between voltage on x-axis and current on y-axis.

OBSERVATIONS:

[Link] Applied voltage Voltage across Current through Diode

(volts) Diode (volts) (mA)
PROCEDURE:

(ii) REVERSE BIAS:

1. Connections are made as per the circuit diagram.

2. For reverse bias, the RPS +ve is connected to the cathode of the diode and RPS –ve is
connected to the anode of the diode.
3. Switch ON the power supply and increase the input voltage (supply voltage) in Steps.
4. Note down the corresponding current flowing through the diode and voltage across the diode
for each and every step of the input voltage.
5. The readings of voltage and current are tabulated.
6. The Graph is plotted between voltage on x-axis and current on y-axis.

[Link] Applied Voltage across Current through Diode

voltage Diode (volts) (μA)
(volts)
PRECAUTIONS:

1. While doing the experiment do not exceed the ratings of the diode. This may lead to
damage the diode.
2. Connect voltmeter and Ammeter in correct polarities as shown in the circuit diagram.
3. Do not switch ON the power supply unless you have checked the circuit connections as per
the circuit diagram.

CALCULATIONS:

1. Cut-in Voltage of ‘Si’ diode is ___________________________

Forward Bias:

(𝒊) 𝑺𝒕𝒂𝒕𝒊𝒄 𝒇𝒐𝒓𝒘𝒂𝒓𝒅 𝑹𝒆𝒔𝒊𝒔𝒕𝒂𝒏𝒄𝒆 (𝑹𝒅𝒄) =𝑽𝒇/𝑰𝒇

(𝒊𝒊)𝑫𝒚𝒏𝒂𝒎𝒊𝒄 𝒇𝒐𝒓𝒘𝒂𝒓𝒅 𝑹𝒆𝒔𝒊𝒔𝒕𝒂𝒏𝒄𝒆 (𝒓𝒂𝒄) =𝜟𝑽𝒇/𝜟𝑰𝒇

Reverse Bias:

(𝒊)𝑺𝒕𝒂𝒕𝒊𝒄 𝒓𝒆𝒗𝒆𝒓𝒔𝒆 𝑹𝒆𝒔𝒊𝒔𝒕𝒂𝒏𝒄𝒆 (𝑹𝒅𝒄) =𝑽𝒓/𝑰𝒓

(𝒊𝒊) 𝑫𝒚𝒏𝒂𝒎𝒊𝒄 𝒓𝒆𝒗𝒆𝒓𝒔𝒆 𝑹𝒆𝒔𝒊𝒔𝒕𝒂𝒏𝒄𝒆 (𝒓𝒂𝒄) =𝜟𝑽𝒓/𝜟𝑰𝒓

RESULT:

VIVA QUESTIONS:
1. Define depletion region of a diode?
2. What is meant by transition & space charge capacitance of a diode?
3. Is the V-I relationship of a diode Linear or Exponential?
4. Define cut-in voltage of a diode and specify the values for Si and Ge diodes?
5. What are the applications of a p-n diode?
6. Draw the ideal characteristics of P-N junction diode?
7. What is the diode equation?
8. What is PIV?
9. What is the break down voltage?
10. What is the effect of temperature on PN junction diodes?
 Expt. No:2 ZENER DIODE CHARACTERISTICS

AIM: 1. To observe and draw the V-I characteristics and Regulation characteristics of a
Zener diode
2. To find the Zener Break down voltage in reverse biased condition
3. To find the Static and Dynamic resistances of Zener diode in both forward
and reverse biased conditions.
APPARATUS:

[Link] Name of the Apparatus Range Quantity

1 Zener Diode (IN 4735A) 1
2 Resistors 1KΩ 1
3 Regulated Power Supply 0-30)V DC 1
4 Bread Board 1
5 DC Ammeter (0-25)mA 1
6 DC Voltmeter (0-1)V,(0-20)V 2
7 Connecting Wires As required

CIRCUIT DIAGRAM:

(i) FORWARD BIAS:

(ii) REVERSE BIAS:

THEORY:
A zener diode is heavily doped p-n junction diode, specially made to operate in the break down
region. A p-n junction diode normally does not conduct when reverse biased. But if the reverse bias
is increased, at a particular voltage it starts conducting heavily. This voltage is called Break down
Voltage. High current through the diode can permanently damage the device To avoid high current,
we connect a resistor in series with zener diode. Once the diode starts conducting it maintains almost
constant voltage across the terminals whatever may be the current through it, i.e., it has very low
dynamic resistance. It is used in voltage regulators.

PROCEDURE:

(i) FORWARD BIAS:

1. Connections are made as per the circuit diagram.

2. The Regulated power supply voltage is increased in steps.
3. The zener current (lz), and the zener voltage (Vz.) are observed and then noted in the tabular
form.
4. A graph is plotted between zener current (Iz) on y-axis and zener voltage (Vz) on x-axis.

(ii) REVERSE BIAS:

1. Connections are made as per the circuit diagram.
2. The Regulated power supply voltage is increased in steps.
3. The voltage across the diode (Vz.) remains almost constant although the current through
the diode increases. This voltage serves as reference voltage.
4. The zener current (lz), and the zener voltage (Vz.) are observed and then noted in the
tabular form.
4. A graph is plotted between zener current (Iz) on y-axis and zener voltage (Vz) on x-axis.
OBSERVATIONS:

(i) FORWARD BIAS:

[Link] Zener Voltage (VZ) Zener Current (IZ) (mA)

(volts)

: (ii) REVERSE BIAS:

[Link] Zener Voltage (VZ) Zener Current (IZ) (mA)

(volts)

V-I CHARACTERISTICS:
PRECAUTIONS:
1. While doing the experiment do not exceed the ratings of the zener diode. This may lead to
damage the diode.
2. Connect voltmeter and Ammeter in correct polarities as shown in the circuit diagram.
3. Do not switch ON the power supply unless you have checked the circuit connections as per
the circuit diagram.
CALCULATIONS:
1. Zener Break down Voltage is ___________________________
2. Forward Bias:
(𝒊) 𝑺𝒕𝒂𝒕𝒊𝒄 𝒇𝒐𝒓𝒘𝒂𝒓𝒅 𝑹𝒆𝒔𝒊𝒔𝒕𝒂𝒏𝒄𝒆 (𝑹𝒅𝒄) =𝑽𝒇/𝑰𝒇
(𝒊𝒊)𝑫𝒚𝒏𝒂𝒎𝒊𝒄 𝒇𝒐𝒓𝒘𝒂𝒓𝒅 𝑹𝒆𝒔𝒊𝒔𝒕𝒂𝒏𝒄𝒆 (𝒓𝒂𝒄) =𝜟𝑽𝒇/𝜟𝑰𝒇
3. Reverse Bias:
(𝒊)𝑺𝒕𝒂𝒕𝒊𝒄 𝒓𝒆𝒗𝒆𝒓𝒔𝒆 𝑹𝒆𝒔𝒊𝒔𝒕𝒂𝒏𝒄𝒆 (𝑹𝒅𝒄) =𝑽𝒓/𝑰𝒓
(𝒊𝒊) 𝑫𝒚𝒏𝒂𝒎𝒊𝒄 𝒓𝒆𝒗𝒆𝒓𝒔𝒆 𝑹𝒆𝒔𝒊𝒔𝒕𝒂𝒏𝒄𝒆 (𝒓𝒂𝒄) =𝜟𝑽𝒓/𝜟𝑰𝒓

RESULT: The V-I characteristics of a zener diode are observed.

The Zener Break down voltage in reverse biased condition, Static and Dynamic resistances of
Zener diodes in both forward and reverse biased conditions are calculated.

i) The Zener Break down voltage is_____________________

ii) The Static foward resistance of Zener Diode is___________________
iii) The Dynamic forward resistance of Zener Diode is_________________
iv) The Static reverse resistance of Zener Diode is___________________
v) The Dynamic reverse resistance of Zener Diode is_________________

VIVA QUESTIONS:
1. What type of temperature Coefficient does the zener diode have?
2. If the impurity concentration is increased, how the depletion width effected?
3. Does the dynamic impendence of a zener diode vary?
4. Explain briefly about avalanche and zener breakdowns?
5. Draw the zener equivalent circuit?
6. Differentiate between line regulation & load regulation?
7. In which region zener diode can be used as a regulator?
8. How the breakdown voltage of a particular diode can be controlled?
9. What type of temperature coefficient does the Avalanche breakdown has?
10. By what type of charge carriers the current flows in zener and avalanche breakdown
diodes?
Expt. No:3a HALF WAVE RECTIFIERS (WITHOUT AND WITH C-FILTER)

AIM: 1. To obtain the load regulation and ripple factor of a half-wave rectifier by using
(a). without Filter
(b). with Filter
2. To observe the input and output waveforms of a half-wave rectifier.

APPARATUS:

[Link] Name of the Apparatus Range Quantity

1 Half wave Rectifier Kit 1
2 Digital Voltmeter (0-20)V 1
3 Digital Ammeter (0-20)mA 1
4 Digital Multimeter 1
5 Connecting wires As required

THEORY:
During positive half-cycle of the input voltage, the diode D1 is in forward bias and conducts
through the load resistor R1. Hence the current produces an output voltage across the
load resistor R1, which has the same shape as the +ve half cycle of the input voltage. During the
negative half-cycle of the input voltage, the diode is reverse biased and there is no current through the
circuit. i.e, the voltage across R1 is zero. The net result is that only the +ve half cycle of the input
voltage appears across the load. The average value of the half wave rectified o/p voltage is the value
measured on dc voltmeter.
For practical circuits, transformer coupling is usually provided for two reasons.
1. The voltage can be stepped-up or stepped-down, as needed.
2. The ac source is electrically isolated from the rectifier.
Thus preventing shock hazards in the secondary circuit.
CIRCUIT DIAGRAM:

(a) WITHOUT FILTER:

(b) WITH FILTER:

PROCEDURE:
1. Connections are made as per the circuit diagram.
2. Connect the primary side of the transformer to ac mains and the secondary side to the
rectifier input.
3. By using the multimeter, measure the ac input voltage of the rectifier and, ac and dc
voltage at the output of the rectifier.
4. Find the theoretical value of dc voltage by using the formula,
Vdc=Vm/П
Where, Vm=2Vrms, (Vrms=output ac voltage.)
Now, the Ripple factor is calculated by using the formula
Γ = ac output voltage (Vac)/dc output voltage (Vdc)
5. By increasing the value of the resistance from 1 KΩ to 10KΩ, the voltage across the load
(VL) and current (IL) flowing through the load are measured.
6. Draw a graph between load voltage (VL) and load current (IL) by taking V L on X-axis and
IL on y-axis.
7. From the value of no-load voltage (VNL) , the % regulation is to be calculated from the
theoretical calculations given below.
INPUT AND OUTPUT WAVEFORMS:

THEORETICAL CALCULATIONS FOR RIPPLE FACTOR & % REGULATION:

(a) WITH OUT FILTER:

For a Half-Wave Rectifier,
Vrms=Vm/2
Vdc=Vm/П
Therefore, Ripple factor Γ=√ (Vrms/ Vdc )2 -1 = 1.21
% regulation = [(VNL-VFL)/VFL]*100
(b) WITH FILTER:
Ripple factor for a Half-Wave Rectifier is Γ=1/ (2√3 fRC).
Where f =50Hz
C =100μF
R=(1-10)KΩ
Therefore, for 1KΩ, Ripple factor, Γ = 0.0577
% regulation = [(VNL-VFL)/VFL]*100
OBSERVATIONS:

a) WITH OUT FILTER:

VNL =______V

[Link] Load Vac(v) Vdc(v) Γ= Vac/ Vdc

Resistance
(KΩ)

(b) WITH FILTER:

VNL =______V

Load Vac(v) Vdc(v) Γ= Vac/ Vdc

[Link] Resistance
(KΩ)

PRECAUTIONS:
1. The primary and secondary sides of the transformer should be carefully identified.
2. The polarities of the diode should be carefully identified.
3. While determining the % regulation, first Full load should be applied and then it should be
decremented in steps.

RESULT:
The Ripple factor and the % regulation for the Half-Wave Rectifier with and without filters are
calculated.
1. The Ripple factor of Half-Wave Rectifier without filter is _____________________
2. The Ripple factor of Half-Wave Rectifier with filter is _____________________
3. The % Regulation of Half-Wave Rectifier without filter is _____________________
4. The % Regulation of Half-Wave Rectifier with filter is _____________________
Expt. No:3b FULL WAVE RECTIFIERS (WITHOUT AND WITH C-FILTER)

AIM: 1. To obtain the load regulation and ripple factor of a full-wave rectifier by using
(a). without Filter
(b). with Filter
2. To observe the input and output waveforms of a full-wave rectifier.

APPARATUS:

[Link] Name of the Apparatus Range Quantity

1 Full wave Rectifier Kit 1
2 Digital Voltmeter (0-20)V 1
3 Digital Ammeter (0-20)mA 1
4 Digital Multimeter 1
5 Connecting wires As required

THEORY:

The circuit of a center-tapped full wave rectifier uses two diodes D1&D2. During positive half
cycle of secondary voltage (input voltage), the diode D1 is forward biased and D2is reverse biased.
The diode D1 conducts and current flows through load resistor RL. During negative half
cycle, diode D2 becomes forward biased and D1 reverse biased. Now, D2 conducts and current
flows through the load resistor RL in the same direction. There is a continuous current flow through
the load resistor RL, during both the half cycles and will get unidirectional current as show in the
model graph. The difference between full wave and half wave rectification is that a
full wave rectifier allows unidirectional (one way) current to the load during the entire 360degrees of
the input signal and half-wave rectifier allows this only during one half cycle (180
degree).

CIRCUIT DIAGRAM:
(a) WITHOUT FILTER:

(b) WITH FILTER:

PROCEDURE:
1. Connections are made as per the circuit diagram.
2. Connect the primary side of the transformer to ac mains and the secondary side to the
rectifier input.
3. By using the multimeter, measure the ac input voltage of the rectifier and, ac and dc
voltage at the output of the rectifier.
4. Find the theoretical value of dc voltage by using the formula,
Vdc=2Vm/П
Where, Vm= √2Vrms, (Vrms=output ac voltage.)
5. Now, the Ripple factor is calculated by using the formula
Γ = ac output voltage (Vac)/dc output voltage (Vdc)
6. By increasing the value of the resistance from 1 KΩ to 10KΩ, the voltage across the load
(VL) and current (IL) flowing through the load are measured.

7. Draw a graph between load voltage (VL) and load current (IL) by taking V L on X-axis and
IL on y-axis.
8. From the value of no-load voltage (VNL), the % regulation is to be calculated from the
theoretical calculations given below.

INPUT AND OUTPUT WAVEFORMS:

THEORETICAL CALCULATIONS FOR RIPPLE FACTOR & % REGULATION:

(a) WITHOUT FILTER:

For a Full-Wave Rectifier,

Vrms=Vm/√2
Vdc=2Vm/П
Therefore, Ripple factor Γ=√ (Vrms/ Vdc )2 -1 = 0.482
% regulation = [(VNL-VFL)/VFL]*100

(b) WITH FILTER:

 Ripple factor for a Full-Wave Rectifier is Γ=1/ (2√3 fRC).
Where f =50Hz
C =100μF
R= (0-10) KΩ
Therefore, for 1KΩ, Ripple factor, Γ = 0.0577
% regulation = [(VNL-VFL)/VFL]*100

OBSERVATIONS:
(a) WITH OUT FILTER:
VNL =______V

Load Vac(v) Vdc(v) Γ= Vac/ Vdc

[Link] Resistance
(KΩ)

(a) WITH FILTER:

VNL =______V

Load Vac(v) Vdc(v) Γ= Vac/ Vdc

[Link] Resistance
(KΩ)

PRECAUTIONS:
1. The primary and secondary sides of the transformer should be carefully identified.
2. The polarities of the diode should be carefully identified.
3. While determining the % regulation, first Full load should be applied and then it should be
decremented in steps.

RESULT:
The Ripple factor and the % regulation for the Full-Wave Rectifier with and without filters are
calculated.
1. The Ripple factor of Full-Wave Rectifier without filter is _____________________
2. The Ripple factor of Full-Wave Rectifier with filter is _____________________
3. The % Regulation of Full-Wave Rectifier without filter is _____________________
4. The % Regulation of Full-Wave Rectifier with filter is _____________________

VIVA QUESTIONS:
1. What is the PIV of Half wave rectifier?
2. What is the efficiency of half wave rectifier?
3. What is a rectifier?
4. What is the difference between the half wave rectifier and full wave Rectifier?
5. What is the output frequency of Bridge Rectifier?
6. What are the ripples?
7. What is the function of a filter?
8. What is TUF?
9. What is the average value of output voltage for a HWR?
10. What is the peak factor?

Expt. No:4 BJT CHARACTERISTICS

(CE CONFIGURATION)
AIM: To draw the input and output characteristics of transistor connected in CE
Configuration

APPARATUS:

[Link] Name of the Apparatus Range Quantity

1 BJT Kit 1
2 Digital Voltmeter (0-20)V 1
3 Digital Ammeter (0-20)mA 1
4 Digital Multimeter 1
5 Connecting wires As required

THEORY:
A transistor is a three terminal device. The terminals are emitter, base, collector. In common
emitter configuration, input voltage is applied between base and emitter terminals and output is taken
across the collector and emitter terminals. Therefore, the emitter terminal is common to both input
and output. The input characteristics resemble that of a forward biased diode curve. This is expected
since the Base-Emitter junction of the transistor is forward biased. As compared to CB arrangement
IB increases less rapidly with VBE. Therefore, input resistance of CE circuit is higher than that of CB
circuit.

The output characteristics are drawn between Ic and VCE at constant IB. the collector current
varies with VCE unto few volts only. After this the collector current becomes almost constant, and
independent of VCE. The value of VCE up to which the collector current changes with V CE is known
as Knee voltage. The transistor always operated in the region above Knee voltage, IC is always
constant and is approximately equal to IB. The current amplification factor of CE configuration is
given by β = ΔIC/ΔIB

CIRCUIT DIAGRAM:
PROCEDURE:

(i) INPUT CHARACTERSTICS:

1. Connect the circuit as per the circuit diagram.

2. For plotting the input characteristics the output voltage VCE is kept constant at 1V and
for different values of VBE, note down the values of IB.
3. Repeat the above step by keeping VCE at 2V and 3V.
4. Tabulate all the readings.
5. Plot the graph between VBE on x-axis and IB on y-axis for constant VCE.

(ii) OUTPUT CHARACTERSTICS:

1. Connect the circuit as per the circuit diagram.

2. For plotting the output characteristics the input current IB is kept constant at 50μA and for
different values of VCE, note down the values of IC.
3. Repeat the above step by keeping IB at 75μA and 100μA.
4. Tabulate the all the readings.
5. Plot the graph between VCE on x-axis and IC on y-axis for constant IB.

OBSERVATIONS:
 (i) INPUT CHARACTERISTICS:

[Link] VCE=0V VCE=1V

VBE (V) IB (μA) VBE(V) IB (μA)

(ii) OUTPUT CHARACTERISTICS:

[Link] IB= 50 μA IB= 75 μA

VCE(V) IC(mA) VCE(V) IC (mA)

MODEL GRAPH:
(i) INPUT CHARACTERISTICS:
(ii) OUTPUT CHARACTERISTICS:

PRECAUTIONS:

1. While doing the experiment do not exceed the ratings of the transistor. This may lead
to damage the transistor.
2. Connect voltmeter and Ammeter in correct polarities as shown in the circuit diagram.
3. Do not switch ON the power supply unless you have checked the circuit connections
as per the circuit diagram.
4. Make sure while selecting the emitter, base and collector terminals of the transistor.

CALCULATIONS:

1. Input resistance: To obtain input resistance find ΔVBE and ΔIB at constant VCE on one
of the input characteristics. Then
Ri = ΔVBE / ΔIB (VCE constant)
2. Output resistance: To obtain output resistance, find ΔIC and ΔVCE at constant IB.
Ro = ΔVCE / ΔIC (IB constant)
3. The current amplification factor of CE configuration is given by
β = ΔIC/ΔIB

RESULT: The input and output characteristics of a transistor in CE configuration are drawn.
The Input (Ri) and Output resistances (Ro) and  of a given transistor are calculated.
1. The Input resistance (Ri) of a given Transistor is______________
2. The Output resistance (Ro) of a given Transistor is____________
3. The Current amplification factor is_________________________

VIVA QUESTIONS:
1. What is the range of  for the transistor?
2. What are the input and output impedances of CE configuration?
3. Identify various regions in the output characteristics?
4. What is the relation between and ?
5. Define current gain in CE configuration?
6. What is the phase relation between input and output?
7. Draw diagram of CE configuration for PNP transistor?
8. What is the power gain of CE configuration?
9. What are the applications of CE configuration?

(CB CONFIGURATION)
AIM: 1. To draw the input and output characteristics of transistor connected in CB
Configuration

APPARATUS:

[Link] Name of the Apparatus Range Quantity

1 Transistor BC 107 1
2 Resistors (1K ) 2
3 Bread board 1
4 Dual DC Regulated Power (0 – 30 V) 1
supply
5 Digital Ammeters ( 0 – 200 mA) 2
6 Digital Voltmeter (0-20V) 2
7 Connecting wires (Single
Strand)

CIRCUIT DIAGRAM:

PROCEDURE:

(i) INPUT CHARACTERSTICS:

 1. Connect the circuit as shown in the circuit diagram.
2. Keep output voltage VCB = 0V by varying VCC.
3. Varying VEE gradually, note down emitter current IE and emitter-base voltage(VEE).
4. Step size is not fixed because of nonlinear curve. Initially vary V EE in steps of
0.1 [Link] the current starts increasing vary VEE in steps of 1V up to 12V.
5. Repeat above procedure (step 3) for VCB = 4V.

(ii) OUTPUT CHARACTERISTICS:

1. Connect the circuit as shown in the circuit diagram.

2. Keep emitter current IE = 5mA by varying VEE.
3. Varying VCC gradually in steps of 1V up to 12V and note down collector current
IC andcollector-base voltage (VCB).
4. Repeat above procedure (step 3) for IE = 10mA.

OBSERVATIONS:

(i) INPUT CHARACTERISTICS:

VCB=0V VCB=4V
[Link]
VEB (V) IE (mA) VEB (V) IE (mA)

(ii) OUTPUT CHARACTERISTICS:

 IE (mA)=0mA IE (mA)=10 mA
[Link]
VCB (V) IC (mA) VEB (V) IE (mA)

Expt. No:5 BJT - CE AMPLIFIER

AIM: 1. To obtain the frequency response of the Common Emitter BJT Amplifier.
 2. To Measure the Voltage gain and Bandwidth of CE amplifier.

APPARATUS:

[Link] Name of the Apparatus Range Quantity

1 CE Amplifier Kit 1
2 CRO (0-20)MHz 1
3 Function generator (0-1)MHz 1
4 Connecting wires As required

THEORY:

The CE amplifier provides high gain &wide frequency response. The emitter lead
is common to both input & output circuits and is grounded. The emitter-base circuit is
forward biased. The collector current is controlled by the base current rather than emitter
current. The input signal is applied to base terminal of the transistor and amplifier output
is taken across collector terminal. A very small change in base current produces a much
larger change in collector current. When +ve half-cycle is fed to the input circuit, it
opposes the forward bias of the circuit which causes the collector current to decrease, it
decreases the voltage more –ve. Thus when input cycle varies through a -ve half-cycle,
increases the forward bias of the circuit, which causes the collector current to increases
thus the output signal is common emitter amplifier is in out of phase with the input signal.
An amplified output signal is obtained when this fluctuating collector current flows
through a collector resistor Rc.
The capacitor across the collector resistor Rc will act as a bypass capacitor. This
will improve high frequency response of amplifier.

CIRCUIT DIAGRAM:
PROCEDURE:
1. Connect the circuit as per the circuit diagram.
2. Set Source Voltage Vs = 50mV (say) at 1 KHz frequency, using function generator.
3. Keeping the input voltage constant, vary the frequency from 50Hz to 1MHz in regular
steps and note down the corresponding output voltage.
4. Calculate the Voltage Gain by using the formula
Av = Output voltage (V0) / Input voltage (Vs)
5. Calculate the Voltage Gain in dB by using Voltage Gain A v (dB) = 20 log10 (Vo/Vs).
6. Plot the Graph by taking Voltage gain (dB) on x-axis and frequency (Hz) on y-axis.
7. The Bandwidth of the amplifier is calculated from the graph using the expression,
Bandwidth, BW=f2-f1
Where f1 is lower 3-dB frequency
f2 is upper 3-dB frequency

OBSERVATIONS: Vs = ______ V
 [Link] Input Output Voltage Voltage Gain (dB)
Frequency Voltage (Vo) Gain=Vo/Vs =20 log10 (Vo/Vs)
(Hz) (volts)

MODELWAVE FORMS:

A) INPUT WAVE FORM:

B)OUTPUT WAVEFORM:

FREQUENCY RESPONSE:
PRECAUTIONS:

1. While doing the experiment do not exceed the ratings of the transistor. This may lead
to damage the transistor.
2. Do not switch ON the power supply unless you have checked the circuit connections
as per the circuit diagram.
3. Make sure while selecting the emitter, base and collector terminals of the transistor.

RESULT: The Voltage gain and Bandwidth of CE amplifier is measured and the
frequency response of the CE Amplifier is obtained.
1. The Voltage gain of CE Amplifier is ____________________.
2. The Bandwidth of CE Amplifier is ______________________.
VIVA QUESTIONS:
1. What is phase difference between input and output waveforms of CE amplifier?
2. What type of biasing is used in the given circuit?
3. If the given transistor is replaced by a p-n-p, can we get output or not?
4. What is effect of emitter-bypass capacitor on frequency response?
5. What is the effect of coupling capacitor?
6. What is region of the transistor so that it is operated as an amplifier?
7. How does transistor acts as an amplifier?
8. Draw the h-parameter model of CE amplifier?
9. What type of transistor configuration is used in intermediate stages of a multistage
amplifier?

[Link] 7 VERIFICATION OF TRUTH TABLE OF LOGIC GATES

AIM: 1. Study of logic gates using IC’s & discrete components.

APPARATUS: 1. Logic gates (IC) trainer kit.

[Link] patch chords.

THEORY:Logic gates are electronic circuits which perform logical functions on one or more
inputs to produce one output. There are seven logic gates. When all the input combinations of a
logic gate are written in a series and their corresponding outputs written along them, then this
input/ output combination is called Truth Table. Various gates and their working is explained
here.

I. Verifying the logic gates using IC’S

AND Gate

AND gate produces an output as 1, when all its inputs are 1; otherwise the output is 0. This gate
can have minimum 2 inputs but output is always one. Its output is 0 when any input is 0.

IC 7408

OR Gate
OR gate produces an output as 1, when any or all its inputs are 1; otherwise the output is 0. This
gate can have minimum 2 inputs but output is always one. Its output is 0 when all input are 0.

IC 7432

NOT Gate

NOT gate produces the complement of its input. This gate is also called an INVERTER. It
always has one input and one output. Its output is 0 when input is 1 and output is 1 when input is
0.

IC 7404

NAND Gate
NAND gate is actually a series of AND gate with NOT gate. If we connect the output of an
AND gate to the input of a NOT gate, this combination will work as NOT-AND or NAND gate.
Its output is 1 when any or all inputs are 0, otherwise output is 1.

IC 7400

NOR Gate

NOR gate is actually a series of OR gate with NOT gate. If we connect the output of an OR gate
to the input of a NOT gate, this combination will work as NOT-OR or NOR gate. Its output is 0
when any or all inputs are 1, otherwise output is 1.

IC 7402

Exclusive OR (X-OR) Gate

X-OR gate produces an output as 1, when number of 1’s at its inputs is odd, otherwise output is
0. It has two inputs and one output.

IC 7486

Exclusive NOR (X-NOR) Gate

X-NOR gate produces an output as 1, when number of 1’s at its inputs is not odd, otherwise
output is 0. It has two inputs and one output.

PROCEDURE:
1. Connect the trainer kit to ac power supply.
2. Connect the inputs of any one logic gate to the logic sources and its output to the logic
indicator.
3. Apply various input combinations and observe output for each one.
4. Verify the truth table for each input/ output combination.
5. Repeat the process for all other logic gates.
Switch off the power supply

RESULT:

VIVA QUESTIONS:

1. Why NAND & NOR gates are called universalgates?

2. Realize the EX – OR gates using minimum number of NANDgates.
3. Give the truth table for EX-NOR and realize using NANDgates?

[Link] 8 VERIFICATION OF TRUTH TABLES OF S-R, J-K& D FLIP FLOPS

AIM:To verify the truth table of SR latch ,JK flipflop ,JK master slave flipflop,T-
flipflop and D- flipflop.

APPARATUS:
1. IC74LS00
2. IC74LS10
3. IC74LS04.
4. Digital TrainerKit.
THEORY:
RS Flip-Flop:

Consider the logic Symbol for RS flip-flop shown in Fig. Notice that the RS flip-flop has
two inputs, labeled S and R. The two outputs are labeled Q and Q. Note that the outputs are
always opposite, or complementary in the flip-flops.
Fig 5.1 shows the timing diagram for an RS flip-flop. Notice that the output Q goes high
whenever R goes low; and the output Q goes LOW whenever S goes LOW. The logic levels
(0,1) are on the left side of the wave forms. The output Q „holds‟ whenever the both inputs

are high.

Logic symbol for RS Flip-flop

Clocked RS Flip-Flop:
We know that the flip-flops are synchronous bistable devices. The term synchronous
indicates that the output changes its state only at a specified point on a triggering input called
the clock‟ i.e. changes in the output occur in synchronization with the clock.; By adding
gates to the inputs of the basic circuit, the flip-flop can be made to respond to input levels
during the occurrence of a clock pulse. Note that the clock signal is a square wave signal and
the signal prevents the flip- flops from changing the states until the right time occurs. The
clocked RS flip-flop using NAND gates are shown in Fig.5.3

Logic symbol for Clocked RS Flip-flop

 Truth Table For Clocked RS Flip-flop

Modification of clocked RS Flip-Flop into D Flip-Flop

D (Delay) Flip-Flop:

The D (Delay) flip-flop is used for storing the information. It is basically an RS flip-
flop with an inverter in the R input. Fig. 6.3 shows a clocked D flip-flop. NAND gates 1 and
2 from a basic RS flip-flop and gates 3 and 4 modify it into a clocked RS flip-flop. The D
input is to the S input and its complement through gate 5 is applied to [Link]-
flopisoftencalleda„delayflip-flop‟Theword„.delay‟describes what happens to the data or
information at input D. In other words, the data, i.e. 0 or 1 at the input D is delayed by one
clock pulse from getting the output Q.

Logic symbol and Truth Table for D Flip-flop

JK- Flip Flop:
The JK flip-flop has the features of all other flip-flops, and hence it can also be
Considered as Universal flip-flop. This JK flip-flop is a refinement of the RS flip-
flop.
The indeterminate state (when R=S=1) of the RS type is defined in the JK type. In
that condition the state of the output is changed; i.e. the complement of the previous
state is available. In other words, if the previous state of the output Q is 0; it becomes
1; and vice versa. This can be written as Qn+1 = complement {Qn}.
The logic diagram of a clocked JK flip-flop is shown in Fig.6.5. Inputs J and K
behave like inputs S and R to set and reset the flip-flop. Note that in a JK flip-flop, the
letter j is for set and the letter K is for reset.
Fig.6.5 shows the logic symbol for JK flip-flop and its truth table is shown in the Table
6.2. Note that the RS flip-flop is converted into JK flip-flop by making S= J.Q‟ and
R = K‟.Q

Logic Symbol for JK Flip-flop

Truth Table For JK-Flip-flop

T(Toggle) Flip Flop:

The single input version of the JK flip-flop is (toggle) flip-flop and it is obtained from
a JK flip-flop if both inputs are tied together. The name T comes from the ability of the flip-
flop to “toggle” or change the state. Generally, T flip-flop IC‟ are not available. It can be
realized using JK, SR, or D flip-flop.
Fig 6.7. shows the logic diagram of a clocked T flip-flop; which has only one input referred

to as T-input.

Logic symbol and Truth Table for T Flip-flop

CIRCUIT DIAGRAMS:

PROCEDURE:

1. Connect the circuit diagram as shown in thediagram.

2. Verify the truth table of the SRlatch.
3. Connect the JK flip-flop circuit using 3-input NAND gates and verify the truthtable.
4. Verify the truth table for T and DFlip-flops.
5. Verify the truth table for J-K MASTER-SLAVEFLIP-FLOP.

RESULT:

VIVA QUESTIONS:
1. What is a sequential logic circuit? How is it different from a combinationalsystem?
2. What is a binary? What is aflip-flop?
3. Explain the meaning of set and reset?
4. Explain the need offlip-flop?
5. What basic purpose does all flip-flopsserve?
6. Is it possible to toggle a SR flip-flop?Explain?
7. Explain the meaning of race – around problem? How does it affect
the behavior of a flip-flop?