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Experiment: 01

Aim: Introduction to Digital IC trainer kit & verification of truth table of all the logic gates.

Objective 1: To identify and locate all the digital blocks available on the trainer kit.

Apparatus: Digital IC trainer kit & patch cords.

Theory:

The Digital IC trainer has well-laid out component patch containing all the popular
Digital IC’s. The component is soldered on a PCB, which lies below the patch panel. All the
important pins are brought out on the patch panel for external connection. The philosophy
behind this approach is that the learner or the student needs not to worry about pin numbers,
and thus save time in setting up experiments.

When experiments are carried out using Digital ICs one needs general instruments like
multimeters, pulse generators, and oscilloscope. The details of the Digital IC trainer can be
divided into 29 blocks.

Description of the Various Blocks:

All gates and IC building blocks are clearly marked using standard symbols. The
following table gives details of available chips.

Block 1: Input Switches

Input of the devices can be set to a logic HIGH or LOW with the aid of input switches
in block 1. LED’s light up to indicate a logic HIGH.

Block 2: Logic Output Switches

Ten Nos. of independent output indicator with transistors are provided to observe
the logic.

Block 3: Connecting strips

Four independent connecting strips made up of five 4mm sockets each useful for
interconnecting higher density circuits.

Block 4: 7 segment Display

This block contains the input points for the 7-segment LED display on the panel. The
common anode point is internally to 5V DC.

Block 5: Clock Generator

This block contains IC555 based variable frequency clock generator which can be
used in the various circuit as clock.

Block 6: Manual Pulsar

Pulse can be applied to device during an experiment by means of pulsar switches.
 Page |2

Block 7: NAND Gate

It contains four 2 input NAND gates with all input and output pins brought
out on the panel.

Block 9: Breadboard
This consists of terminal strips breadboard (with 640 tie points) with a matrix
of 128 terminal for components and interconnection and contains 5
electrically connected tie points spaced on a continuous 0.1” matrix to
accept any components with 0.1 lead spacing.

Block 8 to 17, 19 to 23 and

25 to 29: This block
contains IC chips.

Block 18: Power supply

This block provides 5V, 1A output for additional usage in experiments. One
can use these supply to power the IC’s connected on the Breadboard.

Block 24: Power ON

This block housed the mains power ON switch with Neon indicator.
 Page |3

Table 1 - List of Popular Digital TTL ICs

Sr. No. IC Number IC Identification

1 IC 7400 Quad 2-input NAND Gate
2 IC 7440 Dual 4-input NAND Buffer

3 IC 7425 Dual 4-input NOR Gate with Strobe

4 IC 7408 QUAD 2-Input AND GATES

5 IC 7402 Quad 2-input NOR Gate
6 IC 7432 Quad 2-input OR Gate
7 IC 7404 NOT Gate IC
8 IC 74151 8-input Multiplexer with 8-input&2 output
9 IC 7476 Dual JK Flip-Flop
10 IC 7495 4-bit Parallel-access Shift Register
11 IC 7447 BCD to 7-segment Decoder/Driver (Open Collector)
12 IC 7483 4-bit parallel Adder
13 IC 7485 4-bit Magnitude Comparator
14 IC 74121 Monostable Multivibrator
15 IC 7486 Quad 2-input XOR Gate
16 IC 74138 3 to 8 line decoder
17 IC 74194 4-bit Bi-directional Universal Shift Register
18 IC 74193 4-bit Binary Counter
19 IC 7490 Basically a MOD-19 Decade Counter
 Page |4

Tutorial - 2

Objective 2: To verify the Truth table of all the Logic Gates

using Logisim Simulator.
Apparatus:
 Logisim Simulator. (can be taken from
[Link]

Theory:
AND Gate:
An AND gate has two or more but only one output. The output assumes the
logic 1 state, only and only when each one of its inputs is at logic 1 state. The
output assumes the logic 0 state even if one of its inputs is at logic 0 state.
The AND gate may, therefore, be defined as a device whose output is 1, if
and only if all its inputs are 1. Hence the AND gate is also called all or
nothing gate.
Logic symbol: Truth table:

Inputs Output
2-input AND Gate is
A B X
0 0 0
0 1 0
1 0 0

1 1 1
 Page |5

OR Gate:
An OR gate may have two or more inputs but only one output. The output
assumes the logic 1 state, even if one of its inputs is in logic 1 state. Its
output assumes the logic 0 state, only when each one of its inputs is in logic
0 state. An OR gate may, therefore, be defined as a device whose output is
1, even if one of its input is 1. Hence an OR gate is also called an any or
all gate.
Logic symbol: Truth table:

Inputs Output
A B X
0 0 0

0 1 0
1 0 0
2 input OR Gate 1 1 1
 Page |6

NOT Gate:
A NOT gate, also called an inverter, has only one input and, only one
output. It is a device whose output is always the complement of its input.
That is, the output of a NOT gate assumes the logic 1 state when its input
is in logic 0 state and assumes the logic 0 state when its input is in logic 1
state.

Logic symbol: Truth table:

Input Output
A X
0 1
1 0
NOT gate
 Page |7

NAND Gate:
NAND means NOT AND, i.e. the AND output is NOTed. So, a NAND gate is a
combination of an AND gate and a NOT gate. In fact NAND is a contraction of
the word NOT-AND. The expression for the output of the NAND gate can,
therefore, be written
as X  ABC.... The output is logic 0 level, only when each of the inputs
assumes a
logic 1 level. For any other combination of inputs, the output is
logic 1 level.

Logic symbol: Truth table:

Outpu
Inputs
t
A B X
0 0 1
0 1 1
1 0 1
2 input NAND Gate 1 1 0
 Page |8

NOR Gate:
NOR means NOT OR, i.e. the OR output is NOTed. So, a NOR gate is a
combination of an OR gate and a NOT gate. In fact NOR is a contraction of
the word NOT-OR. The expression for the output of the NOR gate is,
X  A  B  C The output is logic 1 level, only when each one of its inputs assumes a
logic 0 level. For any other combination of inputs, the output is a logic 0 level.

Logic symbol: Truth table:

Inputs Output
A B X
0 0 1
0 1 0
1 0 0
2 input NOR Gate 1 1 0
 Page |9

X-OR Gate:
An X-OR(Exclusive OR) gate is a two input, one output logic circuit, whose
output assumes a logic 1 state when one and only one of its two inputs
assumes a logic 1 state. Under the conditions when both the inputs assume
the logic 0 state, or when both the inputs assume the logic 1 state, the
output assumes a logic 0 state. Since X- OR gate produces an output 1 only
when the inputs are not equal, it is called an anti- coincidence gate or
inequality detector. The output of the X-OR gate is the modulo-2 sum of
the two inputs.
Whenever the inputs have an odd number of one’s the output is one. Thus
the Exclusive-OR us an odd function.
It can be used as an inverter by connecting one of the two input terminals
to logic 1 and feeding the input sequence to be inverted to the other
terminal.
Logic symbol: Truth table:

Inputs Output
A B X
0 0 0
0 1 1
1 0 1
2 input X-OR Gate 1 1 0
 P a g e | 10

X- NOR Gate:
The XNOR gate (sometimes XORN'T, ENOR, EXNOR oyr NXOR and pronounced
as Exclusive NOR) is a digital logic gate whose function is the logical complement of the
exclusive OR (XOR) gate.
A high output (1) results if both of the inputs to the gate are the same. If one but not
both inputs are high (1), a low output (0) results.

Logic symbol: Truth table:

Inputs Output
A B X
0 0 1
0 1 0
1 0 0
2 input X-NOR Gate 1 1 1

Output Snap from Logisim Simulator:

-------------------------------------------------

- -XXXX
 P a g e | 11

Experiment: 03

Aim: Implementation of basic gates using Universal gates & simplification of given
Boolean function.

Objective 1: To verify the function of NAND gate and NOR gate as a Universal gate.

Apparatus:
 Logisim Simulator.

Theory:
AND, OR, and NOT (Invert) gates are the basic building blocks of a digital computer. They are
called the basic gates. Any digital circuit of any complexity can be built using only these three
gates. A universal gate is a gate which alone can be used to build any logic circuit. With the
help of NAND and NOR gate we can perform the functions of all the three basic gates (AND,
OR, and NOT). AOI logic can be converted to NAND logic or NOR logic. Hence, NAND and NOR
gates are called as universal gates.

NAND gate as a Universal gate:-

The diagrams given below show the realization of AND, OR, and NOT functions using NAND
gates.
 Realization of NOT function using only NAND gate:

TRUTH TABLE OBSERVATION TABLE

Input Output Input Output
A X A X
0 1 0 1
1 0 1 0
 P a g e | 12

 Realization of AND function using only NAND gate:

TRUTH TABLE OBSERVATION TABLE

Inputs Output Inputs Output
A B X A B X
0 0 0 0 0 0
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 1 1 1
 P a g e | 13

 Realization of OR function using only the NAND gate:

TRUTH TABLE OBSERVATION TABLE

Inputs Output Inputs Output
A B X A B X
0 0 0 0 0 0
0 1 1 0 1 1
1 0 1 1 0 1
1 1 1 1 1 1
 P a g e | 14

NOR gate as a Universal gate:-

The diagrams given below show the realization of AND, OR, and NOT functions
using NOR gates.

 Realization of NOT function using only the NOR gate:

TRUTH TABLE OBSERVATION TABLE

Input Output Inputs Output
A X A X
0 1 0 1
1 0 1 0

 Realization of OR function using only the NOR gate:

TRUTH TABLE OBSERVATION TABLE

Inputs Output Inputs Output
A B X A B X
0 0 0 0 0 0
0 1 1 0 1 1
1 0 1 1 0 1
1 1 1 1 1 1
 P a g e | 15

Realization of AND function using only the NOR gate

TRUTH TABLE OBSERVATION TABLE

Inputs Output Inputs Output
A B X A B X
0 0 0 0 0 0
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 1 1 1

-XXXX
 P a g e | 16

Experiment: 04

Aim: Identification of logic diagram & Realization of EX-OR gate through universal

gates.

Apparatus: Logisim Simulator.

Theory:
1. Which of the following logic expressions represents the logic diagramshown?

A.

B.

C.

D.

A B A’ B’ AB A’B’ X=AB+A’B’
0 0 1 1 0 1 1
1 0 0 1 0 0 0
0 1 1 0 0 0 0
1 1 0 0 1 0 1

2. DerivetheBooleanexpressionforthefollowingswitchingcirc
uit. Drawthetruthtable.

 Boolean expression for the following switching circuit = (A+B).C

A B C A+B (A+B).C
0 0 0 0 0
0 0 1 1 1
0 1 0 1 0
0 1 1 1 1
1 0 0 1 0
1 0 1 1 1
1 1 0 1 0
1 1 1 1 1
 P a g e | 17

3. Construct EX-OR gate using NAND & NOR gates. Test the circuit using
logisim. Also draw necessary truthtable.

EX-OR gate using NAND gate

A (INPUT) B(INPUT) C D E X (OUTPUT)

0 0 1 1 1 0
1 0 1 0 1 1
0 1 1 1 0 1
1 1 0 1 1 0

E X-OR gate using NOR gate

A (INPUT) B (INPUT) C D E F X (OUTPUT)

0 0 1 1 0 1 0
1 0 0 1 0 0 1
0 1 1 0 0 0 1
1 1 0 0 1 0 0

---xxx---
 P a g e | 18

Tutorial 5
-------------
AIM: Implement the following Boolean functions without & with simplification.
1. F = AB + A(B + C) + B(B + C)
2. F = (A + B)(A + C)
3. F = A′B+BC′+BC+AB′C′
4. F = AB + ABC’D + B’C + ABCD

Example Solution for:

1. F = AB + A(B + C) + B(B + C) = B + AC
Simplification:

F = AB+A(B+C)+B(B+C) Distributive law :

= AB+AB+AC+B+BC B.B = B
= AB+AC+B B+BC =B, Absorption La
= AC+B AB+B =B, Absorption
Law

Logic diagram (with &without simplification using logisim):

THIS TWO CIRCUIT ARE EQUIVALENT.

Output/Truth Table:

A B C AB B+C A(B+C) B(B+C) F(un-simplified) F(Simplified)

0 0 0 0 0 0 0 0 0
0 1 0 0 1 0 1 1 1
1 0 0 0 0 0 0 0 0
1 1 0 1 1 1 1 1 1
0 0 1 0 1 0 0 0 0
0 1 1 0 1 0 1 1 1
1 0 1 0 1 1 0 1 1
1 1 1 1 1 1 1 1 1
 P a g e | 19

Example Solution for:

2. F = (A+B)(A+C) = A+BC
Simplification:

Distributive law :
F = (A+B)(A+C) A.A = A
= A+AC+BA+BC AC+BA = A+BC, distribu ive Law
t
= A+A+BC+BC
= A+BC

Logic diagram (with &without simplification using logisim):

THIS TWO CIRCUIT ARE EQUIVALENT.

Output/Truth Table:

A B C A+B A+C F(un-simplified) F(Simplified)

0 0 0 0 0 0 0
0 1 0 1 0 1 1
1 0 0 0 0 0 0
1 1 0 1 1 1 1
0 0 1 1 0 0 0
0 1 1 1 0 1 1
1 0 1 1 1 1 1
1 1 1 1 1 1 1
 P a g e | 20

Example Solution for:

3. F = A’B+BC’+BC+AB’C’ = B+AB’C’
Simplification:

Distributive law :
F = A’B+BC’+BC+AB’C’ C’+C=1
= B(A’+C’)+BC+AB’C’ A’B+B=B, Absorption Law
= B+(A’+C’+C)+AB’C’
= B(A’+1)+AB’C’
=A’B+B+AB’C’
=B+AB’C’

Logic diagram (with &without simplification using logisim):

THIS TWO CIRCUIT ARE EQUIVALENT.

Output/Truth Table:

A B C A’B BC’ BC AB’C’ F(un-simplified) F(Simplified)

0 0 0 0 0 0 0 0 0
0 1 0 1 1 0 0 1 1
1 0 0 0 0 0 1 0 0
1 1 0 0 1 0 0 1 1
0 0 1 0 0 0 0 0 0
0 1 1 1 0 1 0 1 1
1 0 1 0 0 0 0 1 1
1 1 1 0 0 1 0 1 1
 P a g e | 21

Example Solution for:

3. F = AB+ABC’D+B’C+ABCD = AB+B’C
Simplification:

F=
AB+ABC’D+B’C+ABCD
= AB+B’C+ABD(C’+C) Distributive law :
= AB+B’C+ABD C’+C=1
= AB(1+D)+B’C D+1=1, Identity Law
=AB+B’C

Logic diagram (with &without simplification using logisim):

THIS TWO CIRCUIT ARE EQUIVALENT.

Output/Truth Table:

A B C D AB B’C ABC’D ABCD F(Un-simplified) F(Simplified)

0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0
0 0 1 0 0 1 0 0 1 1
0 0 0 1 0 0 0 0 0 0
1 1 0 0 1 0 0 0 1 1
1 0 1 0 0 1 0 0 1 1
1 0 0 1 0 0 0 0 0 0
0 1 1 0 0 0 0 0 0 0
0 1 0 1 0 0 0 0 0 0
0 0 1 1 0 1 0 0 1 1
1 1 1 0 1 0 0 0 1 1
1 1 0 1 1 0 1 0 1 1
1 0 1 1 0 1 0 0 1 1
0 1 1 1 0 0 0 0 0 0
1 1 1 1 1 0 0 1 1 1
P a g e | 22

22
 P a g e | 23

TUTORIAL :6
Aim: To implement half adder, full adder, half Subtractor and full Subtractor using logic gates.

Apparatus:

Theory:
The binary addition and subtraction are very basic operations in the digital computer. To
perform addition the adder circuit is used and for subtraction the subtractor circuit is used.
There are two types of Adders according to the number of inputs:
1. HalfAdder
2. FullAdder
Also, there are two types of Subtractor according to the number of inputs:
1. HalfSubtractor
2. FullSubtractor

ADDERS
HALF ADDER:
A Half-Adder is a combinational circuit with two binary inputs (augend and addend bits) and
two binary outputs (Sum and Carry bits). It adds the two inputs (A and B) an produces the
sum (S) and the carry (C) bits. It is an arithmetic circuit used to perform the arithmetic
operation of addition of two single bit words.

Block Diagram: Truthtable:

Inputs Outputs
A
HALF A B S C
ADDER
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Logic Equations:

C =AB
 P a g e | 24

Logic Diagram in Logisim:

FULLADDER:
The full-Adder is a combinational circuit that adds two bits and a carry and outputs a sum bit
and a carry bit. The full-adder adds the bits A and B and the carry from the previous column
called the carry-in Cin and outputs the sum bit S and the carry bit called the carry-out Cout. The
variable S gives the value of the least significant bit of sum. The variable C out gives the
outputcarry.

BlockDiagram: Truthtable:

A S
FULL Inputs Outputs
ADDER
B A B Cin S Cout
Cout
Cin 0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
Logic equations:
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
 P a g e | 25

Logic Diagram in Logisim:

----------------------------------- SUBTRACTORS ----------------------------------

HALF SUBTRACTOR:
Half Subtractor Subtracts a single-bit binary value B from another A (i.e. A -B)
and produces a difference bit D and borrow out bit Bo. This operation is called
half subtraction and the circuit to realize it is called a half subtractor.

The Boolean functions describing the half- Subtractor are:

Bo = A’ B
Truthtable:

Inputs Outputs
A B D Bo
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
 P a g e | 26

Logic Diagramin in Logisim:

FULL SUBTRACTOR:
Subtracting two single-bit binary values, B, Cin from a single-bit value A produces a
difference bit D and a borrow out bit Bo. This is called full subtraction. The Boolean
functions describing the full-subtractorare:

Truthtable:

Inputs Outputs
A B Cin D Bo
0 0 0 0 0
0 0 1 1 0
0 1 0 1 1
0 1 1 0 1
1 0 0 1 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 0
 P a g e | 27

Logic Diagramin in Logisim:

---xxx---
P a g e | 28
 P a g e | 29

EXPERIMENT : 07

Aim: To design and set up various logic circuits using 4-bit binary parallel adder IC 7483:

i) A 4-Bit Binary ParallelAdder ii)

A 4-Bit Binary ParallelSubtractor
iii) A 4-Bit Binary
ParallelAdder/Subtractor

Apparatus: Digital IC trainer kit, patchcords, Logisim.

Theory:
The Full adder can add single-digit binary numbers and carries. The largest sum
that can be obtained using a full adder is (11)2. Parallel adders can add multiple-
digit numbers. If full adders are placed in parallel, we can add two- or four-digit
numbers or any other size desired. Figure below uses STANDARD SYMBOLS to
show a parallel adder capable of adding two, two-digit binary numbers. The
addend would be on A inputs, and the augend on the B inputs. For this
explanation we will assume there is no input to C0 (carry from a previous circuit)

Figure 3.1: 4-Bit Binary Parallel Adder (IC 7483 – internal architecture)

The 74LS83A is a high-speed 4-Bit binary Full Adder with internal carry look-
ahead. It accepts two 4-bit binary words (A1–A4, B1–B4) and a Carry Input
(C0). It generates the binary Sum outputs (S1–S4) and the Carry Output (C4)
from the most significant bit. The LS83A operates with either active HIGH or
active LOW operands (positive or negative logic). The 74LS283 is
recommended for new designs since it is identical in function with this device
and features standard corner powerpins.

Procedure (Binary Addition):-

• ConnectonesetofinputsfromA1 toA4 pinsand

theothersetfromB1 toB4,ontheIC 7483.
• Connect the pins from S1 to S4 & C4 to output terminals and observethe
• Ground C0. Switch on thekit.
• Apply the inputs to the adder as shown in the truth tables givenbelow.
 P a g e | 30

• Check the outputs and note them down in the table for the
correspondinginputs.
• Verify that the outputs match with the expectedresults.

74LS

Schematicdi agram:

Pindiagr am:
ObservationTablefortheAdd
er
Cin Input A (Augend) Input B (Addend) Output S (Sum) Cout
C0 A3 A2 A1 A0 B3 B2 B1 B0 S S S S0 C3
3 2 1
0 0 0 1 1 1 0 1 0 1 1 0 1 0
0 0 0 0 1 1 1 0 0 1 1 0 1 0

Example: 8 + 3 = 11 (1011)
 8 is realized as A3 A2
A 1A0 =1000
 3 is realized as B3 B2
B 1 B0 =0011

0
 P a g e | 31

Procedure to connect 4-bit parallel full-adder circuit in Logisim Simulator

1. Take 1-bit full adder from menu.

2. Take such four full adders and connect i/p A and B to all four adders.
3. Connect four LEDs to all four adders as o/p.
4. Give the input at carry in of the first full adder. Also connect one LED as
o/p at carry out of the fourth full adder. Then connect all full adders as
shown in figure.
5. Then take different values of all the inputs and get the sum of two
binary numbers.

(ii) A 4-Bit Binary ParallelSubtractor

Theory:

Subtraction is carried out by adding 2’s complement of the subtrahend to minuend.

Example: 8 – 3 = 5 (0101)
 8 is realized as A 3 A2A1A0 =1000
 3 is realized as B 3 B2B1 B0 =0011
 Output of NOT gate is 1’s complementof3=1100
 Adder output is realized as S4 S3S2S1 = 0101 (After adding Cin = 1 and neglecting
MSB1)

Procedure (Binary Subtraction):-

• ConnectonesetofinputsfromA1toA4
pinsandtheothersetofinputsfromB1toB4 to the input of NOT gates as
shown in figure givenabove.
• Connect the pins from S1 to S4 & C4 to outputterminals.
• Connect C0 to Vcc. Make other connections as per above logic
diagram. Switch onthe kit.
• Apply the inputs to the subtractor as shown in the truth tables givenbelow.
 P a g e | 32

• Check the outputs and note them down in the table for the
correspondinginputs.
• Verify that the outputs match with the expectedresults.

Observation Table for the Subtractor

Output D
Cin Input A (subtrahend) Input B (minuend) Bout
(Difference)
C0 A4 A3 A2 A1 B4 B3 B2 B1 D4 D3 D2 D1 B4
1 1 1 0 1 1 0 1 1 1 0 0 0 1
1 1 1 1 0 0 1 1 1 1 0 1 1 1

Procedure to connect 4-bit parallel full-subtractor circuit in Logisim Simulator

1. Take 1-bit full adder from menu.

2. Take such four full adders and connect input A and B to all four
adders. Here,connect NOT gate before giving inpit B to the
adder.

3. Connect four LEDs to all four full adders as output.

4. Give the input at carry in of the first full adder. Also connect one
LED as output at carry out of the fourth full adder. Then connect all
full adders as shown in figure.
5. Then take different values of all the inputs and get the subtraction
of two binary numbers.
 P a g e | 33

(iii) A 4-Bit Binary ParallelAdder/Subtractor

Theory:

It can be seen that the 7483 IC receives the first operand A

directly and other It can be seen that the 7483 IC receives the first
operand A directly and other operand B through XOR gates. Each
XOR gates receives mode input M and one of the inputs of B. When
M=0 the circuit is an adder and when M=1 it becomes subtractor as
explainedbelow.

When M = 0, the initial carry C0 = 0, one of the input of each

XOR gates is 0 and each X-OR gate passes the other input to its
output (because X (X-OR) 0 = X). Thus the second input to 7483 IC
is B and the circuit performs normal addition as follows:

When M = 1, the initial carry C0 = 1, one of the input of each X-

OR gates is 1 and each X-OR gate produces the complement of its other
input (because X(X-OR) 1 = X’). Thus the second input to 7483 IC is 1’s
complement of B. This 1’s complement plus C0 (1) becomes 2’s
complement of B. Thus circuit adds 2’s complement of B to
A(i.e.subtractionby2’scom plement).
 P a g e | 34

Procedure:
• Make connections as per above logic diagram using X-OR gates
and 7483IC.
• Connect M to either manual pulser or toggleswitch.
• Switch on the trainerkit.
• In order to Perform Addition, keep M = 0, supply required inputs
and recordyour results in table givenbelow.
• In order to implement the IC 7483 as a subtractor, keepM=1.
• Apply the B input through XOR gates (essentially taking complement ofB).
• Check the outputs and note them down in the table for the
the
expectedresults.

Observation Table for the Adder/Subtractor

M = 0 (ADDER) M= 1 (SUBTRACTOR)

Inputs Outputs Inputs Outputs

A4 A3 A2 B4 B3 B2 C4S4 S3 S2 A4 A3 A2 A4 A3 A2 C4S4 S3 S2
A1 B1 S1 A1 A1 S1
1101 1011 11000 1101 1011 10010
1110 0111 10101 1101 0111 10111

Procedure to connect 4-bit parallel full adder/subtractor circuit in Logisim Simulator

1. Take 1-bit full adder from menu.

2. Take such four full adders and connect inpit A and EX-OR gate which
having B as input.
3. Connect four LEDs to all four full adders as output.
4. Give the input at carry in the first full adder. Also connect one LED as
output at carry out of the fourth full adder. Then connect all full adders
as shown in figure. Here, carry in is also one input of all the EX-OR
gates.
5. Then take different values of all the input and get the sum and
subtraction of two binary numbers by changing mode value(Co= 0 is
adder mode and Co=1 is subtractor mode).
 P a g e | 35

 Conclusion:
 By using this kind of circuit we can easily add and subtract binary
numbers and get the answer very quickly
 They are also used in microcontrollers for arithmetic addition, PC(program counter)
and timers
 P a g e | 36

Tutorial : 8
AIM:
A. To implement/design 4-bit binary to Gray codeconverter
B. To implement/design 4-bit Gray to binary code converter usingLogisim.

Theory:
These conversion methods strongly follow the operation of Exclusive-OR gate.

[Link] following steps let you know how to achieve Binary Code to Gray Code conversi n:

1. The left most significant bit of a given Gray code number is same as the mostleft
significant bit of thebinarynumber.
2. To obtain the successive binary bits to produce the equivalent binary number for the
givenGraycodenumber,addthefirstbitofGraycodetothesecondoneandwritedown
theresultnexttothefirstbit,addthesecondGraycodebittothirdoneandwritedown the result
andsoonnextto thesecondbitandrepeatthesameoperationuntilthelastbit.

These conversion techniques are used in digital computation to represent position of the
rotating disk. When it comes to
conversion as you online calculation, this converter
required. assists you to perform the

CIRCUITDIAGRAM: TruthTable

Assignment to the students:

Similarly perform B. 4-bit gray to binary conversion.

For your reference:

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CIRCUITDIAGRAM: Truth Table:

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Tutorial : 9
AIM:
A. To implement/design a SR Flip Flop using cross-coupled NAND gates
&verify its functionality with SR Flip Flop Device.

Theory:
A basic NAND gate SR flip-flop circuit provides feedback from both of its outputs back to its
opposinginputsandiscommonlyusedinmemorycircuitstostoreasingledata [Link] flip-flop
actually has three inputs, Set, Reset and its current output Q relating to its current state
[Link]“Flip-flop”relatestotheactualoperationofthedevice,asitcanbe“flipped” into one
logic Set state or “flopped” back into the opposing logic Resetstate.

Conclusion:

A basic NAND gate SR flip-flop circuit provides feedback from both of its
output back to its opposing inputs and is commonly used in memory circuits to store a
single data bit.
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Tutorial 10
AIM: To study/implement various Registers using Logisim.

• Implement 4-bit Serial In Serial Out Shift Register using D FlipFlop

• Implement4-bitSerialInParallelOutShiftRegisterusingDFlipFlop
Implement 4-bit Parallel In Serial Out Shift Register using D FlipFlop
• Implement 4-bit Parallel In Parallel Out Shift Register using D Flip Flop

Solution:

• Implement 4-bit Serial In Serial Out Shift Register using D FlipFlop

• Implement 4-bit Serial In Parallel Out Shift Register using D FlipFlop

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• Implement 4-bit Parallel In Serial Out Shift Register using D Flip Flop

• Implement 4-bit Parallel In Parallel Out Shift Register using D Flip Flop
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Tutorial 11
AIM: To study about how to design acounter

1. To design a ring counter using SISO shift register.

Ring Counter:

---xxx---
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Tutorial 12

1. To design a 2-bit ripple up-counter using negative edge triggeredFF.

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2. To design a 2-bit ripple down-counter using negative edge triggeredFF.

2-bit ripple down-counter using negative edge triggered FF

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3. To design a 2-bit ripple up-counter using positive edge triggeredFF.

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4. To design a 2-bit ripple down-counter using positive edge triggeredFF.

Sign of the staff in

charge
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Tutorial 13
AIM: To study about how to design acounter

1. To design modulo-6 asynchronous counter.

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Sign of the staff in

charge