ASIC Design

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MODULE 1:
Introduction to ASICs:
Full custom, Semi-custom and Programmable ASICs, ASIC Design flow, ASIC cell libraries.
CMOS Logic: Data path Logic Cells: Data Path Elements, Adders: Carry skip, Carry bypass, Carry save,
Carry select, Conditional sum, Multiplier (Booth encoding), Data path Operators, I/O cells, Cell Compilers.

Text Book 1 : Michael John Sebastian Smith, Application - Specific Integrated Circuits, Addison-Wesley
Professional, 2005.

Introduction:

 An ASIC means application-specific integrated circuit.

 The physical size of a silicon die varies from a few millimeter square to one inch square in area. But
size of an IC is not specified in terms of area but instead we often measure the size of an IC by the number
of logic gates or number of transistors that the IC contains. As a unit of measure gate equivalent corresponds
to a two-input NAND gate. A gate equivalent is a NAND gate F = A • B (IBM uses a NOR gate), or four
transistors. For example, a 100K-gate IC contains the equivalent of 100,000 two input NAND gate.

 History of integration:
 small-scale integration (SSI, ~10 gates per chip, 60’s)
 Medium scale integration (MSI, ~100–1000 gates per chip, 70’s)
 large-scale integration (LSI, ~1000–10,000 gates per chip, 80’s)
 very large-scale integration (VLSI, ~10,000–100,000 gates per chip, 90’s)
 ultra large scale integration (ULSI, ~1M–10M gates per chip)
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 History of technology: bipolar technology and transistor–transistor logic (TTL) preceded metal oxide-
silicon (MOS) technology because it was difficult to make metal-gate n-channel MOS (nMOS or NMOS);
the introduction of complementary MOS (CMOS) greatly reduced the power. The feature size is the
minimum length of the gate or channel make on a chip and is measured in λ or lambda.
Origin of ASICs: the standard parts, initially used to design microelectronic systems, were gradually
replaced with a combination of glue logic, custom ICs, dynamic random access memory (DRAM) and
static RAM (SRAM)

Wafer: The ICs are made on a thin, circular silicon wafer, with each wafer holding hundred’s of die.
Die: The die is the raw, functional piece of silicon containing the complete electronic circuit for a specific
purpose. It is produced by cutting a large, circular silicon wafer into individual, square or rectangular pieces.
This cannot be used in devices.
IC/Chip: A small, individual rectangular piece of semiconductor material that contains a functional
integrated circuit which is then packaged to become final chip. This packaging provides physical protection
for the die, adds electrical connections to the rest of the circuit board. The IC itself is the complete circuit
etched onto that die, while die is the bare, unpackaged silicon. It means chip/IC is the packaged die

The transistors and wiring are made from many layers. The first half dozen or so layers define the transistors
and the last half dozen or so layers define the metal wires between the transistors.
ICs are made in batches called wafer lots. A wafer lot is a group of silicon wafers that are all processed
together. Usually there are between 5 and 30 wafers in a lot. Each wafer can contain tens or hundreds of
chips depending on the size of the IC and the wafer.
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Types Of ASICs

 Full-Custom ASICs

 Semi-Custom ASICs

 Programmable-ASICs
1. Full-Custom ASICs:

 An engineer designs some or all of the logic cells, circuits or layout specifically for one ASIC.
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 Here, the designer will not use the pretested and pre-characterized cells for all or part of the design.
Because, the existing cell libraries are not fast enough, or logic cells are not small enough or consume too
much power.

Advantages of Full-Custom ASICs:

1. High Performance
2. Full-custom design allows for meticulous optimization of the chip's architecture and layout, resulting in
superior speed, low power consumption and compact size compared to other ASIC types.
3. The ability to optimize the layout at a very granular level leads to smaller chip sizes, which is beneficial for
devices where space is limited.
4. Deep System Integration:
Full-custom ASICs can integrate a wide range of components, including analog and digital circuits, forming a
complete system on a single chip, leading to reduced component count and increased functionality.

Disadvantages of Full-Custom ASICs

1. High Development Costs: Designing a full-custom ASIC involves significant Non-Recurring Engineering
(NRE) costs associated with research, design, prototyping, and testing.
2. Long Design Cycles: The extensive customization and optimization process leads to longer design and
manufacturing times compared to other ASIC types.
3. Limited Flexibility: Full-custom ASICs are difficult and costly to modify after the initial design and
manufacturing, making them unsuitable for applications requiring frequent updates or changes.
4. Increased Complexity: Designing full-custom ASICs requires specialized expertise and sophisticated CAD
tools, increasing the complexity of the development process.
5. Higher Risk: The extensive customization and the need for manual optimization increase the risk of design
errors and potentially costly re-spins.
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Which is the best Technology for ASICs?

 Bipolar technology has historically been used for precision analog functions. The reason is, that
the matching of characteristics between components on the same chip is excellent in case of BJTs
 Suppose we have transistors T1, T2 and T3 on an analog/digital ASIC. All 3 transistors are identical
transistors. Transistor T3 is the same size as T1 and T2 but is located on the other side of the chip from T1
and T2 and has a different orientation.

Observations on Characterization of transistors

 T1 will have virtually identical characteristics to T2 on the same IC. That is, they match very well.
 T3 will match T1 and T2 very well but not as closely as T1 matches T2 on the same IC
 T1, T2 and T3 will match fairly well with transistors T1, T2 and T3 on a different IC on the same
wafer. The matching will depend on how apart the two ICs are on the wafer.
 Transistors on ICs from different wafer lot will not match very well
 Transistors on ICs from different wafer lots will match very poorly
 For many analog designs the close matching of transistors is crucial to circuit operation. Bipolar
technology has historically been more widely used for full custom analog design because of its improved
precision.
 Despite of its poorer analog properties, the use of CMOS technology is for analog functions is
increasing. Two reasons for this is
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CMOS is the most widely available IC technology.

Increased level of integration requirement for mixing analog and digital functions on the same
IC

This has forced designers to find ways to use CMOS technology to implement analog designs

Standard-Cell-Based ASICs

 These ASICs are popularly called as CBIC ASICs. It uses predesigned logic cells known as standard cells.
These ASICs save time, money and reduce risk by using predesigned and pretested logic cells (AND, OR gates,
multiplexers and flip-flops). Which are known as standard characterized standard-cells and library of those
cells is called Standard cell library.

 The standard cell areas in a CBIC are built of rows of standard cells Like a wall built of bricks.
 The standard-cell areas may be used in combination with larger pre-defined cells like microprocessors
and microcontrollers called Megacells. Megacells are also called mega functions, full custom blocks, fixed
blocks, cores, system level macros or functional standard blocks.

 The standard cell area in a CBIC is called flexible blocks. These blocks are built of rows of standard cells- like
a wall built of bricks.
Advantages
 Designers save time and money and reduce risk by using predesigned and pretested logic cells
 Each standard cell can be optimized individually.
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 During the design of the cell library each and every transistor in every standard cell can be chosen to maximize
speed or minimize area

Disadvantages

 expense of designing
 Buying the standard-cell library
 The time needed to fabricate all layers of the ASIC for each new design
Important features of CBIC

 All mask layers are customized-transistors and interconnect

 Custom blocks can be embedded
 Manufacturing lead time is about eight weeks
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Fig: A cell based ASIC die with a flexible and fixed blocks

 Each standard cell in the library is constructed using full-custom design methods, but you can use these
predesigned and pre characterized circuits without having to do any full-custom design yourself. This design
style gives the same performance and flexibility advantages of a full-custom ASIC but reduces design time and
reduces risk.

 Area between the cell bounding box and Cell abutment box is the area of overlap between the bricks
 Power supplies (VDD and VSS) run horizontally inside a standard cell
on a metal layer that lies above the transistor layers.
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 Each different shaded pattern represents a different layer.

 It has a center connectors (A1, B1,Z) that allows the cell to connect with others.
Layout Of CBIC
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Routing Of CBIC
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 Power and ground buses run

 horizontally on metal lines inside the cells.

 A connection that needs to cross over a row of standard cells uses a feedthrough. The term feedthrough can refer either to the piece of metal that is
used to pass a signal through a cell.

 The width of each row of standard cells is adjusted so that they may be aligned using spacer cell
Gate- Array- Based ASICs
 Also known as Masked Gate Array (MGAs)
 The transistors are predefined on the silicon wafer. The predefined pattern of transistors on a gate array is the base array.
 The smallest element that is replicated to make the base array is called base cell
 The costs for all the initial fabrication steps for an MGA are shared for each customer and this reduces the cost of an MGA compared to a
full-custom or standard-cell ASIC design
 There are 3 types of gate-array-based ASICs
1. Channeled gate arrays
2. Channelless gate arrays

3. Structured gate arrays

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1. Channeled Gate array

 In a channeled gate array the space is left between the rows of transistors for wiring

 Only the interconnect is customized

 The interconnect uses predefined spaces between rows of base cells

 Manufacturing lead time is between two days and two week

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2. Channelless gate arrays

 A channelless gate array (channel-free gate array, sea of-gates array, or SOG array) base cell array of base cells (not all shown)

 No Predefined Routing Channels:

There are no dedicated routing areas. Wires are routed directly over the cells, using transistors that are not used for logic.
 Routing Complexity:
Routing can be more complex and time-consuming due to the need to find available paths across the array.

 Density:
Higher logic density because there are no wasted spaces for routing.
Design Flexibility: More flexible for routing, as you can utilize the entire surface area for connections.

 Manufacturing lead time is between two days and two weeks

 It combines some of the features of CBICs and MGAs.
 One of the disadvantages of the MGA is the fixed gate array base cell. This makes the implementation of embedded block (for example, if an
embedded gate array contains an area set aside for a 32-K bit memory but we only need a 16k-bit memory, then we may have to waste half of the
embedded memory function), difficult and inefficient.
 In an embedded gate array we reserve some of the IC area and dedicate it to a specific function. This embedded area either can contain a different
base cell that is more suitable for building memory cells, or it can contain a complete circuit block, such as a microcontroller
 Important features are
 Only the interconnect is customized
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 Custom blocks (the same for each design) can be embedded

 Manufacturing lead time is between two days and two weeks

The key difference between channeled and channelless gate arrays lies in how they handle routing between logic cells. Channeled gate arrays predefine
routing paths, while channelless (or sea-of-gates) arrays do not, instead routing over the top of the gate cells. This fundamental difference impacts density,
flexibility, and design complexity.
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3. Structured gate array

 It is also called as embedded Gate Array
 It combines some of the features of CBICs and MGAs.
 One of the disadvantages of the MGA is the fixed gate array base cell. This makes the implementation of embedded block (for example, if an
embedded gate array contains an area set aside for a 32-K bit memory but we only need a 16k-bit memory, then we may have to waste half of the
embedded memory function), difficult and inefficient.

 In an embedded gate array we reserve some of the IC area and dedicate it to a specific function. This embedded area either can contain a different
base cell that is more suitable for building memory cells, or it can contain a complete circuit block, such as a microcontroller
 Important features are
 Only the interconnect is customized
 Custom blocks (the same for each design) can be embedded
 Manufacturing lead time is between two days and two weeks
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o programmable logic device (PLD)

The most common types of ROM use a

 PLDs may be configured or programmed to metal fuse that can be blown permanently.
 An Electrically programmable ROM or application EPROM uses programmable MOS
 PLDs use different technologies to allow transistors whose characteristics are programming of the device altered by applying a high
voltage.
All PLDs have the following features in common
 No customized mask layers or logic cells
 Fast design turnaround
 A single large block of programmable interconnect
 A matrix of logic macro-cells that usually consist of programmable array logic followed by a flip-flop or latch

 The simplest type of programmable IC is a Read Only Memory (ROM)

 There is another type of ROM that can be placed in any ASIC is Mask Programmable ROM. Which is a regular array of transistors
permanently programmed using custom mask patterns
 By using the programmable devices in a large array of AND and OR gates, a family of flexible and programmable logic device called
Logic arrays were invented. They were popularly known as Programmable Array Logic (PALs). which can also include registers to
store the current state information so that we can use them to make a complete state machine.
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 A logic array is placed as a cell on a custom ASIC, such a programmable device is known as Programmable Array Logic (PALs)

 There is a difference between a PAL and a PLA: A PLA has a programmable AND logic array followed by a programmable OR logic
array. A PAL has a programmable AND plane and in contrast to a PLA, a fixed OR plane is used
 Depending on how the PLD is programmed, we can have an erasable PLD or mask-programmable PLD. The first PALs, PLAs and
PLDs were based on bipolar technology and used programmable fuses or links. CMOS PLDs usually employ floating-gate transistors
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Field Programmable Gate Arrays (FPGAs)

There is a very little difference between FPGA and a PLD: FPGA is usually just larger and more complex than PLD
Essential characteristics of FPGA
None of the mask layers are customized
The core is a regular array of programmable basic logic cells that can implement combinational as well as sequential logic (flip-flops)
 A matrix of programmable interconnect surrounds the core

 basic logic cells programmable basic logic cell

 Programmable I/O cells surround the core

 Design turnaround is few hours

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ASIC Design flow

1. Design entry: Enter the design into an ASIC design system either using hardware description language (HDL) or schematic entry.
2. Logic synthesis: Produces a netlist— logic cells and their connections. Logic synthesis is the automatic process of translating a high-level
behavioral description of a digital circuit, written in a Hardware Description Language (HDL) (like Verilog or VHDL), into an optimized gate-
level netlist. This conversion, performed by software tools called synthesis tools, creates a circuit composed of basic logic gates (like AND, OR,
NOT) connected by wires, allowing for efficient physical implementation and optimization for design constraints such as performance (speed),
power consumption, and chip area.
3. System partitioning: System partitioning in an ASIC is the process of dividing a complex circuit design into smaller, more manageable sub-
circuits or blocks.
4. Pre layout simulation: Pre-layout simulation in ASIC design involves functional and timing verification of a chip's logical design before its
physical layout is finalized. Basically, it is to Check to see if the design functions correctly.
5. Floor planning: Floor planning in an Application-Specific Integrated Circuit (ASIC) is the initial stage of physical design that involves
defining the chip's core dimensions, macro (large fixed block) and I/O pad placement, and standard cell row areas. Its primary goal is to create
a preliminary layout that optimizes power, performance, and area (PPA) by minimizing wire congestion, ensuring efficient power distribution,
and setting constraints for subsequent placement and routing steps.

6. Placement: Decide the location of cells in a block. placement is the critical physical design step where the exact locations for all standard cells,
macro blocks, and other design components are determined on a chip's core area. The goal of this process is to achieve an optimal balance
between performance, power, and area

7. Routing: Make the connections between cells and blocks.

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8. Extraction: Determine the resistance and capacitance of the interconnect. (See next page for Figure)
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ASIC CELL LIBRARIES

1. In first choice, using an ASIC- vendor library, requires to use a set of design tools approved by the ASIC vendor to enter and simulate the design.
Some vendors supply tools that they have developed in-house. An ASIC vendor library is usually a phantom library—the cells are empty boxes, or
phantoms, you hand off your design to the ASIC vendor and they perform phantom instantiation (Synopsys CBA).

2. Second choice, involves a buy-or-build decision. You need a qualified cell library (qualified by the ASIC foundry) If you own the masks (the
tooling) you have a customer-owned tooling (COT, pronounced “see-oh-tee”) solution (which is becoming very popular)

3. The third choice is to develop a cell library in-house. Many large computer and electronics companies make this choice. Each cell in an ASIC cell
library must contain the following.
A physical layout
A behavioral model
A HDL model
A detailed timing model
A test strategy
A circuit schematic
A cell icon
A routing model

Summary

• We could define an ASIC as a design style that uses a cell library

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• The difference between full-custom and semicustom ASICs

• The difference between standard-cell, gate-array, and programmable ASICs
• The ASIC design flow
• Design economics including part cost, NRE, and breakeven volume
• The contents and use of an ASIC cell library
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Datapath
 Data path logic in VLSI is a part of a logic VLSI network that is usually implemented using general purpose function blocks. These blocks
are repeatable and structured.
 The layout of bus wide logic that operates on data signals is called a Data path. The module ADD is called a Data path element
 The data path is a crucial component of the entire design.
 The speed of the data path elements often dominates the overall system performance.
 The data path layout automatically takes care of most of the interconnect between the cells.
 A regular layout produces predictable and equal delay for each bit.
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Data path Logic Cells

 Sum and COUT are the two functions implemented.
 The sum uses the parity function (output is 1 if there are an odd number of 1s in the inputs.
 The COUT uses 2-of-3 majority function (1 if the majority of the inputs are 1).
 Difference between using a data path and standard cells is that in standard cells there is no regularity to the arrangement of the cell within
the rows. Cells are placed together in rows but generally there is no regularity to the arrangement of the cells within the rows—we let
software arrange the cells and complete the interconnect.
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 Using a data path is one way to specify regularity to ASIC design tools.
 The following functions, sum and COUT implements the sum and carry out for a full adder (FA) with two data inputs (A,B) and a carry in,
Cin:

 Below figure shows the implementation of the data path adder. Figure a is a full adder cell with inputs a, B and Cin, sum output S and
Carry output COUT. A 4-bit ripple carry adder is implemented in figure (b). In 4-bit adder we connect the carry input, CIN[0] to VSS and
use COUT[3] COUT[2] to indicate arithmetic overflow. Notice that we build the ADD cell so that COUT[2] is available at the top of the
data path when we need it. Figure (c) shows the layout of the ADD cell. The A inputs, B inputs and S outputs all use m1 interconnect
running in horizontal direction. They are called as data signals. The other signals can enter or exit from top or bottom and run vertically
across the data path in m2. These are called control signals. Control signals are typically clocks and other signals common to elements. To
build a 4-bit adder we stack four DD cells creating the array structure shown in figure (d). In this case the A and B data bus inputs enter
from the left and bus S, the sum, exits at the right, but we can connect A,B and S to either side we want.
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 Advantages of Datapath:
1. Regular layout produces predictable and equal delay for each bit.
2. Interconnect between cells can be built into each cell.
 Disadvantages of Data path:
1. Area overhead, harder design
2. Datapath cells have to be predesigned for use in wide range of datapath sizes. Datapath cell design is harder than designing gate-
array macros or standard cells.

Datapath Elements
 Below figure shows the typical symbols used for datapath adder. For a bus, A[3:0] denotes a 32-bit bus with A[31] as the MSB and A[0]
as the LSB. We need to explicitly tie CIN[0] to VSS and use COUT[MSB] and COUT[MSB-1] to detect overflow.
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Adders:
 We can view addition in terms of Generate G[i] and Propagate, P[i] signals.

In the above, C[i] is the carry-out signal from stage I, equal to the carry in of stage (i+1). Thus, C[i]=COUT[i]=CIN[i+1)
For an adder we set the carry in to the first stage, C[-1] or C[0], to ‘0’.
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Ripple Carry Adder (RCA)

 Figure a shows conventional RCA. The delay of n-bit RCA is proportional to n. We can reduce the delay by using pairs of “go-faster” bubbles
to change from OR and AND gates to fast 2-input NAND gates.
 Alternatively, we can write the equations for the carry signal separately for odd and even stages separately in two different ways.

Where P[i]`=NOT(P[i]). Below equations allows us to build the carry chain from two-input NAND gates, one per cell, using different logic
in even and odd stages as shown in figure(b)
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Carry Save Adder:

 Instead of propagating the carries through each stage of RCA, a different approach is used in Carry Save Adder (CAS)
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 The inputs, A1, A2, A3 and outputs, S1 and S2 are buses. The input, CIN is the carry from stage (i-1). The carry in, CIN, is connected
directly to the output bus S1. The symbol is shown in figure (a). We connect CIN[0] to VSS and the output, COUT, is the carry out to stage
(i+1). The 4-bit CSA is shown in figure (b). The arithmetic overflow signal for ones complement or two’s complement arithmetic, 0V, is
XOR(COUT[MSB]COUT[MSB-1]) as shown in figure(c)
 In CSA, the carries are “saved” at each stage and shifted left onto the bus S1. There is thus no carry propagation and the delay of CSA is
constant. At the output of a CSA we still need to add the SI bus and the S2 to get an n-bit result using a final stage.(not shown in figures).
CSA can be used to add multiple inputs- as an example, an adder with four 4-bit inputs is shown in figure (d). In figure ( e) it shows how
the two CSA cells and the RCA cell together horizontally to form a bit slice and then the slices are stacked vertically to form the datapath.
We can register the CSA stages by adding vectors of flip-flops as shown in figure(f). This reduces the adder delay to that of the slowest
adder stage. By using registers between stages of combinational logic we use pipelining to increase the speed and pay a price of increased
area and introduce latency.
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Carry Bypass Adders:

 The problem with RCA is that every stages has to wait to make its carry decision, C[i], until the previous stage has calculated C[i-1]. But,
this critical path can be bypassed. For example, to bypass the carries for bits 4-7 of an adder we can compute BYPASS as BYPASS= P[4].
P[5]. P[6].P[7] and then use a mux as follows:
C[7]= (G[7]+P[7].C[6]). (BYPASS)’ +C[3]. BYPASS.
Adders based on this principle are called Carry-Bypass Adders (CBA)
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Carry-Skip Adder:
 Instead of checking the propagated signals we can check the inputs. For example, we compute
Skip=(A[i-1] XOR B[i-1] + (A[i] xor B[i]) and then use a mux to select C[i]
Thus, CSKIP[i]= (G[i]+P[i].C[i-1]). (SKIP)’ + C[i-2]. SKIP
A carry skip adder, or carry-bypass adder, is a faster binary adder that speeds up the carry propagation in a ripple-carry adder by
allowing the carry to "skip" over full adder blocks using multiplexers when all adders in a segment are in a propagate state. It uses
a propagate signal, generated from the individual adder inputs, to control the multiplexer and bypass the carry chain, thereby
reducing the overall worst-case delay compared to a simple ripple-carry adder.

Working
1. Blocks of Full Adders:
The adder is divided into segments or blocks, each containing a series of full adders.
2. Propagate Signal:
Within each block, a propagate signal (P) is generated. This signal indicates whether all the individual full adders in that block are in a
"propagate mode" (i.e., the carry in will be equal to the carry out).
3. Mux-based Skip:
Each block is followed by a 2:1 multiplexer.
4. Carry Bypassing:
1. If the propagate signal (P) for a block is 1 (all individual adders are propagating), the multiplexer selects the incoming
carry (Cin) to become the carry out for that block, effectively bypassing the carry through that block.
2. If the propagate signal (P) is 0 (at least one adder in the block is generating a carry), the carry is not skipped, and it
proceeds normally to the next full adder within the block to be calculated.
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5. Speed Improvement:
By allowing the carry to bypass segments when possible, the carry does not have to ripple sequentially through every single b it in a
large number, significantly reducing the worst-case delay.
Benefits
 Speed:

It is faster than a ripple-carry adder because it reduces the carry propagation path.
 Simplicity:
It offers a good balance between speed and area with a relatively simple and regular layout.
 Power Efficiency:
It can provide a good trade-off between operating speed and power dissipation.

Carry-Lookahead Adder and Brent-Kung Carry- Lookahead adder

We have
C[i]=G[i]+P[i]. C[i-1]
If we evaluate the basic equations of C[i] and S[i] in terms of P[i] and G[i] recursively for i=1, we get
C[1]=G[1]+P[1].C[0]= G[1]+P[1].(G[0+P[1].c[-1])
=G[1]+P[1].G[0]
 This result means that we can look ahead by two stages and calculate the carry into the third stage (bit2) which is C[1], using only the first
stage inputs(to calculate G[0]) and the second stage inputs. This is called carry Look Ahead Adder.

C[2]=G[2]+P[2].G[1]+P[2].P[1].G[0]
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C[3]=G[3]+P[2].G[2]+P[2].P[1].G[1]+P[3].P[2].P[1].G[0]
As we look ahead further these equations become more complex take longer time to calculation and the logic becomes less regular when
implemented using cells with a limited number of inputs. In the below figure, the figure(a) shows a regular 4-bit CLA which uses Carry-
Lookahead Generator cell(CLG). The structure of CLG is as shown in figure(b). The CLG generate the lookahead terms, C[0]-C[3].
Figure(c), the Cells L1,L2 and L3 are rearranged into a tree that has less delay. Cell L4 is added to calculate C[2] that is lost in the
translation. Figure(d) and € are simplified representations of figure (a) and (c). Figure(f) shows the lookahead logic for an 8-bit adder.
Brent-Kung adder:
 With this type of adders, reduces the delay and increases the regularity of carry-lookahead scheme. An 8-bit Brent-Kung CLA is shown in
figure(g). The output of the look ahead logic are the carry bits that form the sum. One advantage of this adder is that the delay from the
inputs to the outputs are more nearly equal than in other adders. This tends to reduce the number of unwanted and unnecessary switching
events and thus reduces power dissipation.
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Conditional Sum Adder:

 A conditional sum adder is a high speed digital circuit that uses a divide and conquer approach to add numbers, achieving logarithmic speed
by calculating two possible sum and carry sets one assuming a carry-in-of 0, and other assuming a carry in of 1 for each group of operand
bits.
 These sets are generated in parallel and then selected by a tree of multiplexers once the actual carry in is known, allowing fast addition
compared to all types of adders
 The below figure shows the simplest form of an n-bit conditional-sum adder that uses n single-bit conditional adders. H, together with a
tree of 2:1 MUXes (Qi-j). The conditional sum adder is usually the fastest of all the adders.
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Multipliers
 6-bit array multiplier is as shown below. Where A and B are 6-bit data which requires (5X6) number of adders. An n-bit array multiplier
has a delay proportional to n plus the delay of the CPA.
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 One thing we can do is to reduce the complexity by reducing the number of partial products. This is done by recoding the binary data by
using the below concept.
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 Suppose we wish to multiply 15 and 19. Instead of multiplying 15 and 19 we can calculate easily as (15X20)-15. Same concept is used
with binary multiplication.
 Example:
B=00010111 (decimal 16+4+2+1)=23. It has weight if 4. So need 4 adders.
It is easier to multiply A by the canonical signed-digit vector (CSD) vector D=00101Ȋ001 which is decimal equivalent of (32-8+1=23).
Now it has a weight of 3. So, only 3 operations to be done.
Recoding binary data B as a radix-2 signed bit
We can recode (or encode) any binary number B, as a CSD vector, D in canonical form as follows.
Canonical form means there is only one CSD vector for any number.

We can recode using a radix other than 2 as below

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Recoding binary data B as a radix-4 signed bit

Assume B is an (n+1)- digit tow’s complement number,

Using equation 2.61 we can encode any number by taking groups of 3-bits at a time and calculating
Ej=-2Bi +Bi-1 +Bi-2, Ej+1=-2Bi+2 +Bi-1 +Bi, ……..
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Where each 3-bit group overlaps by one bit. We pad B with 0. Bn…..B1B0, to match the first term in equation 6.1. If B has an odd number of
bits, then we extend the sign: Bn Bn-1……..B1 B0 0 For example,
#1. B=01011(Eleven), encodes to E=1 Ȋ Ȋ(read/write as 1 bar)
#2. B=101 then E= Ȋ 1
This is called booth encoding. It reduces number of partial products by a factor of two and thus considerably the area is reduced.
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Other datapath operators:

So far we have discussed about adder. Other datapath elements are as shown below.
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IO Cells:
Input and output buffers are required when it is required to convert from one to other logic levels like from TTL logic level to CMOS logic level
and vice versa. Below circuit is the tristate bidirectional output buffer circuit.
Operation: When the output enable, OE is ‘1’, the output section enabled and drives the I/O pad. When OE is ‘0’, the output buffer is placed in
high-impedance state.

Electro Static Discharge problem and Remedies

 The gate oxide in CMOS transistors is extremely thin. This leads the gate oxide of the I/O cell input transistors susceptible to breakdown
from static Electricity due to ESD.
 ESD arises when we or machines handle the package leads.
 Sometimes this problem is called as Electrical Overstress (EOS)
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 Since most ESD-related issues arte caused not by gate oxide breakdown, but by the thermal stress that occurs when the n-channel transistor
in an output driver overheats due to the large current that can flow in the drain diffusion connected to a pad during an ESD event. Protection
of I/O cells from ESD
 The input pads are normally tied to device structures that clamp the input voltage to below the gate breakdown voltage. Some I/O cells use
transistors with a special ESD implant that increases breakdown voltage and provides protection.
 Another solution is to use pnpn and npnp diffusion structures called silicon controlled rectifiers to clamp voltages and divert current to
protect the I/O circuits from ESD.

Latch-up problem and remedies

Latch-up is a low resistance connection between a power supply rail and a tub in a CMOS chip. It can be caused by a number of factors, including:
 A voltage applied to the chip's pins that is higher than the power supply voltage

 An electrostatic discharge (ESD) event

 Ionizing radiation some ways to prevent latch-up:

 Use latch-proof switches: These are simpler and more compact than discrete solutions.

 Add an insulating oxide layer: This is called a trench and it surrounds both the NMOS and PMOS transistors.

 Increase the distance between NMOS and PMOS devices: This increases the width of the lateral device and reduces the beta of the parasitic
devices.
 Use a Schottky diode: A Schottky diode can be added between Vdd and Vss to prevent SCR conduction.

 Use a latchup protection technology circuit: This shuts off the device when latch-up is detected.
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Cell Compilers
 The process of hand crafting circuits and layout for a full-custom IC is a time-consuming and error prone task. There are two types of
automated layout assembly tools, often known as Silicon compilers
 There are two types
 RAM compiler or multiplier compiler
 Provides programming languages that assembles layout from an input command file. This is more flexible.
 RAM compilers are available that produce single port RAM as well as dual port RAMs and multiport RAMs.
 In addition to producing layout we also need a model compiler so that we can verify the circuit at the behavioral level and we need a netlist
from netlist compiler  Silicon compilers are thus complex pieces of software.
 We assume that a silicon compiler will produce working silicon even if every configuration has not been tested.
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