THAMIRABHARANI ENGINEERING COLLEGE

(An Autonomous Institution)

Thatchanallur, Tirunelveli 627 358, Tamil Nadu.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING

EC3552 VLSI AND CHIP DESIGN

ASSIGNMENT- II

[Link] ASSIGNMENT TOPIC

1 Define setup and holding time.
2 What is C 2MOS register?
3 What is NORA CMOS?
4 Define Race condition?
5 Define bistability principle. Name the approaches used to accomplish the
bistable circuit.
6 Mention the problems occurred due to clock overlapping.
7 Differentiate monostable and astable sequential circuits.
8 Mention the disadvantages of Static Latches and Registers.
9 Draw the schematic of dynamic edge-triggered register.
10 What are the operation modes of NORA-CMOS logic style?
11 Discuss in detail about synchronous design.
12 Explain Dynamic latches and registers?

Course Coordinator HoD

 THAMIRABHARANI ENGINEERING COLLEGE
(An Autonomous Institution)
Thatchanallur, Tirunelveli 627 358, Tamil Nadu.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING

EC3552 VLSI AND CHIP DESIGN

ASSIGNMENT- II (ANSWER)
1. Define setup and holding time.
Set up time (tsu):
The time that the data input (D) is valid before the clock transition that is 0 to 1 transition for a
positive edge -triggered registers
Hold time (thold):
The time that the data input must remain valid after the clock edge.

2. What is C 2MOS register?

The positive edge triggered register based on master slave concept insensitive to clock overlap.
This is called clocked CMOS or C 2MOS.

3. What is NORA CMOS?

NORA-CMOS is a logic circuit that combines C2MOS pipeline and NORA dynamic logic
function blocks. Each module consists of a block of combinational logic with a mixture of static
and dynamic logic followed by a C2MOS latch.

4. Define Race condition?

When a CLK and inverter of CLK both are high for a short period of time (overlap period),both
sampling pass transistors conduct and there is a direct path from the D input to a Q output. So
output change at the rising edge of clock, which is undesired for a negative edge triggered
register. This is called race condition.

5. Define bistability principle. Name the approaches used to accomplish the bistable circuit.
Bistability principle states that, when the gain of the inverter in the transient region is larger than
1, there are two stable operating points (High and Low). Triggering is needed to change from one
state to another state.
Approaches for bistable circuit are,
i. Cutting the feedback loop
ii. Overpowering the feedback loop

6. Mention the problems occurred due to clock overlapping.

i. Race condition
ii. Undefined state
7. Differentiate monostable and astable sequential circuits.
[Link] Monostable circuits Astable circuits
1 Monostable circuits have only one Astable circuit has no stable states.
stable state.
2 A trigger event causes the circuit to The output oscillates back and forth between
go temporarily into another quasi- two quasi-stable states, with a period
stable state. determined by the circuit topology and
parameters.

8. Mention the disadvantages of Static Latches and Registers.

 Stored value remains valid as long as supply voltage is available.
 Complexity.

9. Draw the schematic of dynamic edge-triggered register.

10. What are the operation modes of NORA-CMOS logic style?

i. Precharge mode (hold mode)
ii. Evaluation mode

11. Discuss in detail about synchronous design.

Synchronous design is a system whose behavior can be defined from the knowledge of its signals
at discrete instants of time.

In Synchronous sequential circuit, the output depends on present and previous states of the inputs
at the clocked instances. The circuits use a memory element to store the previous sate. The
memory elements in these circuits will have clocks. All these clock signals are driven by the
same clock signal.
Using clock signal, state changes will occur across all storage elements.

These circuits are bit slower compared to asynchronous because they wait for the next clock
pulse to arrive to perform the next operation.

These circuits can be clocked or pulsed.

The Synchronous sequential circuits that use clock pulses in their inputs are called clocked-
sequential circuits.

It is very stable. The sequential circuits that change their state using the pulse and these are
called pulsed or unclocked sequential circuits.

In a clocked sequential circuit which has flip-flops or, in some instances, gated latches, for
memory elements there is a (synchronizing) periodic clock connected to the clock inputs of all
the memory elements of the circuit, to synchronize all internal changes of state.

Hence the operation of the entire circuit is controlled and synchronized by the periodic pulses of
the clock.

On the other hand in an unclocked or pulsed sequential circuit, such a clock is not present.

Pulse mode circuits require two consecutive transitions between 0 and 1 - that is a 0-pulse- or a 1
pulse to alter the circuit state.

A pulse -mode circuit is designed to respond to pulses of certain duration; the constant signals
between the pulses are null or spacer signals, which do not affect the circuit behavior.
Pulse outputs:

For pulsed sequential circuits these occur only for the duration of the respective input pulse and
in some cases for duration considerably less. For clocked sequential circuits these outputs occur
for the duration of the clock pulse.

Level outputs:

These change state at the start of the respective input or clock pulse and remain in that state until
the next state of output is required.

A requirement of synchronous sequential circuits is that the duration of the activating pulse or
clock pulse should be sufficiently low in value that the pulse (or clock) has disappeared by the
time the secondary (the flip-flops outputs) have taken on their new value; otherwise the circuit
will change state again.

This means that the storage elements (flip-flops) should be edge-triggered devices (for example:
D-type flip-flop, the JK flip-flop and their derivatives).

Limitations:

 All the flip-flops in synchronous sequential circuits must be connected to clock signal.
Clock signals are very high frequency signals and clock distribution consumes and
dissipated a large amount of heat.
 Critical path or the slowest path determines the maximum possible clock frequency. It is
slower than asynchronous circuits.

12. Explain Dynamic latches and registers?

Dynamic circuits are based on temporary storage of charge on parasitic capacitors. The absence
of charge denotes a 0, and presence of charge denotes a 1. Capacitor has some leakage. The
stored value can be kept in for some milliseconds. To preserve signal integrity, periodic refresh
is necessary.

1. Dynamic Transmission Gate Edge Triggered Registers

2. C2MOS with Clock Skew Insensitive Approach

3. True Single Phase Clocked Register

1. Dynamic Transmission Gate Edge Triggered Registers:

Figure 3.19 shows a fully dynamic positive edge triggered registered based on master-slave
concept. When clock is 0 input data is sampled on storage node 1 with capacitance C1 that
consisting of gate capacitance of I1, junction capacitance of T1 and overlap gate capacitance of
T1. During this period, the slave is in hold mode and the node 2 is in high impedance state. On
rising edge of clock, the transmission gate T2 turns on, and the sampled value at node 1
propagates to the output Q. Now node 2 stores the inverted value of node 1.

Advantages:

 Very efficient
 Zero hold time
[Link] of Nonoverlapping Clock:

Figure 3.20 shows the impact of non-overlapping clocks. During the 0-0 overlap period, MO of
T, and pMOS T, are simultaneously ON. This creates a direct path for data to flow from input of
the register to the Q output. This is called race condition. During the 1-1 overlap period an input-
output path exists through the pMOS of T, and the nMOS of T, that take care of the hold time
constraint. The data must be stable during the high-overlap period. The overlap period constraint
is given by,

The constraint for 1-1 overlap is given by,

2. C2MOS with Clock Skew Insensitive Approach:

i. C2MOS Register:

Figure 3.21 show a positive edge triggered register based on master slave concept insensitive to
clock overlap. This is called clocked CMOS or C2MOS. The operation of clocked CMOS has
two phases.

i. If clock is 0, the first tristate driver is turned ON, and the master stage act as inverter. This
inverts the D input on the internal node X. The master stage is in evaluation mode and slave
stage is in high impedance mode. Both transistors M7 and M8 are in OFF condition and this
decouples the output from the input. The output Q retains its previous value stored on the output
capacitor CL2.

ii. If clock is 1, the master stage is in hold mode making transistors M 3 and M4 in OFF condition.
The slave stage is in evaluation mode making the transistors M7 and M8 in ON condition. Now
the value stored in CL1 propagates to the output acting as an inverter.

ii. Dual Edge Register:

Figure 3.22 shows a C2MOS based dual edge triggered register. This sequential circuit samples
the input on both clock edges.) This circuit needs lower clock frequency resulting in power
savings. The circuit consists of two parallel master slave edge triggered registers, whose Outputs
are multiplexed by using tristate drivers.

When clock is 1, the positive latch with transistors M1 to M4 is sampling the inverted D input on
node X. Transistors M9 and M10 are in OFF condition and node Y is held stable. On falling edge
of clock, M5 to M8 turns ON and drives the inverted value of X to the output Q. When clock is 0,
transistors M1, M4., M9, M10 is turned ON to sample the inverted D input on node Y. On the
rising edge of clock, the bottom slave conducts and drives the inverted value on Y to node Q.
Thus data changes on both edges.

3. True Single Phase Clocked Register:

True Single Phase Clocked Register (TSPCR) uses single phase clock. Figure 3.23 and 3.24
shows a true single phase positive and negative latches respectively. In a positive latch, when
clock is high the latch is in transparent mode and corresponds to two cascaded inverters. The
latch is in non-inverting state and propagates the input to the output. When clock is low, both
inverters are disabled and latch is in hold mode. Now the pull-up networks are active and pull-
down circuits are disabled. So no signal can ever propagate from the in at of the latch to the
output in this mode. A register is constructed by cascading positive and negative latches.

Advantage:

i. Use of single clock phase.

Disadvantage:

i. Increase in number of transistors (twelve transistors are required).