UNIT-V

Serial data transfer schemes:-

In computer architecture and microprocessors, Serial Data Transfer is the process of sending data
one bit at a time, sequentially, over a single communication channel or wire.

While early computers heavily relied on parallel data transfer (sending 8, 16, or 32 bits
simultaneously over many wires), parallel buses suffer from "crosstalk" (electromagnetic
interference between wires) over long distances and require expensive, bulky cables. Today, almost
all modern communication (USB, Ethernet, SATA, PCIe) is serial.

Serial data transfer schemes are primarily classified in two ways: by synchronization (timing) and
by directionality (duplexing).

1. Classification by Synchronization (Timing)

The biggest challenge in serial communication is ensuring the receiver knows exactly when one bit
ends and the next bit begins.

A. Asynchronous Serial Transfer

In this scheme, there is no shared clock signal between the sender and the receiver.

 How it works: Because they don't share a clock, both devices must pre-agree on a specific
speed, known as the Baud Rate (e.g., 9600 bits per second).
 Framing: To alert the receiver that data is coming, the sender wraps the data in extra bits. It
sends a Start Bit (usually a logic 0), followed by the data bits (usually 8 bits), an optional
Parity bit for error checking, and one or more Stop Bits (logic 1).
 Pros: Requires fewer wires (just Tx, Rx, and Ground). Simple to implement.
 Cons: Slower. The extra start/stop bits add overhead (about 20% of the bandwidth is wasted
on timing bits).
 Examples: UART (Universal Asynchronous Receiver-Transmitter), classic RS-232 serial
ports.

B. Synchronous Serial Transfer

In this scheme, the sender and receiver share a common clock line.

 How it works: The "Master" device generates a continuous clock pulse. With every tick of
the clock, a bit of data is pushed across the data line. The receiver simply reads the data line
every time the clock pulses.
 Framing: Because the clock dictates the timing perfectly, there is no need for start or stop
bits. Data is sent continuously in large blocks or "frames."
 Pros: Extremely fast and highly efficient (no overhead bits).
 Cons: Requires an extra physical wire for the clock signal. Over very long distances, the
clock signal and data signal can fall out of sync (clock skew).
 Examples: SPI (Serial Peripheral Interface), I2C (Inter-Integrated Circuit).

2. Classification by Directionality (Duplexing)

This defines how the two devices share the communication channel.
  Simplex: Communication is strictly one-way. Device A can only send, and Device B can
only receive.
Example: A computer keyboard sending keystrokes to the PC, or a traditional radio
broadcast.
 Half-Duplex: Communication is two-way, but only one device can talk at a time. They
must take turns using the single data wire.
Example: Walkie-talkies ("Over"), or the I2C protocol.
 Full-Duplex: Communication is two-way and simultaneous. This usually requires two
separate data wires (one for Transmit, one for Receive).
Example: Telephone conversations, SPI, or standard UART.

3. Common Serial Protocols at a Glance

 UART: Asynchronous, Full-Duplex. Uses 2 wires (Tx, Rx). Point-to-point only.

 SPI (Serial Peripheral Interface): Synchronous, Full-Duplex. Uses 4 wires (Clock, Master
Out, Master In, Chip Select). Extremely fast, used for communicating with sensors and flash
memory on motherboards.
 I2C (Inter-Integrated Circuit): Synchronous, Half-Duplex. Uses just 2 wires (Clock,
Data). Slower than SPI, but allows multiple master devices and dozens of slave devices on
the same two wires.

To help you visualize how the timing and directionality alter the physical transfer of data, an
interactive simulator can be used to toggle between Sync/Async and the different duplex modes to
watch how the bits flow across the wires.

Asynchronous and Synchronous data transfer schemes:-

At the heart of all data transfer between two digital devices is a fundamental problem: timing.
When Device A sends a stream of electrical highs (1) and lows (0), how does Device B know
exactly where one bit ends and the next begins?

If Device B reads the line a fraction of a second too late, it might misread the data entirely.

To solve this, systems use either Asynchronous or Synchronous data transfer. The defining
difference between the two is the presence or absence of a shared Clock signal.

Here is a deep dive into how each scheme manages timing.

1. Asynchronous Data Transfer (No Shared Clock)

In asynchronous transfer, the sender and receiver do not share a physical clock wire. Because they
aren't marching to the exact same electrical beat, they must use other methods to keep their timing
aligned.

 The Agreement (Baud Rate): Both devices must be pre-configured to communicate at the
exact same speed, known as the baud rate (e.g., 9600 bits per second). This tells the receiver
roughly how long each bit should last.
 Framing (Start and Stop Bits): Because data can arrive at any random time (like a user
pressing keys on a keyboard), the sender must "wake up" the receiver. It does this by
wrapping every byte of data in extra timing bits:
o Idle State: When nothing is sending, the data line is held High (1).
o Start Bit: The sender drops the line to Low (0) for exactly one clock cycle. This
alerts the receiver that data is coming and synchronizes their internal timers.
o Data Bits: The actual 8 bits of data are sent.
 o Stop Bit: The line is pulled High (1) again to signal the end of the packet and give
the receiver time to process it.
 Pros: Requires fewer wires. Excellent for sporadic, unpredictable data (like human input).
 Cons: Inefficient. For every 8 bits of actual data, you must send 10 bits total (Start + 8 Data
+ Stop). This means 20% of the bandwidth is wasted on "overhead."

2. Synchronous Data Transfer (Shared Clock)

In synchronous transfer, the devices are physically wired together with an extra line dedicated
entirely to a Clock Signal.

 The Master Clock: One device (the Master) generates a continuous, steady square wave on
the clock wire.
 Lockstep Transmission: The sender pushes a bit of data onto the data wire exactly when
the clock wave goes up (the rising edge). The receiver reads the data wire exactly when the
clock wave goes down (the falling edge).
 Continuous Blocks: Because the shared clock dictates the timing perfectly, the sender
doesn't need to use Start or Stop bits to wake up the receiver. It can send massive,
continuous blocks of data (frames) without interruption.
 Pros: Highly efficient and extremely fast. There is zero overhead spent on Start/Stop bits,
meaning 100% of the bandwidth is used for actual data.
 Cons: Requires an extra physical wire. Over very long distances, the clock signal can
degrade or become misaligned with the data signal (a problem known as "clock skew").
Therefore, it is mostly used for short distances (like communicating between chips on a
single motherboard).

8251 USART architecture and interfacing:-

The 8251 USART (Universal Synchronous/Asynchronous Receiver/Transmitter) is a classic

programmable communication interface chip designed by Intel. While the 8259 PIC manages
interrupts, the 8251 manages serial communication.

Its primary job is to act as a translator between the microprocessor (which processes data in
parallel, 8 bits at a time) and the outside world (which often communicates serially, one bit at a
time).
Here is a detailed breakdown of its internal architecture and how it interfaces with a CPU.

1. Architecture of the 8251 USART

The internal architecture of the 8251 is divided into five main functional blocks.

A. Read/Write Control Logic

This is the brain of the chip that communicates directly with the CPU's control bus. It determines
what the CPU wants to do (read or write) and whether the CPU is sending raw data or programming
instructions.

 (Chip Select): Enables the 8251 when tied low. Usually connected to the CPU's
address decoding logic.
 (Control/Data): Tells the 8251 what type of information is on the data bus. If high
(1), the CPU is writing a control word or reading the status. If low (0), the CPU is writing or
reading actual data.
 and : Standard active-low read and write signals.
 CLK: The system clock input used for the internal operations of the 8251 (does not
determine the serial transmission baud rate).

B. Data Bus Buffer

An 8-bit bidirectional buffer (D₀ - D₇) that connects to the system data bus. All data, control words,
and status information flow through this buffer between the CPU and the 8251.

C. Transmitter Section

This section converts parallel data from the CPU into a serial bit stream.

 Transmit Buffer: Holds the parallel data given by the CPU.

 Transmit Control: Manages the conversion and timing.
 TxD (Transmit Data): The actual output pin where serial data leaves the chip.
 (Transmitter Clock): Controls the baud rate (speed) at which bits are pushed out.
 TxRDY (Transmitter Ready): A signal sent to the CPU indicating the buffer is empty and
ready to accept another character.
 TxE (Transmitter Empty): Indicates both the buffer and the internal shift register are
completely empty.

D. Receiver Section

This section does the exact opposite: it receives a serial bit stream and converts it into 8-bit parallel
data for the CPU.

 Receive Buffer: Assembles incoming bits into a parallel byte.

 Receive Control:
 RxD (Receive Data): The input pin where serial data enters the chip.
 (Receiver Clock): Controls the sampling rate for incoming bits.
 RxRDY (Receiver Ready): A signal sent to the CPU (often tied to an interrupt pin)
indicating a full character has been received and is waiting to be read.

E. Modem Control Section

Provides hardware handshake signals to communicate with older modems or other serial devices.
  (Data Set Ready) & (Data Terminal Ready): General-purpose handshake pins.
 (Request to Send) & (Clear to Send): Used to prevent the transmitter from
sending data until the receiving device is ready.

2. Interfacing the 8251 with a Microprocessor

Interfacing the 8251 to a microprocessor (like the 8085 or 8086) requires connecting three main
buses: Data, Control, and Address.

1. Data Bus Connection: Connect the CPU's D₀ - D₇ directly to the 8251's D₀ - D₇ pins.
2. Control Bus Connection: Connect the CPU's and to the corresponding pins on the
8251. The system clock and reset lines are also connected.
3. Address Decoding (The Tricky Part):
o The CPU uses the Address Bus to select the chip and specify what it wants to do.
o Higher-order address lines (e.g., A₁ - A₇) are passed through a logic gate (like a
NAND gate) to generate the (Chip Select) signal.
o The lowest address line, A₀, is usually connected directly to the pin.
o Result: This creates two specific memory or I/O port addresses for the 8251. For
example, writing to Port 0x40 (A₀ = 0) sends Data, while writing to Port 0x41 (A₀ =
1) sends a Control/Configuration word.

TTL to RS232C and RS232C to TTL conversion:-

This diagram illustrates the classic, "old-school" method of voltage conversion using a dedicated
pair of integrated circuits.
Before the invention of single-chip solutions like the MAX232 (which generates its own internal
voltages), systems had to use two separate chips to handle the transmit and receive lines, and the
motherboard itself had to supply the high voltages.

Here is a breakdown of exactly what is happening in the two halves of your diagram.

(a) TTL to RS-232C: The MC1488 Transmitter

The left side of the diagram shows the MC1488 Quad Line Driver. Its job is to take the weak
0V/5V signals from the logic chip (TTL) and amplify them into the high voltages required by the
RS-232 standard.

 The Power Supply (Crucial Difference): Look at the text at the bottom: PIN 14 = +12V
and PIN 1 = -12V. Unlike modern chips, the MC1488 cannot create its own high voltages.
The computer's power supply must physically provide dedicated +12V and -12V lines
directly to this chip.
 Logic Inversion: The "D" shaped symbols with the little circles (bubbles) on the output
represent logic inverting gates (specifically, NAND gates wired as inverters). This is where
the logic flip happens: a TTL 5V (Logic 1) goes in, and a -12V (RS-232 Logic 1) comes out.
 The 330pF Capacitors: You will notice small capacitors tied to the outputs (Pins 3, 6, 8)
going to ground. These are slew-rate limiting capacitors. RS-232 cables can be very long.
If the voltage transitions from +12V to -12V too incredibly fast, it creates a radio frequency
"ring" that causes interference (crosstalk) on neighboring wires. These capacitors
intentionally slow down the voltage change slightly to keep the signal clean.

(b) RS-232C to TTL: The Receiver (MC1489)

The right side of the diagram shows the receiver circuit.

(Note: The diagram labels this chip as the MC1459, but the industry standard partner to the
MC1488 is actually the MC1489 Quad Line Receiver. It is highly likely a typo in the original
textbook/source image, but the logic remains identical).

 Stepping Down: This chip receives the massive, dangerous ±12V signals from the outside
world and safely steps them down to 0V/5V so they do not destroy the microcontroller's
RxD (Receive Data) pin.
 The Power Supply: Because it is only outputting low voltages, look at the bottom text: PIN
14 = +5V and PIN 7 = GND. It does not require the heavy-duty ±12V rails.
 Logic Inversion: Again, the bubbles on the outputs show that the signal is inverted back.
An incoming -12V (RS-232 Logic 1) is flipped back into a safe +5V (TTL Logic 1).

Summary of the Flow

If your microcontroller wants to talk to an industrial machine, the signal path looks like this:

1. Microcontroller TxD outputs +5V.

2. MC1488 receives +5V, inverts it, and uses its heavy ±12V power rails to blast a -12V signal
down the long serial cable.
3. The industrial machine replies with a +12V signal down the cable.
4. MC1489 receives the +12V, absorbs the high voltage, inverts it, and gently hands a 0V signal
to the Microcontroller's RxD pin.
Sample program of serial data transfer:-
To see how the hardware concepts we've discussed (like baud rates, start/stop bits, and buffers)
translate into software, we can look at a classic assembly language program.

The 8051 Microcontroller is the industry standard for learning how to program serial ports
because it has a built-in UART (Universal Asynchronous Receiver-Transmitter) that operates very
similarly to the 8251 chip.

Here is a complete, well-documented assembly program that continuously transmits the letter 'A'
serially at a baud rate of 9600 bps.

The 8051 Serial Transmission Program

; =================================================================
; Program: Serial Transmission of character 'A' at 9600 Baud
; Hardware: 8051 Microcontroller (11.0592 MHz Crystal)
; =================================================================

ORG 0000H ; Set program origin/start address

; --- STEP 1: CONFIGURATION ---

MOV TMOD, #20H ; Configure Timer 1 in Mode 2 (8-bit auto-reload).
; The timer is used to generate the Baud Rate clock.

MOV TH1, #0FDH ; Load TH1 register with the hex value FD (-3).
; With an 11.0592 MHz crystal, this perfectly creates 9600
Baud.

MOV SCON, #50H ; Configure Serial Control Register (SCON) for Mode 1.
; 50H = 01010000 in binary.
; This sets 8-bit data transfer, 1 start bit, 1 stop bit.

SETB TR1 ; Start Timer 1. The internal baud clock is now ticking.

; --- STEP 2: TRANSMISSION LOOP ---

AGAIN:
MOV SBUF, #'A' ; Load the ASCII character 'A' into the Serial Buffer
(SBUF).
; The moment data hits SBUF, the hardware automatically
; adds the Start/Stop bits and begins shifting it out the
TxD pin.

; --- STEP 3: POLLING (WAITING FOR COMPLETION) ---

WAIT:
JNB TI, WAIT ; "Jump if Not Bit". Check the Transmit Interrupt (TI) flag.
; This loops in place until the 8051 finishes pushing the
last Stop Bit.

CLR TI ; The hardware set TI to 1 when finished. We must clear it

to 0
; so we can detect when the *next* transmission is finished.

SJMP AGAIN ; Short Jump back to 'AGAIN' to send the next 'A'.

END ; End of program

How the Code Connects to the Hardware

1. TMOD and TH1 (The Clock Generator):

In the 8251 architecture, we noted that a transmitter needs an external clock ( ) to
 dictate the speed. The 8051 uses its internal "Timer 1" to generate this clock. Loading #0FDH
into the timer creates exactly 9600 ticks per second.
2. SCON (Control Logic):
Writing #50H to this register is exactly like sending a control word to the 8251's Control
Logic block. It tells the hardware to use standard Asynchronous framing (1 Start bit, 8 Data
bits, 1 Stop bit).
3. SBUF (The Transmit Buffer):
This acts just like the "Data Bus Buffer" going into the "Transmit Buffer." When the CPU
executes:

MOV SBUF, #'A'

it drops the 8-bit parallel binary code for 'A' (01000001) into the register. The internal shift
register immediately takes over and starts pushing those bits out serially.

4. TI Flag (Transmitter Ready):

This software flag acts identically to the TxRDY hardware pin on the 8251. The CPU sits in
the WAIT loop, effectively polling this flag to say, “Are you done yet? Are you done yet?”
The moment the flag goes high, the CPU knows it is safe to send the next character.

Introduction to High-speed serial communications standards,

USB:-

The transition from classic, low-speed serial connections (like RS-232) to modern high-speed serial
standards was driven by a fundamental physics problem in computer architecture.

For a long time, engineers believed that sending data in parallel (8, 16, or 32 wires at once) was the
best way to achieve high speeds. However, at very high frequencies, parallel wires suffer from
crosstalk (electromagnetic interference between adjacent wires) and clock skew (data arriving at
slightly different times on different wires).

The industry realized it was actually faster and more reliable to send data sequentially over a single,
highly optimized pair of wires at blistering speeds. This led to the rise of high-speed serial
standards like PCIe, SATA, Ethernet, and the most ubiquitous of all: the Universal Serial Bus
(USB).

Here is an introduction to the core architecture and concepts of USB.

1. The Core Philosophy of USB

Before USB, connecting peripherals was a nightmare. You had to deal with dedicated ports (PS/2
for mice, parallel ports for printers, COM ports for modems), manual IRQ assignments, custom
drivers, and rebooting the PC to recognize new hardware.

USB was designed with four primary goals:

 Universal Connector: Replace the myriad of legacy ports with a single standard.
 Plug-and-Play (Hot-Swappable): Allow devices to be connected and disconnected while
the computer is running, without manual configuration.
 Power Delivery: Provide electrical power (originally 5V) over the same cable used for data,
eliminating the need for separate power bricks for small devices.
 Expandability: Allow up to 127 devices to be connected to a single host controller.
2. The Tiered-Star Topology

Unlike classic RS-232 (which is strictly point-to-point between two devices) or I2C (which is a
single shared bus line), USB uses a Tiered-Star Topology.

 The Host Controller (The Boss): There is only one master in a USB network—the Host
(usually the PC motherboard). The Host initiates all communication. A USB keyboard
cannot just send data; it must wait for the Host to ask for it.
 The Root Hub: Built directly into the Host, this provides the first physical USB ports.
 External Hubs: You can plug a hub into a hub, creating branches (up to 7 tiers deep).
 Devices (Nodes): These are the end-point peripherals (mice, cameras, hard drives) at the
ends of the branches.

3. How Data Flows: The Four Transfer Types

Because USB handles everything from a slow mouse to a high-speed webcam, the Host must
manage bandwidth carefully. When a device is plugged in, it tells the Host what kind of data it
sends. The Host then assigns it one of four distinct "Transfer Types":

1. Control Transfers: Used by the Host to configure a device immediately after it is plugged
in (a process called Enumeration). It asks the device "What are you, and what drivers do
you need?"
2. Interrupt Transfers: Used for devices that send small amounts of data and need a
guaranteed, fast response time.
Example: A mouse or keyboard.
(Note: Despite the name, this does not use traditional hardware interrupts; the Host simply
polls the device very frequently).
3. Isochronous Transfers: Used for streaming real-time data where continuous timing is
more important than perfect accuracy. It guarantees bandwidth but does not resend lost data
packets.
Example: Webcams or USB audio interfaces (a dropped pixel or audio pop is better than a
video freezing to resend data).
4. Bulk Transfers: Used for massive amounts of data where accuracy is 100% critical, but
timing is not. It uses whatever bandwidth is "left over" on the bus.
Example: Copying files to a USB flash drive or external hard drive.

4. The Evolution of Speed

USB achieves its high speeds through Differential Signaling (using two data wires, D+ and D-,
where the signal is the voltage difference between them, effectively canceling out electrical noise).

Over the years, the standard has evolved dramatically:

 USB 1.1 (Low/Full Speed): 1.5 Mbps to 12 Mbps. (Half-Duplex)

 USB 2.0 (High Speed): 480 Mbps. (Half-Duplex)
 USB 3.x (SuperSpeed): 5 Gbps to 20 Gbps. Introduced new physical wires to allow Full-
Duplex communication (simultaneous reading and writing).
 USB 4: Up to 80 Gbps, merging with the Thunderbolt protocol.

Interactive USB Topology Explorer

To help visualize how the Host Controller manages different devices and their specific transfer
types across the network tree, you can explore the simulator below.
Which specific aspect of USB would you like to dive into next: the physical packet structure (how
the 1s and 0s are arranged), or how enumeration (the plug-and-play process) actually works when
you plug a device in?