Advance Diploma in AI-Chip Design

(ADAC)

SEMESTER - 4
Module - 1

Microcontroller Programming
(ADAC LAB CODE: S1M4L01)
Assembly Level Language for Microprocessors
Table of Content

1. Aim of the Laboratory............................................................................3

2. EDA Tool...............................................................................................4
3. Process Flow.........................................................................................5
4. Design................................................................................................... 6
5. Run Simulation......................................................................................7
6. Conclusion.............................................................................................8
[Link] of the Laboratory
To sum of 10 numbers using 8085 microprocessor.
[Link]
Online compiler
[Link]
[Link] Program
; 8085 ALP to generate an Arithmetic Progression (AP) Series
LXI H, 2000H ; Point HL to the parameter initialization address
MOV C, M ; Load the total number of terms (N) into Register C
(Counter)
INX H ; Move HL to 2001H
MOV A, M ; Load the first term (a) into the Accumulator
INX H ; Move HL to 2002H
MOV B, M ; Load the common difference (d) into Register B
LXI H, 3000H ; Initialize HL to the starting output memory address
LOOP: MOV M, A ; Store the current AP term into the memory
location
ADD B ; Calculate next term by adding common difference: A = A + B
INX H ; Increment memory pointer to point to next storage location
DCR C ; Decrement term counter (C = C - 1)
JNZ LOOP ; If Counter C is not zero, repeat loop for next term
HLT ; Halt the execution
[Link] Simulation

This will print all the node voltages in a table format.

[Link]

Mini RISC Processor

A Complete RTL Design &
Verification Roadmap
Advanced Verilog & SystemVerilog Learning Path
 Table of Contents
• 1. Aim/Objectives
• 2. Introduction
• 3. Theory / Background
• 4. Procedure / Working / Process Flow
• 5. Algorithms / Design / Code
• 6. Practical Implementation
• 7. Simulation / Results
• 8. Observations
• 9. Advantages
• 10. Applications
• 11. Conclusion
• 12. References
 1. Aim/Objectives
The primary goal of this project is to design an 8-bit Mini RISC Processor that demonstrates
core concepts in digital design, Verilog hardware description language, and design
verification. This project bridges the gap between theoretical understanding and practical
chip design.

Specific Objectives:
• Learn fundamental Verilog constructs through modular design
• Design and implement a complete processor architecture from scratch
• Understand control flow, instruction decoding, and execution pipelines
• Develop testbenches and verification methodologies using SystemVerilog
• Create reusable, professional-grade RTL code suitable for production
• Build a comprehensive verification environment with assertions and coverage
• Gain experience in real-world chip design workflows
 2. Introduction
Processor design is at the heart of modern computing. Understanding how CPUs execute
instructions, manage data, and coordinate complex operations is essential for any digital
design engineer. This project provides a hands-on approach to learning these concepts
through building a Mini RISC processor.

What You'll Learn:

This structured roadmap covers six phases of development, from basic Verilog
fundamentals to advanced SystemVerilog verification techniques. Each phase builds upon
the previous one, ensuring a smooth learning curve while maintaining technical rigor.
The processor supports a small instruction set including MOV, ADD, SUB, LOAD, and STORE
operations. While simple, this instruction set is sufficient to demonstrate all key processor
concepts: instruction fetch, decode, execute, memory access, and write-back.

Why This Project?

• Resembles real-world chip design methodologies
• Comprehensive coverage of Verilog and SystemVerilog
• Builds a strong portfolio piece for hardware design careers
• Applicable to FPGA implementation and ASIC design
 3. Theory / Background
3.1 Processor Architecture Basics
A processor is a complex system that fetches, decodes, and executes instructions. The
fundamental building blocks include:
• Program Counter (PC): Tracks the current instruction address
• Instruction Memory: Stores the program instructions
• Register File: Fast storage for operands and results
• Arithmetic Logic Unit (ALU): Performs computations
• Control Unit: Orchestrates instruction execution via FSM
• Data Memory: Stores program data

3.2 Instruction Execution Pipeline

The processor follows a standard 6-stage pipeline:
1. RESET: Initialize all signals and clear memory
2. FETCH: Retrieve instruction from instruction memory using PC
3. DECODE: Parse instruction to extract opcode, operands, and immediates
4. EXECUTE: Perform ALU operation or branch calculation
5. MEMORY: Access data memory if load/store operation
6. WRITEBACK: Store result back to register file

3.3 Verilog Design Methodology

Verilog enables hardware designers to describe digital systems at various abstraction
levels. This project uses Behavioral Verilog for simple modules and Structural Verilog to
connect them, mirroring production design practices.
 4. Procedure / Working / Process Flow
4.1 Six-Phase Development Roadmap
Phase 1: Learn Basic Verilog
Master fundamental constructs through simple modules (Clock Divider, LED Blinker, ALU)

Phase 2: Storage Elements

Implement Register File, Program Counter, and Memory modules

Phase 3: CPU Assembly

Combine all modules into a complete processor (CPU Top-level)

Phase 4: Testbench Development

Create comprehensive testbenches with tasks, randomization, and monitoring

Phase 5: Example Programs

Load real assembly programs and verify correct execution

Phase 6: Verification
Build a full SystemVerilog verification environment with coverage and assertions

4.2 Development Workflow

• Design module RTL code in Verilog
• Write targeted testbenches for unit testing
• Simulate and debug using waveform analysis
• Integrate modules into higher-level hierarchy
• Perform system-level verification
• Add coverage metrics and assertions
• Document design decisions and test results
 5. Algorithms / Design / Code
5.1 ALU Operations
The ALU supports the following operations:
• ADD: Addition
• SUB: Subtraction
• AND: Bitwise AND
• OR: Bitwise OR
• XOR: Bitwise XOR
• NOT: Bitwise NOT
• SHL: Shift Left
• SHR: Shift Right
• CMP: Compare

5.2 Instruction Set

The processor executes the following instruction types:
• MOV: Move immediate or register value to destination register
• ADD: Add two registers, store in destination
• SUB: Subtract source from destination
• LOAD: Load value from data memory
• STORE: Store register value to data memory
• JMP: Jump to specified address
• CMP: Compare two registers (set flags)
• HALT: Stop execution

5.3 Instruction Format

Instructions are 16 bits wide with the following structure:
[Opcode: 4 bits][Destination: 3 bits][Source: 3 bits][Immediate: 6 bits]

5.4 Register File

The processor includes 8 general-purpose registers (R0-R7), each 8 bits wide. R0 is often
used as a zero register by convention.
 5.5 Control FSM States
• RESET → FETCH
• FETCH → DECODE
• DECODE → EXECUTE
• EXECUTE → MEMORY
• MEMORY → WRITEBACK
• WRITEBACK → FETCH (loop) or HALT
 6. Practical Implementation
6.1 Module Hierarchy
The design follows a hierarchical approach with the following modules:
• alu.v: 8-bit arithmetic and logic unit
• register_file.v: 8 registers with dual-port read, single-port write
• pc.v: Program counter with increment and jump support
• instruction_memory.v: ROM storing program instructions
• data_memory.v: RAM for load/store operations
• decoder.v: Instruction decoder extracting fields
• control_unit.v: FSM coordinating execution stages
• cpu_top.v: Top-level module connecting all submodules

6.2 File Organization

The project is organized as follows:
• rtl/: Verilog RTL modules
• tb/: Testbench files
• programs/: Assembly programs in hex format
• waves/: VCD waveform files
• docs/: Documentation and diagrams

6.3 Simulation Setup

Simulations use open-source tools (Icarus Verilog, ModelSim) or commercial simulators
(VCS, Xcelium). The testbench includes clock generation, reset sequencing, instruction
loading, and result monitoring.
 7. Simulation / Results
7.1 Testbench Methodology
The comprehensive testbench includes:
• Clock generator (period = 10ns)
• Reset task for initialization
• Instruction loader from hex files
• Register and memory dump utilities
• Waveform generation (VCD format)
• Assertion-based checking
• Functional coverage tracking

7.2 Example Test Program

The following assembly program demonstrates basic processor functionality:
MOV R1, 5 # Load 5 into R1
MOV R2, 10 # Load 10 into R2
ADD R3, R1, R2 # R3 = R1 + R2 = 15
STORE R3, 20 # Store R3 to memory address 20
LOAD R4, 20 # Load from address 20 into R4
SUB R5, R4, R1 # R5 = R4 - R1 = 10
HALT # End execution

7.3 Expected Results

After executing the test program:
• R1 = 0x05
• R2 = 0x0A
• R3 = 0x0F
• Memory[20] = 0x0F
• R4 = 0x0F
• R5 = 0x0A

7.4 Waveform Analysis

Simulation generates VCD waveform files that show signal transitions in detail. Key signals
monitored include clock, reset, PC, instruction, register writes, and memory accesses.
 8. Observations
8.1 Design Insights
• Simple 6-stage pipeline is sufficient for correct execution
• Proper reset sequencing is critical to avoid undefined states
• Memory access patterns reveal instruction efficiency
• Clock frequency constraints depend on critical path
• Modular design enables efficient debugging and verification

8.2 Verification Observations

• Random instruction generation exposes corner cases
• Functional coverage identifies untested code paths
• Assertions catch design specification violations early
• Constrained-random testing is more effective than directed tests

8.3 Performance Metrics

The processor achieves:
• Instructions Per Cycle (IPC): 1 (one instruction per 6 clock cycles)
• Maximum Frequency: ~100 MHz on FPGA (technology-dependent)
• Power Consumption: Minimal (instruction-dependent)
 9. Advantages
9.1 Learning Value
• Teaches all essential Verilog/SystemVerilog concepts
• Bridges gap between theory and practice
• Real-world design patterns and methodologies
• Portfolio-quality project for job applications

9.2 Extensibility
• Architecture supports adding new instruction types
• Can be extended to 16-bit or 32-bit design
• Pipeline can be deepened for higher clock frequencies
• Verification methodology scales to larger designs

9.3 Practical Applications

• Foundation for FPGA-based processor implementation
• Starting point for custom accelerator design
• Test vehicle for new design techniques
• Reference implementation for teaching
 10. Applications
10.1 Industrial Applications
• Embedded system controllers
• Microcontroller design and verification
• FPGA-based accelerators
• Custom instruction set processors

10.2 Research Applications

• Novel instruction set architectures
• Energy-efficient processor designs
• Specialized processing units
• Hardware acceleration for AI/ML workloads

10.3 Educational Applications

• Teaching digital design fundamentals
• Verification methodology courses
• RTL design best practices
• FPGA development training
 11. Conclusion
This Mini RISC Processor project provides a comprehensive pathway from Verilog basics to
professional chip design and verification. By progressing through six phases and
implementing a complete processor from first principles, you develop skills directly
applicable to real-world hardware design.
The project demonstrates that complex systems can be built by combining simple, well-
designed modules. This modular approach, combined with rigorous verification, is the
foundation of modern chip design.
Beyond the technical skills, this project teaches the importance of architecture, planning,
and verification. These soft skills are equally valuable as the technical knowledge and are
highly sought in the semiconductor industry.

Key Takeaways:
• Master Verilog through structured, hands-on learning
• Design complex systems using modularity and hierarchy
• Implement professional verification methodologies
• Build a portfolio piece that impresses employers
• Understand real-world chip design workflows
As you progress through this roadmap, you are not just building a processor—you are
building the foundation for a career in digital design and hardware engineering.
12. References
[1] Morris, M. Mano, & Michael D. Ciletti. "Digital Design." (6th ed.). Pearson, 2018.
[2] Sutherland, S., Davidmann, S., & Flake, P. "SystemVerilog for Design." (2nd ed.).
Springer, 2006.
[3] Palnitkar, S. "Verilog HDL." (2nd ed.). Prentice Hall, 2003.
[4] Ciletti, M. D. "Advanced Digital Design with the Verilog HDL." (2nd ed.). Prentice Hall,
2010.
[5] IEEE. "IEEE Standard for Verilog Hardware Description Language." IEEE Std 1364-2005,
2006.
[6] Accellera. "SystemVerilog IEEE 1800 Language Reference Manual." 2017.
[7] ARM. "ARM Cortex-M4 Devices Generic User Guide." ARM, 2011.
[8] Intel. "Intel 64 and IA-32 Architectures Software Developer Manuals." Intel, 2023.
[9] Open-source tools: Icarus Verilog, Yosys, GTKWave.
[10] Online resources: EDA Playground, HDLBits, Stack Overflow Electronics.