Decoder:

A decoder is a combinational circuit that detects the presence of a specified

combination of bits (code) on its inputs and indicates the presence of that code by a
specified output level. A binary decoder converts the set of binary code to the set
of outputs.

 In its general form, Decoder is a combinational circuit that has 'n' input lines
and maximum of 2n output lines.
 If the n-bit decoded information has unused or don‟t care combinations, the
decoder output will have less than 2𝑛 outputs.

A0
Inputs , n A1
n to 2n 𝑂𝑢𝑡𝑝𝑢𝑡(𝑚) ≤ 2𝑛
An-1
Decoder
Low active 𝐸
enable
n -to -m line decoder
n:1
 for n to m line decoder , where m ≤ 2𝑛 , there are maximum 2𝑛 min terms of
n-input variables. Multiplexer
 The name decoder is also used in conjunction with some code converters
such as BCD to Seven Segment decoder.
 For each possible input condition, one and only one output signal will be
„high‟. Therefore, a decoder can be considered a minterm generator with
each output corresponding to exactly one minterm

Applications:
Used for the following code conversions
 Binary code to Octal code
 Binary code to hexadecimal code
 Binary code to Decimal code

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2 –to-4 line decoder or 2 x 4 decoder

Here, n=2 , decoded output = 22 =4 ; there are four decoded output, each
representing one of the minterm of 2-input variables.
Number of No of output lines or decoded minterms)
binary input
lines
2 x4 decoder 2 4 (m0 , m1, m2, m3 )
3 x8 decoder 3 8(m0 , m1, m2, ……………. m7)
4 x16 decoder 4 16 (m0 , m1, m2, ………… m15)
5 x32 decoder 5 32 (m0 , m1, m2,…………. m31)
6 x 64 decoder 6 64(m0 , m1, m2,…………. m63)

Logic symbols of 2 x 4 decoder are shown below in figure(a) and figure(b) respectively. Decoder
in fig(a) is with enable pin and inverted output and fig(b) is without enable pin.

A D0
Inputs 2x4 D1 𝑂𝑢𝑡𝑝𝑢𝑡
B Decoder D2
D3

n:1
Figure (a) : 2 x 4 decoder with inverted input Figure(b) : 2 x 4 decoder without enable, E
Multiplexer
Truth table of 2 x 4 decoder with normal output, there is no enable pin

Binary Inputs Decoded output

A B D0 D1 D2 D3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

The decoded outputs are

𝐷0 = 𝐴 𝐵 ; 𝐷1 = 𝐴 𝐵 ;𝐷0 = 𝐴 𝐵; 𝐷0 = 𝐴𝐵

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 Figure: logic diagram of 2 x 4 decoder with AND gates

The decoder circuit using NAND gates, results in an active-“LOW” output while the rest outputs
will be “HIGH”. As a NAND gate produces the AND operation with an inverted output,
the NAND decoder looks like this with its inverted truth table. In case of NAND decoder, only
one output can be LOW and equal to logic “0” at any given time, with all the other outputs being
HIGH at logic “1”.

Truth table of 2 x 4 decoder with NAND gates without enable

Binary Inputs Decoded output

A B Q0 Q1 Q2 Q3
0 0 0 1 1 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 1 1 1 0

Figure: Logic diagram of 2 x 4 decoder with NAND gates

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Decoders are also available with an additional “Enable” input pin which allows the decoded
output to be turned “ON” or “OFF” by applying a logic “1” or logic “0” respectively to it. So for
example, when the enable input is at logic level “0”, (E = 0) all outputs are “OFF” at logic “0”
(for AND gates) regardless of the state of the inputs A and B.

Decoders with the enable pin the two inputs AND gate or two input NAND gates are replaced
with the three inputs AND gate or three input NAND gates respectively.

Truth table of 2 x 4 decoder with high active enable pin

Enable Inputs Decoded output

E A B Y0 Y1 Y2 Y3
0 x x 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1

Logic diagram of 2 x 4 decoder with high active enable

Truth table of 2 x 4 decoder for inverted output with low active enable

Enable Inputs Decoded output

A B D0 D1 D2 D3
1 x x 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0

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 D0

D1
A
D2
B

D3
Enable(E)

Figure: Logic diagram of 2 x 4 decoder with low active enable

3 x 8 Decoder or 3 to 8- line decoder

The three inputs are decoded to the eight outputs. Each output representing one of the minterm
of three input variables. There are 8 minterms in the decoded output.
Truth table of 3 x 8 decoder ; 1= HIGH , 0= LOW
Inputs Decoded Outputs
x y z D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

Figure: Logic diagram of 3 x 8 decoder

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Design of BCD to Decimal decoder:
 The 0 to 9 (10 decimal digits can be represented by the BCD code(8421)).
 The BCD code has four bits therefore; the decoder should have four inputs to accept the
coded digit and ten outputs.
 This can be implemented by 4-to- 10 line decoder.
 The 10 outputs can be map by 10 blocks in k-map. But there are 6-don‟t care conditions
also.
AB CD
00 01 11 10
D0 D1 D3 D2
00
D4 D5 D7 D6
01

11 x x x x

10 D8 D9 x x

The literals D0 and D1 cannot combined with any don‟t care minterm. All other minterms are
combined with some don‟t care minterms.

The decoded output are ;

𝐷0 = 𝐴 𝐵 𝐶 𝐷 ; 𝐷1 = 𝐴 𝐵 𝐶 𝐷 ; 𝐷2 = 𝐵 𝐶 𝐷 ; 𝐷3 = 𝐵 𝐶 𝐷 ; 𝐷4 = 𝐵 𝐶 𝐷 ; 𝐷5 = 𝐵𝐶 𝐷
𝐷6 = 𝐵 𝐶 𝐷 ; 𝐷7 = 𝐵 𝐶 𝐷 ; 𝐷8 = 𝐴 𝐷 ; 𝐷9 = 𝐴 𝐷 ;

Figure: Logic diagram of BCD to Decimal decoder.

Logic diagram of BCD to Decimal decoder.

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Ex. Prob.: (i) Implement a full adder circuit with a decoder and two OR gates.

(ii) Implement a full adder circuit with a decoder and NAND gates.

Solution:

The sum and carry expression of the full adder is given:

S (x,y,z) = Σ ( 1,2,4,7)

C (x,y,z) = Σ ( 3,5,6,7)

Implementation of Sum(S) and Carry© using decoder and NAND gates

m0
m1
m2 S
x 3x8 m3
Decoder m4
Inputs y m5 C
m6
z
m7

Prob. Show how using a 3-to-8 decoder and multi-input OR gates following
Boolean expressions can be realized simultaneously. F1 (A, B, C) = m(O, 4, 6);
F2(A, B, C) = l:m(O, 5); F2(A, B, C) = l:m(l, 2, 3, 7)

Solution Since there are three variables then we need 3 x 8 decoder to implement
the above Boolean functions:

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Ex. Construct the 4 x 16 decoder using 3 x8 decoders.

The enable pin of both the decoders are used as one input of the decoder.

Decoders with enable inputs can be connected together to form a large decoder
circuit. Example 3 x 8 decoder with enable inputs can be connected to form a 4 x
16 decoder. Here enable is high active( enable when E=1, disable when E=0)

When w=0, the top decoder is enabled and other is disabled. The top decoder eight
output minterms are 0000 to 0111 and bottom decoder outputs are all 0‟s.

When w=1, the top decoder is disabled and bottom decoder is enabled. The top
decoder eight output are all 0‟s. The bottom decoder output minterms are 1000 to
1111.

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Encoder:

An encoder is a combinational logic circuit that essentially performs a “reverse”

decoder function. An encoder accepts an active level on one of its inputs
representing a digit, such as a decimal or octal digit, and converts it to a coded
output, such as BCD or binary. Encoders can also be devised to encode various
symbols and alphabetic characters. The process of converting from familiar
symbols or numbers to a coded format is called encoding

 In its general form, encoder is a combinational circuit that has 2𝑛 input lines
and n output lines. The output lines generate the binary codes corresponding
to the input binary values

There are eight binary inputs corresponding to each octal digit and three output
lines to generate the corresponding binary number.

Truth table of 8 x 3 Encoder

From the truth table the logic Boolean functions are as given

The logic diagram of 8 x 3 encoder is given below

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 Logic diagram of 8 x 3 decoder.

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