What is General Register Organization?

A set of flip-flops forms a register. A register is a unique high-speed storage area in the CPU. The registers speed
up the implementation of programs.
Functions of registers:-
 It can support a temporary storage location for data. It speed up the data access.
 It can save the status of the CPU and data about the directly implementing program.

Example − Address of the next program instruction, signals get from the external devices and error messages, and
including different data is saved in the registers.
If a CPU includes some registers, therefore a common bus can link these registers. A general organization of seven
CPU registers is displayed in the figure.

The CPU bus system is managed by the control unit. The control unit explicit the data flow through the ALU by
choosing the function of the ALU and components of the system.
Consider R1 ← R2 + R3, the following are the functions implemented within the CPU −
MUX A Selector (SELA) − It can place R2 into bus A.
MUX B Selector (SELB) − It can place R3 into bus B.
ALU Operation Selector (OPR) − It can select the arithmetic addition (ADD).
Decoder Destination Selector (SELD) − It can transfers the result into R1.
The multiplexers of 3-state gates are performed with the buses. The state of 14 binary selection inputs determines
the control word. The 14-bit control word defines a micro-operation.
The encoding of register selection fields is specified in the table.
Encoding of Register Selection Field

Binary Code SELA SELB SELD

Binary Code SELA SELB SELD

000 Input Input None

001 R1 R1 R1

010 R2 R2 R2

011 R3 R3 R3

100 R4 R4 R4

101 R5 R5 R5

110 R6 R6 R6

111 R7 R7 R7
There are several micro-operations are implemented by the ALU. Few of the operations implemented by the ALU
are displayed in the table.
Encoding of ALU Operations

OPR Select Operation Symbol

00000 Transfer A TSFA

00001 Increment A INCA

00010 Add A + B ADD

00101 Subtract A - B SUB

00110 Decrement A DECA

01000 ADD A and B AND

01010 OR A and B OR

01100 XOR A and B XOR

01110 Complement A COMA

10000 Shift right A SHRA

11000 Shift left A SHLA

There are some ALU micro-operations are shown in the table.
ALU Micro-Operations

Micro-operation SELA SELB SELD OPR Control Word

R1 ← R2 – R3 R2 R3 R1 SUB 010 011 001 00101

R4 ← R4 ∨ R5 R4 R5 R4 OR 100 101 100 01010

R6 ← R6 + R1 - R6 R1 INCA 110 000 110 00001

R7 ← R1 R1 - R7 TSFA 001 000 111 00000

Output ← R2 R2 – None TSFA 010 000 000 00000

Output ← Input Input - None TSFA 000 000 000 00000

R4 ← shl R4 R4 - R4 SHLA 100 000 100 11000

R5 ← 0 R5 R5 R5 XOR 101 101 101 01100

What is Memory Stack in Computer Architecture?

A stack can be executed in the CPU by analyzing an area of the computer memory to a stack operation and
utilizing a processor register as a stack pointer. In this method, it is performed in a random access memory
connected to the CPU.
An area of the computer memory is broken into three segments such as program, data, and stack. The address of
the next instruction in the program is saved in the pointer Program Counter (PC). The Address Register (AR) points
to an array of the information. SP (Stack Pointer) continually influences the address of the element present at the
top of the stack.
The three registers that are linked to the common bus are PC, AR, and SP. PC can read
the instruction during the fetch stage. An operand is read during execute stage using the address register. An
element is pushed into or popped from the stack using a stack pointer.
 In the figure, the SP points to a beginning value ‘2001’. Therefore, the stack increase with decreasing addresses.
The first element is saved at address 2000, the next element is saved at address 1999 and the last element is saved
at address 1000.
A computer performs a task based on the instruction provided. Instruction in computers comprises groups
called fields. These fields contain different information as for computers everything is in 0 and 1 so each field
has different significance based on which a CPU decides what to perform. The most common fields are:
 Operation field specifies the operation to be performed like addition.
 Address field which contains the location of the operand, i.e., register or memory location.
 Mode field which specifies how operand is to be founded.

Instruction is of variable length depending upon the number of addresses it contains. Generally, CPU
organization is of three types based on the number of address fields:
1. Single Accumulator organization
2. General register organization
3. Stack organization

In the first organization, the operation is done involving a special register called the accumulator. In second on
multiple registers are used for the computation purpose. In the third organization the work on stack basis
operation due to which it does not contain any address field. Only a single organization doesn’t need to be
applied, a blend of various organizations is mostly what we see generally.
Based on the number of address, instructions are classified as:
Note that we will use X = (A+B)*(C+D) expression to showcase the procedure.

1. Zero Address Instructions –

A stack-based computer does not use the address field in the instruction. To evaluate an expression first it is
converted to reverse Polish Notation i.e. Postfix Notation.
Expression: X = (A+B)*(C+D)
Postfixed : X = AB+CD+*
TOP means top of stack
M[X] is any memory location
 PUSH A TOP = A

PUSH B TOP = B

ADD TOP = A+B

PUSH C TOP = C

PUSH D TOP = D

ADD TOP = C+D

MUL TOP = (C+D)*(A+B)

POP X M[X] = TOP

2 .One Address Instructions –

This uses an implied ACCUMULATOR register for data manipulation. One operand is in the accumulator and the
other is in the register or memory location. Implied means that the CPU already knows that one operand is in
the accumulator so there is no need to specify it.

Expression: X = (A+B)*(C+D)
AC is accumulator
M[] is any memory location
M[T] is temporary location

LOAD A AC = M[A]

ADD B AC = AC + M[B]

STORE T M[T] = AC

LOAD C AC = M[C]

ADD D AC = AC + M[D]

MUL T AC = AC * M[T]

STORE X M[X] = AC
[Link] Address Instructions

This is common in commercial computers. Here two addresses can be specified in the instruction. Unlike earlier
in one address instruction, the result was stored in the accumulator, here the result can be stored at different
locations rather than just accumulators, but require more number of bit to represent address.

Here destination address can also contain operand.

Expression: X = (A+B)*(C+D)
R1, R2 are registers
M[] is any memory location

MOV R1, A R1 = M[A]

ADD R1, B R1 = R1 + M[B]

MOV R2, C R2 = C

ADD R2, D R2 = R2 + D

MUL R1, R2 R1 = R1 * R2

MOV X, R1 M[X] = R1

[Link] Address Instructions –

This has three address field to specify a register or a memory location. Program created are much short in size
but number of bits per instruction increase. These instructions make creation of program much easier but it
does not mean that program will run much faster because now instruction only contain more information but
each micro operation (changing content of register, loading address in address bus etc.) will be performed in
one cycle only.

Expression: X = (A+B)*(C+D)
R1, R2 are registers
M[] is any memory location

ADD R1, A, B R1 = M[A] + M[B]

ADD R2, C, D R2 = M[C] + M[D]

 X, R1,
MUL M[X] = R1 * R2
R2

What is data transfer instruction process in Computer Architecture?

Data transfer instructions transfer the data between memory and processor registers, processor registers, and I/O
devices, and from one processor register to another. There are eight commonly used data transfer instructions.
Each instruction is represented by a mnemonic symbol.
The table shows the eight data transfer instructions and their respective mnemonic symbols.
Data Transfer Instructions

Name Mnemonic Symbols

Load LD

Store ST

Move MOV

Exchange XCH

Input In

Output OUT

Push PUSH

Pop POP
The instructions can be described as follows −
 Load − The load instruction is used to transfer data from the memory to a processor register, which is usually
an accumulator.
 Store − The store instruction transfers data from processor registers to memory.
 Move − The move instruction transfers data from processor register to memory or memory to processor
register or between processor registers itself.
 Exchange − The exchange instruction swaps information either between two registers or between a register
and a memory word.
 Input − The input instruction transfers data between the processor register and the input terminal.
 Output − The output instruction transfers data between the processor register and the output terminal.
 Push and Pop − The push and pop instructions transfer data between a processor register and memory
stack.
All these instructions are associated with a variety of addressing modes. Some assembly language instructions use
different mnemonic symbols just to differentiate between the different addressing modes.
Example − The mnemonic symbols for load immediate is LDI.
Thus, it is necessary to be familiar with various addressing modes and different types of instructions to write
efficient assembly language programs for a computer.

Arithmetic instructions in 8085 microprocessor

Arithmetic Instructions are the instructions which perform basic arithmetic operations such as addition,
subtraction and a few more. In 8085 microprocessor, the destination operand is generally the accumulator.
Following is the table showing the list of arithmetic instructions:

Opcode Operand Explanation Example

ADD R A=A+R ADD B

ADD M A = A + Mc ADD 2050

ADI 8-bit data A = A + 8-bit data ADI 50

ADC R A = A + R + prev. carry ADC B

ADC M A = A + Mc + prev. carry ADC 2050

ACI 8-bit data A = A + 8-bit data + prev. carry ACI 50

SUB R A=A–R SUB B

SUB M A = A – Mc SUB 2050

SUI 8-bit data A = A – 8-bit data SUI 50

SBB R A = A – R – prev. carry SBB B

SBB M A = A – Mc -prev. carry SBB 2050

SBI 8-bit data A = A – 8-bit data – prev. carry SBI 50

INR R R=R+1 INR B

INR M M = Mc + 1 INR 2050

INX r.p. r.p. = r.p. + 1 INX H

DCR R R=R–1 DCR B

DCR M M = Mc – 1 DCR 2050

DCX r.p. r.p. = r.p. – 1 DCX H

DAD r.p. HL = HL + r.p. DAD H

1 Add) – The content of operand are added to the content of the accumulator and the result is stored in
accumulator .
with the addition instruction , the following 3 operations can be done.
1) any 8 bit number can be added to the contents of the accumulator and the result is stored in the
accumulator.
2) The contents of a register can be added to the contents of the accumulator and result is stored in the
accumulator .
3) The contents of a memory location can be added to the contents of the accumulator and result is stored in
accumulator.
this 1 byte instruction.
example – addb c it adds the content of accumulator to the content of the register b
2) SUB Any 8 bit data or the contents of a register or contents of a memory location can be subtracted from
the contents of the accumulator.
with the subtraction instruction the following 3 operator can be done .
1) any 8 bit number can be subtracted from the contents of the accumulator . The result is stored in the
accumulator.
In the table, R stands for register M stands for memory Mc stands for memory contents r.p. stands for register
pair

Logical instructions in 8085 microprocessor

Logical instructions are the instructions that perform basic logical operations such as AND, OR, etc. In the 8085
microprocessor, the destination operand is always the accumulator. Here logical operation works on a bitwise
level.
Following is the table showing the list of logical instructions:

OPERAN
OPCODE D DESTINATION EXAMPLE

ANA R A = A AND R ANA B

ANA M A = A AND Mc ANA 2050

ANI 8-bit data A = A AND 8-bit data ANI 50

ORA R A = A OR R ORA B

ORA M A = A OR Mc ORA 2050

ORI 8-bit data A = A OR 8-bit data ORI 50

XRA R A = A XOR R XRA B

XRA M A = A XOR Mc XRA 2050

XRI 8-bit data A = A XOR 8-bit data XRI 50

CMA none A = 1’s complement of A CMA

CMP R Compares R with A and triggers the flag register CMP B

 OPERAN
OPCODE D DESTINATION EXAMPLE

CMP M Compares Mc with A and triggers the flag register CMP 2050

CPI 8-bit data Compares 8-bit data with A and triggers the flag register CPI 50

RRC none Rotate accumulator right without carry RRC

RLC none Rotate accumulator left without carry RLC

RAR none Rotate accumulator right with carry RAR

RAL none Rotate accumulator left with carry RAR

CMC none Compliments the carry flag CMC

STC none Sets the carry flag STC

In the table,
R stands for register
M stands for memory
Mc stands for memory contents

SHIFT INSTRUCTIONS

Shift instructions allow the bits of a register or memory byte to be shifted one bit place to the left or to the right.
There are two types of shift instructions — logical and arithmetic. Logical shifts consider the contents of the
register or memory byte to be just a bit pattern when the shift is made.

SOFTWARE INTERRUP

 A software interrupt is invoked by software and is considered one of the ways to communicate with the
kernel or to invoke system calls, especially during error or exception handling. It indirectly interrupts the
central processing unit.
 A software interrupt often occurs when an application software terminates or when it requests the
operating system for some service.
 All software interrupts are associated with an interrupt handler, which is actually just a interrupt service
routine that is activated when an interrupt happens.

HARDWARE INTERRUPT

 Hardware interrupt is caused by any peripheral device by sending a signal through a specified pin to the
microprocessor.
 The 8086 has two hardware interrupt pins, i.e. NMI and INTR.
 NMI is a non-maskable interrupt and INTR is a maskable interrupt having lower priority.

Arithmetic Pipeline and Instruction Pipeline

1. Arithmetic Pipeline :
 An arithmetic pipeline divides an arithmetic problem into various sub problems for
execution in various pipeline segments.
 It is used for floating point operations, multiplication and various other computations.
 The process or flowchart arithmetic pipeline for floating point addition is shown in the
diagram.
 Floating point addition using arithmetic pipeline :

The following sub operations are performed in this case:

1. Compare the exponents.
2. Align the mantissas.
3. Add or subtract the mantissas.
4. Normalise the result

First of all the two exponents are compared and the larger of two exponents is chosen as the result exponent.
The difference in the exponents then decides how many times we must shift the smaller exponent to the right.
Then after shifting of exponent, both the mantissas get aligned. Finally the addition of both numbers take place
followed by normalisation of the result in the last segment.
Example:
Let us consider two numbers,
X=0.3214*10^3 and Y=0.4500*10^2
Explanation:
First of all the two exponents are subtracted to give 3-2=1. Thus 3 becomes the exponent of result and the
smaller exponent is shifted 1 times to the right to give
Y=0.0450*10^3
Finally the two numbers are added to produce
Z=0.3664*10^3
As the result is already normalized the result remains the same.
2. Instruction Pipeline :
 In this a stream of instructions can be executed by overlapping fetch, decode and
execute phases of an instruction cycle.
 This type of technique is used to increase the throughput of the computer system.
 An instruction pipeline reads instruction from the memory while previous instructions
are being executed in other segments of the pipeline.
 Thus we can execute multiple instructions simultaneously. The pipeline will be more
efficient if the instruction cycle is divided into segments of equal duration.

In the most general case computer needs to process each instruction in following sequence of steps:
1. Fetch the instruction from memory (FI)
2. Decode the instruction (DA)
3. Calculate the effective address
4. Fetch the operands from memory (FO)
5. Execute the instruction (EX)
6. Store the result in the proper place
7. The flowchart for instruction pipeline is shown below.
8.
9.

Let us see an example of instruction pipeline.

10. Example:
11. Here the instruction is fetched on first clock cycle in segment 1.
Now it is decoded in next clock cycle, then operands are fetched and finally the instruction is executed.
We can see that here the fetch and decode phase overlap due to pipelining. By the time the first
instruction is being decoded, next instruction is fetched by the pipeline.
12. In case of third instruction we see that it is a branched instruction. Here when it is being decoded 4th
instruction is fetched simultaneously. But as it is a branched instruction it may point to some other
instruction when it is decoded. Thus fourth instruction is kept on hold until the branched instruction is
executed. When it gets executed then the fourth instruction is copied back and the other phases
continue as usual.