EE3018 EMBEDDED PROCESSORS

UNIT I ARM ARCHITECTURE

6

Architecture – Memory Organization – addressing modes -

Registers – Pipeline - Interrupts – Coprocessors – Interrupt
Structure

Advanced RISC Machine or Acorn RISC Machine is the architecture with

different computing architectures set to be used in different environments.
32-bit and 64-bit can be used here in different computer processors. It was
developed by Arm Holdings and the architecture is updated in between.
This architecture is specified to be used with CPU, different chips in the
system, and in different registers. Smartphones, microcomputers, and
embedded devices also use ARM architecture for the instruction set in the
registers.

Many Arm-based devices are used all over the world and are one of the
popular architectures within the devices. The architecture can be divided
into A, R, and M profiles.

A profile is for applications- It helps to maintain high performance and is

designed to run the complex system in Linux or Windows.

R profile is for real-time- R profile checks for systems with real-time

requirements and is found in networking equipment or embedded control
systems.

M profile is for Microcontroller. M profile is used in IOT devices and can be

synchronized with small and high-power devices.

What is ARM Processor?

ARM Processors derive their name from the acronym "Advanced RISC
Machines," signifying their connection to the broader family of CPUs that
adhere to the RISC architecture. In essence, Advanced RISC Machines
have laid the foundation for the architecture of ARM processors, giving
them their distinctive name.

The hallmark of ARM processors lies in their

 architectural simplicity
 compact size
  reduced complexity. This inherent simplicity allows for optimal
performance when integrated into a system, delivering high levels
of efficiency.

ARM Processor Architecture

The ARM processor architecture is a family of RISC (Reduced Instruction

Set Computing) processors developed by ARM Holdings. It is characterized
by its energy efficiency, performance, and scalability, making it a popular
choice in a wide range of devices and applications.

The key features of the ARM processor architecture include:

 Instruction Set Architecture (ISA): ARM processors use a 32-bit or

64-bit instruction set architecture, depending on the specific version. The
ISA defines the supported instructions, addressing modes, and registers.

 RISC Design: ARM processors follow the RISC design philosophy, which
emphasizes simplicity and efficiency. They have a streamlined instruction
set with fixed-length instructions, a large set of general-purpose registers,
and a load/store architecture.

 Thumb Instruction Set: The Thumb instruction set is an extension of

ARM architecture that uses 16-bit instructions instead of 32-bit
instructions. It provides improved code density and is commonly used in
memory constrained systems.

 ARM and Thumb-2 Interworking:

ARM processors support a feature called ARM and Thumb-2 interworking,

which allows seamless switching between ARM and Thumb instructions
during runtime. This provides flexibility in code optimization and
execution.

 Multiple Execution Modes:

ARM processors have different execution modes, including User mode,

Supervisor mode, Interrupt mode, and System mode. Each mode has its
own set of privileges and access rights, enabling secure and controlled
execution of software.

 Coprocessors: ARM processors support coprocessors, which are

specialized hardware units that assist in executing specific tasks such as
floating-point operations or digital signal processing. These coprocessors
can be integrated directly into the processor core or implemented as
separate modules.

 SIMD (Single Instruction, Multiple Data) Extensions: Some ARM

processors feature SIMD extensions, such as the NEON technology, which
allows parallel processing of multiple data elements. This is particularly
useful for multimedia and signal processing applications.

 TrustZone: TrustZone is a security feature available in ARM processors

that enables hardware-based isolation between secure and non-secure
environments. It allows for the secure execution of sensitive tasks and
protects critical data.

 Power Efficiency: ARM processors are known for their energy

efficiency, consuming lower power compared to other processor
architectures. This makes them suitable for battery-powered devices and
systems with strict power constraints.

ARM Architecture Versions

• ARM means Advanced RISC Machines. ARM machines have a 32-bit

Reduced instruction Set Computer (RISC) Load Store Architecture. It is
first RISC microprocessor for commercial use and market-leader for low
power and cost-sensitive embedded applications.

• The processor originated in England in 1984.

• The ARM is a Von Neumann, load/store architecture i.e. only 32-bit data
bus for both instruction and data. Also for the load/store instruction access
memory.

• First models had only a 26-bit program counter, limiting the memory
space to 64 MB.

• In 1990, the research section of Acorn separated from the parent

company and formed : Advanced RISC Machines Limited.

• The ARM is a 32-bit architecture. When used in relation to the ARM :

1. Byte means 8 bits

2. Halfword means 16 bits.

3. Word means 32 bits.

• Most ARM's implement two instruction sets

1. 32-bit ARM Instruction Set

2. 16-bit Thumb Instruction Set

• Memory is addressed as a 32 bit address space. Data type can be 8 bit

bytes, 16 bit half-words or 32 bit words and may be seen as a byte line

folded into 4-byte words.

 ARM Architecture
• The ARM architecture processor is an advanced reduced instruction set
computing [RISC] machine and it's a 32 bit RISC microcontroller.

• The ARM cortex is a complicated microcontroller within the ARM family

that has ARMv7 design. There are 3 sub families within the ARM cortex
family:

a) ARM Cortex Ax-series

b) ARM Cortex Rx-series

c) ARM Cortex Mx-series

• The ARM Architecture consists of following:

a) Arithmetic Logic Unit

b) Booth multiplier

c) Barrel shifter

d) Control unit

e) Register file
• The ARM processor co jointly has other components like the Program
status register, which contains the processor flags (Z, S, V and C).

• The modes bits conjointly exist within the program standing register, in
addition to the interrupt and quick interrupt disable bits;

Some special registers: Some registers are used like the instruction,
memory data read and write registers and memory address register.

[Link] encoder: The encoder is used in the multiple load and store
instruction to point which register within the register file to be loaded or
kept. Priority encoders help to load the instruction and to store it in the
specified register in order to manage the files. This helps to identify the
registers and instructions easily in the architecture.
2. Multiplexers: Several multiplexers are accustomed to the management
operation of the processor buses.

3. Arithmetic Logic Unit (ALU): The ALU has two 32-bits inputs. The
primary comes from the register file, whereas the other comes from the
shifter. Status registers flags modified by the ALU outputs. The V-bit
output goes to the V flag as well as the Count goes to the C flag. Whereas
the foremost significant bit really represents the S flag, the ALU output
operation is done by NOR ed to get the Z flag. The ALU has a 4-bit
function bus that permits up to 16 opcodes to be implemented. 32-bit
inputs are used in Arithmetic and Logic Unit which comes from register
files and shifter. The outputs are modified in register flags. There are C
flag, V flag, S flag and Z flag. 16 opcodes can be implemented with the
help of 4-bit function bus in the microprocessor. V-bit output goes to the V
flag and C output to the C flag and so on.

4. Booth multiplier factor: The multiplier factor has 3 32-bit inputs and the
inputs return from the register file. The multiplier output is barely 32-Least
Significant Bits of the merchandise. The entity representation of the
multiplier factor is shown in the above block diagram. The multiplication
starts whenever the beginning 04 input goes active. Fin of the output goes
high when finishing.

5. Barrel shifter: The barrel shifter features a 32-bit input to be shifted.

This input is coming back from the register file or it might be immediate
data.

The shifter has different control inputs coming back from the instruction
register. The Shift field within the instruction controls the operation of the
barrel shifter. This field indicates the kind of shift to be performed. The
quantity by which the register thought to be shifted is contained in an
immediate field within the instruction or it might be the lower 6 bits of a
register within the register file.

6. Control unit: The control unit is sometimes a pure combinational circuit

design. Here, the control unit is implemented by easy state machine. The
processor timing is additionally included within the control unit. Signals
from the control unit are connected to each component within the
processor to supervise its operation.

7. Incremented:

• For load and store instructions, the incremented updates the contents of
the address register before the processor core reads or writes the next
register value from or to the consecutive memory location.
• The processor core continues the execution of instruction. Only when an
exception or interrupt occurs, the normal execution flow is changed.

8. Address Register: This holds the address generated by the load and
store instructions and places it on the address bus.

9. Instruction decoder: It decodes the instruction opcode read from the

memory and then the instruction is executed.

[Link] file : This is a bank of 32-bit registers used for storing data
items.

Features of ARM Processor

As mentioned earlier, ARM processors are built upon the principles of RISC
architecture. Consequently, they incorporate essential characteristics associated
with RISC architecture, which encompass the following:
1. Instruction Set: ARM processors employ 32-bit instructions, enabling the
fetching of each instruction in a single cycle, simplifying operations. Fixed-
length instructions allow for the fetching of future instructions while previous
ones are being executed. In contrast, CISC architecture lacks this feature, with
variable-sized instructions requiring multiple cycles for execution. ARM
processors excel in straightforward instruction decoding.
2. Register Architecture: RISC machines feature expansive, uniform register
files. With 37 registers, each 32 bits in size, only 16 can be utilized at a given
time. Unlike CISC processors, where registers have specific dedicated purposes,
RISC allows any register to hold either data or an address. This enhances the
overall execution process of the system.
3. Pipelining: ARM processors adopt a three-stage pipelining approach that
maximizes throughput. In this setup, while the first instruction is being
executed, the subsequent one is being decoded, and the next-to-next instruction
is being fetched. This simultaneous fetching, decoding, and execution enable
progress of one step per cycle, saving time. Consequently, ARM processors do
not require micro codes for instruction execution, as seen in CISC processors.
4. Load/Store Model: ARM architecture follows a load/store model, where all
operations occur within registers. Data is loaded from memory into registers
using load operations, and operations are performed on that data. Once the
operation is completed, the resulting data is stored back into memory. Unlike
CISC processors, which support memory-based operations, ARM processors do
not allow direct processing on memory.
 ARM Instruction Sets
Below are some various ARM Instruction Sets:
[Link] Instruction
Branch instructions in ARM processors cause an immediate switch in execution
to a specified address location. When a branch (B) instruction is encountered,
the processor seamlessly transitions to the designated location and proceeds to
execute the operation from there. These instructions facilitate both forward and
backward branches, allowing for branching within a range of up to 32 MB.
[Link] Processing instructions
The various data processing instructions occur within the general-purpose
registers. These instructions include:
 Arithmetic and logic instructions: These instructions serve the purpose of
executing diverse arithmetic and logic operations. They typically involve two
source operands, and the resulting output is stored in a designated destination
register. Notably, the outcomes of these instructions can be directly written into
the Program Counter, which functions as a versatile register.
 Comparison instructions: Similar in format to arithmetic and logic
instructions, comparison instructions facilitate comparisons between two
operands. However, instead of storing the results in registers, these instructions
update the contents of flag registers.
 Multiply instructions: These instructions are categorized based on the
length of the resulting bits after multiplication:
 32-bit result: This category represents normal multiplication results, where
all 32 bits of the product are stored within a single register.
 64-bit result: These instructions produce longer results that span 64 bits.
Storing the entire 64-bit value requires the use of two separate registers.
 Count leading zero instruction: With this instruction, the device counts the
number of consecutive leading zeros in a given sequence, starting from the
Most Significant Bit (MSB) to the Least Significant Bit (LSB). The count
obtained from this operation is then stored within a register.
Load and Store Instruction
These Instructions are as follows:
Load and Store register: The load register instruction enables the loading of 8-
bit, 16-bit, or 32-bit data from memory into a register. Conversely, the store
register instruction facilitates the transfer of data from a register to memory.
Load and Store multiple registers: This instruction provides the capability to
load or store multiple general purpose registers as a block from or to memory. It
supports various addressing modes, including pre-increment, post-increment,
pre-decrement, and post-decrement.
Swap register and memory content: The swap (SWP) instruction functions
sequentially in the following manner:
 Loading a value from a specified memory location into a register.
 Storing the current content of the register into the same memory location.
 Simultaneously, the loaded value from memory is stored back into the
register.
By maintaining the same register for both steps, the data within the register and
memory location are interchanged.
Status Register Transfer Instruction
This instruction enables the transfer of the current program status registers
content to or from a general-purpose register. It involves the following steps:
 Setting the value of the condition code flag.
 Configuring the interrupt enables bits.
 Establishing the processor mode.
Applications of ARM Processor
ARM processors have found widespread application across various industries
and devices. Some notable applications of ARM processors include:
Mobile Devices: ARM processors have gained significant popularity in
smartphones, tablets, and wearable devices due to their power efficiency,
compact size, and strong performance capabilities. They are widely used in
devices running operating systems like Android and iOS.
Embedded Systems: ARM processors are extensively used in embedded
systems, such as automotive electronics, industrial automation, smart
appliances, and IoT devices. Their low power consumption, scalability, and real-
time processing capabilities make them well-suited for these applications.
Consumer Electronics: ARM processors are found in a range of consumer
electronic devices like digital cameras, gaming consoles, set-top boxes, and
smart TVs. Their ability to handle multimedia processing, graphics rendering,
and connectivity features makes them ideal for delivering rich user experiences.
Automotive Systems: ARM processors play a crucial role in automotive
systems, powering functions such as engine control units (ECUs), infotainment
systems, driver assistance systems, and telematics. They offer the necessary
performance, safety features, and reliability for automotive applications.
Networking and Communication: ARM processors are used in networking
equipment such as routers, switches, and wireless access points. Their high-
speed data processing capabilities, support for networking protocols, and low
power consumption make them suitable for networking and communication
infrastructure.
Healthcare Devices: ARM processors find applications in medical devices,
such as patient monitoring systems, diagnostic equipment, and portable medical
devices. Their low power consumption, real-time processing, and integration
with sensor technologies enable advanced healthcare solutions.
Server and Data Centers: ARM processors are increasingly being adopted in
server and data center environments. Their energy efficiency and scalable
architecture make them attractive for handling large-scale data processing,
cloud computing, and virtualization.

ARM Memory Organization

The Cortex-M3 and Cortex-M4 have a predefined memory map.
This allows the built-in peripherals, such as the interrupt
controller and the debug components, to be accessed by simple
memory access instructions. Thus, most system features are
accessible in program code. The predefined memory map also
allows the Cortex-M3 processor to be highly optimized for
speed and ease of integration in system-on-a-chip (SoC)
designs.
Overall, the 4 GB memory space can be divided into ranges as
shown in picture below. The Cortex-M3 design has an internal
bus infrastructure optimized for this memory usage.
A graphical representation of the ARM memory is shown in
picture below :

The ARM Cortex-M3 memory is divided into following regions :

[Link] - .
[Link] Peripheral Bus - External - Provides access to :
 the Trace Port Interface Unit (TPIU),
 the Embedded Trace Macrocell (ETM),
 the ROM table,
 implementation-specific areas of the PPB memory map.
Private Peripheral Bus - External - Provides access to :
 the Instrumentation Trace Macrocell (ITM),
 the Data Watchpoint and Trace (DWT),
 the Flashpatch and Breakpoint (FPB),
 the System Control Space (SCS), including the MPU and the Nested Vectored
Interrupt Controller (NVIC).
External Device - This region is used for external device memory.
External RAM - This region is used for data.
Peripheral - This region includes bit band and bit band alias areas.
 Peripheral Bit-band alias - Direct accesses to this memory range behave
as peripheral memory accesses, but this region is also bit addressable
through bit-band alias.
 Peripheral bit-band region - Data accesses to this region are remapped to
bit band region. A write operation is performed as read-modify-write.
SRAM - This executable region is for data storage. Code can also be stored
here. This regionincludes bit band and bit band alias areas.
 SRAM Bit-band alias - Direct accesses to this memory range behave as
SRAM memory accesses, but this region is also bit addressable through
bit-band alias.
 SRAM bit-band region - Data accesses to this region are remapped to bit
band region. A write operation is performed as read-modify-write.
Code - This executable region is for program code. Data can also be stored
here.
Addressing Modes in ARM
The phrase addressing modes in ARM relates to the manner an instruction
operand is expressed. Before the operand is actually performed, the addressing
mode provides a rule for interpreting or altering the address field of the
instruction.
Data Processing Operand (i.e. op1) Addressing Modes
There are two approaches to dealing with these operands.

Unaltered value :The register or a value is delivered unchanged, that is,

without any shift or rotation, in this addressing style, for example,
I MOV R0, # 1234 H The instantaneous constant value 1234 will be moved
into register R0 by this instruction.
Modified value :The provided value or register is shifted or rotated in this
addressing mode. As shown below with examples, there are several shift and
rotate operations that may be performed.
(1)(Leftward logical shift :This will move the value of a register by n bits in
the direction of the most significant bits
For ex:
MOV R0, R1, LSL #2 R0 will become the value of R1 shifted 2 bits
once this instruction is executed.
(2)Right logical shift This shifts the value of a register by n bits to the right.
EX:
MOV R0, R1, LSR R2 R0 will have the value of R1 moved right by
R2 times once this instruction is executed. R1 and R2 are unaffected.
(3) Right arithmetic shift This is identical to logical shift right, except that
for arithmetic shift operations, the MSB is maintained as well as shifted,
Ex:

MOV R0, R1, ASR #2. R0 will have the value of R1 Arithmetic; moved
right by 2 bits after this instruction is executed.
(4) Rotate to the right. This will rotate the value of a register by n bits,
ex:
MOV R0, R1, ROR R2. R0 will have the value of R1 rotated right
for R2 times once this instruction is executed.
(5) Extend right rotation This is comparable to Rotate right by one bit with the
carry flag put into the MSB, The value of register R1 will be rotated right
through carry by 1 bit once this instruction is executed.
Addressing Modes for Memory Access Operand
To access memory, load and store instructions are utilised, as previously
mentioned. The various memory
access addressing modes are as follows:
(i) Register indirect addressing mode
(ii) Indirect addressing mode for relative registers
(iIi) Indirect addressing method with a base index
(iv) Scale register addressing mode as a base
As demonstrated in the examples for each addressing method, offset addressing,
pre-index addressing, and post index addressing are all available.
(i) Register indirect addressing mode
A register is utilised in this addressing mechanism to provide the address of the
memory region to be accessed.
LDR R0, [R1] is an example. This instruction loads the 32-bit word at the
memory location contained in register R0 into register R0.
(ii) Indirect addressing mode for relative registers
An instantaneous value applied to a register generates the memory address in
this addressing style. This method of addressing allows for both pre- and post-
indexing.
For example, (a) LDR R0, [R1, #4]
This instruction loads the register R0 with the word at the memory regions
computed by adding the constant address included in the R1 register value 4 to
the memory address stored in the R1 register,
e.g. (b) LDR R0, [R1, #4]!
This is a type of addressing that comes before the index. This instruction is the
same as (a) in that it sets the new address in R1, i.e. R1 (R1 + 4).
e.g. (c)’LDR, [R1], #4
This is referred to as post-index addressing. This instruction loads the word at
the memory location supplied in register R1 into register R0. It will then
compute the new address by multiplying R1 by 4 and storing it in R1.
(ii) Indirect addressing method with a base index
The memory address is produced by adding the values of two registers in this
addressing scheme.. For example,
(a) LDR R0, [R1, R2]
Pre indexing and post indexing is also supported.
This instruction will load the word at the memory address determined by adding
register R1 and register R2 into register R0.
For example,
(b) LDR R0, [R1, R2]! This is pre-index addressing.
This instruction loads the word at the memory location supplied in register R1
into register R0. The new address will then be calculated by adding the value in
register R2 to register R1 and placed in R1.
(iii) Scaled register addressing mode as a base
The memory address is produced by adding a register value to another register
that is moved left in this addressing scheme. This addressing technique allows
for pre-indexing and post-indexing.
For ex: (a) LDR R0, [R1, R2, LSL #2]
The word at the memory location computed by adding register leith register R2
shifted left by 2 bits will be loaded into register R0 using this command. For
instance, (b) LDR RO,[R1, R2, LSL #2]!
ARM Registers
Basically there are two types of registers –
General purpose registers and Special purpose registers.
General purpose registers hold either data or an address. The letter r is prefixed
to the register number to identify them. For example, the label r4 is assigned to
register 4. Figure depicts the active registers that are available in user mode,
which is a protected state that is often utilized for running programmes. There
are seven various modes that the CPU may work in, which we shall go through
momentarily. The registers in this example are all 32 bits in size. Up to 18 active
registers are available: 16 data registers and 2 processor status registers. The
data registers are labeled r0 through r15 by the programmer. The ARM
processor contains three registers: r13, r14, and r15, each of which is allocated
to a specific duty or unique function. To distinguish them from the other
registers, they are typically given separate labels. The coloured registers
indicate which special-purpose registers have been allocated.
 Register 13 is traditionally used as the stack pointer (SP) and stores the head
of the stack in the current processor mode.
 Register r14 is called the link register (LR) and is where the core puts the
return address whenever it calls a subroutine.
 Register 15 is the program counter (PC) and contains the address of the next
instruction to be fetched by the processor.
Few of these registers are actually banked and different registers are available
for different processor modes.
SP ( Stack Pointer )
 The stack pointer, often known as the SP register, is located in register r13.
 Each exception mode has its own version of r13, pointing to a stack
specialised to that mode.
 Temporary values are stored in the stack.
LR ( The link register )
 The Link register, also known as register r14, is used to store the subroutine’s
return address.
 When an exception occurs, the version of r14 in the exception mode is set to
the address after the instruction is executed.
 SPSR is a copy of the CPSR just before an exception has occurred.
PC ( Program Counter )
 The Program Counter, sometimes known as the PC, is located in register r15.
 It’s used to determine which instruction will be executed next.
 The PC is referred to as an instruction pointer because it stores the address of
the next instruction.
CPSR (Current Processor Status Register )
•Current processor status register (CPSR) contains the current status of the
processor.
•This includes various conditional code flags, Interrupt Status Processor mode
and other status and control information.
•The exception modes also have a saved processor status register (SPSR), that is
used to preserve the value of CPSR when the associated exception occurs.
•Because the User and System modes are not exception modes, there is no
SPSR available.
SPSR (Saved Processor Status Register)
In the exception modes there is an additional Saved Processor Status register
(SPSR) which holds information on the processor’s state before the system
changed into this mode i.e. the processor status just before an exception.
ARM Pipelining
Pipelining is a design method or procedure that improves the efficiency of data
processing in computer and microcontroller processors. By keeping the CPU in
a continuous fetching, decoding, and execution process known as (the F&E
cycle).
 RISC (Reduced instruction set computer) employs a pipelining approach to
execute instructions. Pipelining in ARM boosts execution speed.
 by retrieving the instruction and executing it while other instructions are
being decoded and executed at the same time.
 As a result, the memory system and CPU can run continually.
 Each ARM family has a distinct pipeline architecture.
3-s pipeline is the mechanism a RISC processor uses to execute instructions.
Using a pipeline speeds up execution by fetching the next instruction while
other instructions are being decoded and executed. One way to view the
pipeline is to think of it as an automobile assembly line, with each stage
carrying out a particular task to manufacture the vehicle.
3-Stage Pipelining Schematic
 Fetch retrieves a memory instruction.
 Decode identifies the to-be-executed instruction.
 The instruction is processed by Execute, and the result is written back to the
register.
 The speed of execution is boosted by overlapping the aforementioned steps of
execution of various instructions.
 The pipelining technique allows the core to execute an instruction once every
cycle, resulting in higher throughput

The figure illustrates the pipeline using a simple example.

It shows a sequence of three instructions being fetched, decoded, and executed
by the processor. Each instruction takes a single cycle to complete after the
pipeline is filled. The three instructions are placed into the pipeline sequentially.
In the first cycle the core fetches the ADD instruction from memory. In the
second cycle the core fetches the SUB instruction and decodes the ADD
instruction. In the third cycle, both the SUB and ADD instructions are moved
along the pipeline. The ADD instruction is executed, the SUB instruction is
decoded, and the CMP instruction is fetched. This procedure is called filling the
pipeline. The pipeline allows the core to execute an instruction every cycle. As
the pipeline length increases, the amount of work done at each stage is reduced,
which allows the processor to attain a higher operating frequency. This in turn
increases the performance. The system latency also increases because it takes
more cycles to fill the pipeline before the core can execute an instruction. The
increased pipeline length also means there can be data dependency between
certain stages. You can write code to reduce this dependency by using
instruction scheduling.
It has the ability to finish its procedure in three cycles.
 It utilises the fundamental F&E cycle to achieve maximum throughput.
 This is why, when compared to its other family members, the ARM 7 has the
lowest throughput.
 It works with 32-bit data.
ARM7 Pipeline Characteristics
 An instruction in the ARM pipeline is not processed until it has completed the
execution step.
 The PC always refers to the instruction address Plus 8 bytes throughout the
execution step.
 PC always refers to the instruction address Plus 4 bytes when the processor is
in thumb state.
 The ARM core flushes its pipeline when executing branch instructions or
branching via direct change of the PC.
 Even if an interrupt has been raised, an instruction in the execution stage will
finish its execution.
5-Stage Pipelining
3 stage pipeline vs 5 stage pipeline
The pipeline design for each ARM family differs. For example, The ARM9 core
increases the pipeline length to five stages. The ARM9 adds a memory and
writeback stage, which allows the ARM9 to process on average 1.1 Dhrystone
MIPS per MHz—an increase in instruction throughput by around 13%
compared with an ARM7. The maximum core frequency attainable using an
ARM9 is also higher.

ARM9 five stage pipeline

pipelining in ARM
 Pipelining is similar to ARM 7, however there are five phases in ARM 9.
 The procedure takes 5 cycles to finish.
 Pipelining in 5 stages
 It will fetch instructions from memory using the fetch command.
 Decode- It decodes the instructions acquired in the previous cycle.
 ALU – This step performs the instruction that was previously decoded.
 LS1 (Memory) loads/stores data given by load/store instructions.
 LS2(Write) extracts (zero or sign) data loaded by byte or half word load
instruction and extends it.
 The throughput is 10 percent to 13 percent greater than ARM 7 due to an
improvement in phases and
efficiency.
 The ARM 9 core frequency is somewhat higher than the ARM 7 core
frequency.
Interrupts on ARM
Most processor families have a mechanism to handle “hardware interrupts”. The
ARM Cortex series is no exception – it has surprisingly sophisticated support
for them, in fact. But first: what is an interrupt?
You can think of a µC / CPU as performing the following task, millions of times
per second:
 fetch the next instruction from memory
 advance the instruction pointer
 perform whatever that instruction says
 rinse and repeat
This is all nice and great, but it completely ignores the outside world. If this was
all we had, then we’d have to constantly check all the hardware peripherals
whether there is anything we need to take care of: serial input or output, some
amount of clock time has passed, a digital or analog pin change, etc. Given the
many possible sources of occasional work, we’d be wasting our time checking
up on all that. With fast I/O, we’d have to check very often!
Here’s what an interrupt-aware CPU does instead:
 if there’s an interrupt event, process it
 fetch the next instruction from memory
 advance the instruction pointer
 perform whatever that instruction says
 rinse and repeat
So in a way, interrupts are nothing but lots of checking, done in hardware. At
the start of every new instruction, the processor does the checking for us.
Except that now, it’s virtually instant (and free): all the interrupt signals are OR-
ed together to generate a single logic level – when set, there’s an interrupt
“pending”, and the processor will divert its attention.
A couple of key points here:
 interrupts happen only between instructions
 interrupts can happen between any two instructions
 interrupts add overhead, but only when they actually happen
It seems so simple, but as you will see later on, this can cause all sorts of
trouble.
An important note in the context of embedded microcontrollers: hardware
interrupts are also essential for “waking up” a µC when it’s in some low-power /
power-down mode.
The stack
What a processor needs to do to process – or “service” – an interrupt is not
trivial: it was doing something, with all sorts of context in its registers. And now
it needs to somehow suspend that work, take care of the interrupt, and then
resume what it was doing before.
To further complicate this: we’d like to be able to write the interrupt code
(Interrupt Service Routine, or ISR) in a higher-level language such as C or C++,
not just assembly. This is where the hardware stack plays an essential role:
when an interrupt is about to be serviced, all the state of the processor (i.e. its
registers, including the instruction pointer) are pushed onto the stack, the
instruction pointer is changed to the address of the ISR code, and then… the
above loop is simply resumed!
The effect is that all of a sudden, the CPU starts running the ISR code. At the
end of that code is a special “return from interrupt” instruction, which pops all
the saved registers from the stack, and then again resumes the above loop.
We’re back where we were before! There are several clever optimisations for
this important mechanism on ARM, such as not saving all the registers and
automatically restoring registers on return. This allows ARM chips to efficiently
support C/C++ code without any special interrupt entry/exit instructions. But
the essential model and mechanism remains unaffected, Each interrupt routine
eats up some stack space when started and gives it back when done.

Interrupt vectors
Hardware interrupts can be used for lots of different purposes. Some interrupts
might occur extremely often (many tens of thousands of times per second) – in
the case of fast peripherals, such as SPI, or a serial port set to a very high baud
rate. This in itself is fine, but we need to be careful with overhead. Interrupts
“eat away” processor time from the main processing task – if we’re not careful,
we could end up consuming more time than the processor has (and cause it to
totally lock up).
Then again, some interrupts are very infrequent, at least on a µC’s MHz
performance scale. The solution to get high performance is called “interrupt
vectoring” and causes each type of interrupt to jump to a different ISR. The first
words in flash memory are reserved precisely for this purpose, and are normally
set up to hold the addresses of each of the ISRs. This means that when any
specific ISR is called, it will know exactly what just happened and can do
whatever is needed (i.e. copy some data in or out), to then return quickly.
ARM COPROCESSORS
Coprocessors can be attached to the ARM processor. A coprocessor extends the
processing features of a core by extending the instruction set or by providing
configuration registers. More than one coprocessor can be added to the ARM
core via the coprocessor interface.
The coprocessor can be accessed through a group of dedicated ARM
instructions that provide a load-store type interface. Consider, for example,
coprocessor 15: The ARM processor uses coprocessor 15 registers to control the
cache, TCMs, and memory management. The coprocessor can also extend the
instruction set by providing a specialized group of new instructions. For
example, there are a set of specialized instructions that can be added to the
standard ARM instruction set to process vector floating-point (VFP) operations.
These new instructions are processed in the decode stage of the ARM pipeline.
If the decode stage sees a coprocessor instruction, then it offers it to the relevant
coprocessor. But if the coprocessor is not present or doesn't recognize the
instruction, then the ARM takes an undefined instruction exception, which
allows you to emulate the behavior of the coprocessor in software.

Coprocessor-only model
The MPI coprocessor-only or native model has the MPI processes launched and
residing solely on the coprocessor. MPI libraries, the application, and other
needed libraries are uploaded to the coprocessors. Then an application can be
launched from the host or from the coprocessor. Once the application is running,
MPI network communications between other coprocessors (either on the local
node or to other network fabric connected nodes) are managed by the Intel®
Coprocessor Communications Link (Intel® CCL) services. Intel CCL provides
underlying services to the MPI library to select the optimal transport for MPI
messages. One such Intel CCL transport mechanism is the peer-to-peer PCI
Express DMA support described in Chapter 8 to directly transfer message data
between the coprocessor’s memory and a peer InfiniBand (IB) adapter without
host memory staging. Figure 9.5 illustrates the MPI Coprocessor-Only model.
More details on the structure and components of Intel CCL are described later in
this chapter.

Coprocessor Interface
The Armv8 architecture also includes a coprocessor interface designed to allow
the integration of hardware accelerators that extend the compute capabilities of
the Cortex-M processor. The coprocessors are not peripherals in that they do not
provide an interface to the external World like an ADC. Typically, the
coprocessor will be an accelerator for specific algorithms such as a DSP or
cryptographic accelerator. Each coprocessor is tightly coupled to the Cortex-M
processor to provide a low latency interface. Dedicated single cycle instructions
are used to move 32- or 64-bit data to and from the Cortex-M processor
registers. The Armv8-M architecture provides control and data channels for up
to eight separate coprocessors with an addressing scheme shown in Table 7.4
When an Armv8-M-based microcontroller is fitted with a coprocessor, the
silicon vendor will typically provide a supporting library of functions that are
used to access the coprocessor features. For example, the NXP lpc55s69 is a
Cortex-M33-based microcontroller that includes a cryptographic coprocessor
and a DSP coprocessor. Both are supported by vendor libraries so you don’t
need to do any low-level code development.
ARM Interrupt Structure
A collection of reduced instruction set computer (RISC) instruction set
architectures for computer processors that are tailored for different contexts is
known as ARM (stylized in lowercase as an arm; originally an abbreviation for
Advanced RISC Machines. System-on-a-chip (SoC) and system-on-module
(SOM) designs, which combine various components including memory,
interfaces, and radios, are examples of devices that other firms design and
manufacture using one or more of the architectures that ARM Ltd. develops and
licenses. Additionally, it develops cores that use these instruction set
architectures and licenses these designs to a large number of businesses, who
then use them to create their own products.
The ARM design has gone through multiple iterations. The original ARM1
featured a 32-bit internal structure but only supported 64 MB of main memory
due to its 26-bit address space. The ARMv3 series, which has a 32-bit address
space, abolished this restriction, while subsequent generations up to ARMv7
maintained this constraint. With its new 32-bit fixed-length instruction set, the
2011-released ARMv8-A architecture gained capability for 64-bit address space
and 64-bit arithmetic. Arm Ltd. also released a number of additional instruction
sets for various rules. Simultaneous multithreading (SMT) has been added more
recently for fault tolerance or improved performance.
For light, portable, battery-powered devices like smartphones, laptops, and
tablet computers, as well as other embedded systems, ARM processors are
preferred because they are less expensive, consume less power, and generate
less heat than their competitors. However, ARM processors are widely
employed in servers and desktop computers, notably Fukuku, which will hold
the record for the fastest supercomputer from 2020 until 2022. As of 2022,
ARM will have created over 230 billion ARM chips, making it the most popular
and most abundant family of instruction set architectures (ISA). To include or
exclude optional capabilities, there are currently variants of the popular Cortex
cores, older “classic” cores, and specialized SecurCore cores available for each
of these.
Structure of ARM interrupt:
The following points help us in understanding the structure of ARM interrupt: 
 All interrupts are disabled on startup for the ARM CPU until the
initialization code turns them on. The Processor Status Registers’ bit can be
changed to enable or disable the interrupts (PSR or CPSR where C stands
for current). The CPSR also determines whether the processor is decoding
Thumb instructions and the processor mode (SVC, System, User, etc.). The
application can read and write to the CPSR in its entirety when operating in
privileged mode, but it can only read the CPSR when operating in non
privileged mode. The processor enters the appropriate interrupt or exception
mode in response to an interrupt or exception, which causes a portion of the
main registers to be banked, swapped out, or replaced with set mode
registers. 
 The interrupt masks’ ability to be enabled and disabled is controlled by bits.
The two interrupt inputs on the ARM processor can both be regarded as
general-purpose interrupts. Interrupt Request (IRQ) and Fast Interrupt
Request are the names of the first and second, respectively (FIQ) 
 The regular sequential execution of instructions can be stopped by one of
seven events on the ARM processor. Since not all events are created equal,
the processor must adopt a priority strategy because these events may occur
simultaneously. For instance, since it happens when the power to the ARM
processor is switched, the Reset has the highest priority. As a result, a reset
supersedes all other events when it happens. The only exception to this rule
is a Reset event, which takes precedence over all other events when a Data
Abort occurs. Since the ARM processor must recognize the event with the
highest importance when several events are happening at once, this priority
mechanism is crucial. 
 The vector table begins at 0x00000000, as was indicated in earlier chapters
(ARMx20 processors can optionally locate the vector table address to
0xffff0000). A vector table is a collection of ARM instructions that control
the computer (i.e. B, MOV, and LDR). These commands cause the computer
to jump to a certain area that can deal with a particular exception or
interrupt. Since the FIQ vector is at the end of the table, it can avoid using
the B or LDR instruction. The FIQ handler can now begin execution at the
FIQ vector point. By preventing the pipe from having to be flushed when
the PC is moved, FIQs can conserve processor cycles. 
 From an interrupt handler returning The return address from an interrupt or
execution handler must be changed because of the processor pipeline. An
offset will be present in the address that is kept in the link register. As a
result, the offset value must be deducted from the link register. 
 The interrupt stacks being set up Depending on the hardware being utilized
and the RTOS needs, the interrupt stack may be put in a different location.
The target system will crash if the Interrupt Stack extends into the Interrupt
vector. Unless a check is made on the stack’s extension and a way is
provided to deal with that problem when it happens. The IRQ mode stack
must first be set up before an interrupt may be enabled. Normally, this is
completed in the system’s initialization code. Knowing the stack’s
maximum size is crucial because it allows for the interrupt stack to be
allocated that much space. Possible memory configurations with a linear
address space are shown below. 
 Interrupt handler installation and chaining. The vector table can be fixed for
ROM and/or FlashROM based devices without the need for installation.
These systems often copy the entire vector table from ROM to RAM as a
block without the need to install individual vectors. Since memory tends to
be remapped during initialization, this method is typically employed.
Placing a vector entry for the IRQ address (0x00000018) or FIQ address
(0x0000001C) so that the entry links to the proper handler is the first step in
installing an interrupt handler. Chaining entails inserting a new entry while
saving the current vector entry. The original handler may regain control if
the newly added handler is unable to handle a certain interrupt source by
calling the saved vector entry. 
 Another interrupt may occur inside the presently called handler thanks to
nested interrupt handlers. This is accomplished by re-enabling the interrupts
 before the current interrupt has been fully handled by the handler. This
feature makes the system more complex for real-time systems. A system
failure could result from subtle timing problems introduced by this
complexity. These small issues can be very challenging to fix. In order to
prevent issues of this nature, the nested interrupt technique needs to be
carefully constructed. In order to prevent the next interrupt from filling
(overflowing) the stack or corrupting any of the registers, context restoration
is protected from interruption. 
 If nested interrupts are supported, many common issues can be seen as a
result of a rise in complexity. A race condition that results in a cascade of
interrupts is one of the key issues. The handler will experience constant
interruptions up until the point at which the interrupt stack overflows or the
registers become damaged. When designing, efficiency and safety must be
balanced. This entails writing code defensively, assuming issues will arise.
When possible, the system should examine the stack and take precautions to
prevent register corruption. 
 Multiple interrupts can be handled using a re-entrant interrupt handler,
where interruptions are prioritized. This is significant because interrupts
with a higher priority must have a smaller latency. The typically nested
interrupt handler is unable to perform this kind of filtering. Re-enabling
interrupts early on in the interrupt handler to achieve minimal interrupt
latency is the primary distinction between a re-entrant interrupt handler and
a nested interrupt handler. 
 A prioritized interrupt handler will assign a priority level to a specific
interrupt source as opposed to the simple and nested interrupt handlers,
which service interruptions on a first-come, first-served basis. The sequence
in which the interrupts are handled is determined by a priority level. A
desirable property in an embedded system is that a higher-priority interrupt
will take precedence over a lower-priority interrupt.