8085 Microprocessor

I. Introduction

BASIC CONCEPTS OF MICROPROCESSORS

Differences between: Microcomputer, Microprocessor and Microcontroller
• Microcomputer is a computer with a microprocessor as its CPU. Includes memory, I/O
etc.
• Microprocessor is a silicon chip which includes ALU, register circuits & control
circuits
• Microcontroller is a silicon chip which includes microprocessor, memory & I/O in a
single package.

WHAT IS MICRO?

Micro is a new addition. In the late 1960’s, processors were built using discrete elements. These
devices performed the required operation, but were too large and too slow. It went directly from
discrete elements to a single chip. However, comparing today’s microprocessors to the ones
built in the early 1970’s you find an extreme increase in the amount of integration.

WHAT IS A MICROPROCESSOR?

The word comes from the combination of micro and processor. Processor means a device that
processes whatever. In this context processor means a device that processes numbers,
specifically binary numbers, 0’s and 1’[Link] process means to manipulate. It is a general term
that describes all manipulation. Again in this content, it means to perform certain operations
on the numbers that depend on the microprocessor’s design. It is a programmable device that
takes in numbers, performs on them arithmetic or logical operations according to the program
stored in memory and then produces other numbers

As a Programmable device:

• The microprocessor can perform different sets of operations on the data it receives
depending on the sequence of instructions supplied in the given program.
• By changing the program, the microprocessor manipulates the data in different ways as
Instructions, Words, Bytes, etc.
• They processed information 8-bits at a time. That’s why they are called —8-bit
processors. They can handle large numbers, but in order to process these numbers, they
 broke them into 8-bit pieces and processed each group of 8-bits separately.

WHAT IS MEMORY?

Memory is the location where information is kept while not in current use. It is stored in
memory. Memory is a collection of storage devices. Usually, each storage device holds one bit.
Also, in most kinds of memory, these storage devices are grouped into groups of 8. These 8
storage locations can only be accessed together. So, one can only read or write in terms of bytes to and
from memory. Memory is usually measured by the number of bytes it can hold. It is measured
in Kilos, Megas and lately Gigas. A Kilo in computer language is 210 =1024. So, a KB
(KiloByte) is 1024 bytes. Mega is 1024 Kilos and Giga is 1024 Mega. When a program is
entered into a computer, it is stored in memory. Then as the microprocessor starts to execute
the instructions, it brings the instructions from memory one at a time. Memory is also used to
hold the [Link] microprocessor reads (brings in) the data from memory when it needs it and
writes (stores) the results into memory when it is done.

A MICROPROCESSOR-BASED SYSTEM

From the above description, we can draw the following block diagram to represent a
microprocessor-based system as shown in fig 1. In this system, the microprocessor is the master
and all other peripherals are slaves. The master controls all peripherals and initiates all
operations. The buses are group of lines that carry data, address or control signals. The CPU
interface is provided to demultiplex the multiplexed lines, to generate the chip select signals
and additional control signals. The system bus has separate lines for each signal.

All the slaves in the system are connected to the same system bus. At any time instant
communication takes place between the master and one of the slaves. All the slaves have
tristate logic and hence normally remain in high impedance state. The processor selects a slave
by sending an address. When a slave is selected, it comes to the normal logic and communicates
with the processor.

The EPROM memory is used to store permanent programs and data. The RAM memory is used
to store temporary programs and data. The input device is used to enter program, data and to
operate system. The output device is also used for examining the results. Since the speed of IO
devices does not match with speed of microprocessor, an interface device is provided between
system bus and IO device.
 Fig.1.1 Microprocessor based system (organization of microcomputer)

CENTRAL PROCESSING UNIT

The CPU consists of ALU (Arithmetic and Logic Unit), Register unit and control unit. The
CPU retrieves stored instructions and data word from memory; it also deposits processed data
in memory.

ALU (ARITHMETIC AND LOGIC UNIT)

This section performs computing functions on data. These functions are arithmetic operations
such as additions subtraction and logical operation such as AND, OR rotate etc. Result are
stored either in registers or in memory or sent to output devices.

REGISTER UNIT

It contains various register. The registers are used primarily to store data temporarily during
the execution of a program. Some of the registers are accessible to the uses through
instructions.

CONTROL UNIT

It provides necessary timing & control signals necessary to all the operations in the
microcomputer. It controls the flow of data between the p and peripherals (input, output &
memory). The control unit gets a clock which determines the speed of the p.

The CPU basic functions

 • It fetches an instructions word stored in memory.

• It determines what the instruction is telling it to do.(decodes the instruction)

• It executes the instruction. Executing the instruction may include some of the
following major tasks.
• Transfer of data from reg. to reg. in the CPU itself.
• Transfer of data between a CPU reg. & specified memory location.
• Performing arithmetic and logical operations on data from a specific memory
location or a designated CPU register.
• Directing the CPU to change a sequence of fetching instruction, if processing
the data created a specific condition.
• Performing housekeeping function within the CPU itself inorder to establish
desired condition at certain registers.
• It looks for control signal such as interrupts and provides appropriate
responses.
• It provides states, control, and timing signals that the memory and input/output
section can use.

There are three buses:

ADDRESS BUS:

It is a group of wires or lines that are used to transfer the addresses of Memory or I/O devices.
It is unidirectional. In Intel 8085 microprocessor, Address bus was of 16 bits. This means that
Microprocessor 8085 can transfer maximum 16 bit address which means it can address 65,536
different memory locations. This bus is multiplexed with 8 bit data bus. So the most significant
bits (MSB) of address goes through Address bus (A7-A0) and LSB goes through multiplexed
data bus (AD0-AD7).

DATA BUS:

Data Bus is used to transfer data within Microprocessor and Memory/Input or Output devices.
It is bidirectional as Microprocessor requires to send or receive data. The data bus also works
as address bus when multiplexed with lower order address bus. Data bus is 8 Bits long. The
word length of a processor depends on data bus, thats why Intel 8085 is called 8 bit
Microprocessor because it have an 8 bit data bus.
CONTROL BUS:

Microprocessor uses control bus to process data that is what to do with the selected memory
location. Some control signals are Read, Write and Opcode fetch etc. Various operations are
performed by microprocessor with the help of control bus. This is a dedicated bus, because all
timing signals are generated according to control signal. The microprocessor is the master,
which controls all the activities of the system. To perform a specific job or task, the
microprocessor has to execute a program stored in memory. The program consists of a set of
instructions stored in consecutive memory location. In order to execute the program the
microprocessor issues address and control signals, to fetch the instruction and data from
memory one by one. After fetching each instruction it decodes the instruction and carries out
the task specified by the instruction.

8085 MICROPROCESSOR ARCHITECTURE

FEATURES OF 8085
• 8-bit general purpose µp
• Capable of addressing 64 k of memory
• Has 40 pins as shown in fig 2
• Requires +5 v power supply
• Can operate with 3 MHz clock
• 8085 upward compatible

PIN DIAGRAM OF 8085

Figure shows 8085 pin configuration and functional 8085 Microprocessor Pin Diagram
respectively. The signals of 8085 can be classified into seven groups according to their
functions.
 Fig Pin Diagram of 8085

• Data and Address bus

❖ A8 – A15 Address bus - it carries the most significant 8-bits of memory I/O address.
❖ AD7-AD0,(Multiplexed Address/data bus).It carries the least significant 8-bit address and
data bus. These pins serve the dual purpose of transmitting lower order address and data
byte. During 1st clock cycle, these pins act as lower half of address. In remaining clock
cycles, these pins act as data bus

• Control and status signals

These signals are used to identify the nature of operation. There are 3 control signal and 3
status signals.
✓ Three control signals are RD, WR & ALE.
 ✓ RD − This signal indicates that the selected IO or memory device is to be read and is
ready for accepting data available on the data bus.

✓ WR − This signal indicates that the data on the data bus is to be written into a selected
memory or IO location.

✓ ALE − It is a positive going pulse generated when a new operation is started by the
microprocessor. When the pulse goes high, it indicates address. When the pulse goes down
it indicates data.
✓ Three status signals are IO/M, S0 & S1.

❖ S1 & S0

S0 and S1 are called Status Pins. They tell the current operation which is in progress in 8085.

❖ IO/M

This signal is used to differentiate between I/O and Memory operations, i.e.

✓ when it is high indicates I/O operation and

✓ when it is low then it indicates memory operation.

These signals are used to identify the type of current operation.

Control and Status Signals
Machine IO/M S1 S0 Control
Cycle signals
Opcode 0 1 1 RD=0
Fetch
Memory 0 1 0 RD=0
Read
Memory 0 0 1 WR=0
Write
 I/O Read 1 1 0 RD=0

I/O Write 1 0 1 WR=0

Interrupt 1 1 1 INTA=0
Acknowledge

Halt Z 0 0 RD, WR=z

and INTA=1
Hold Z X X RD, WR=z
and INTA=1
Reset Z X X RD, WR=z
and INTA=1

• Power supply
There are 2 power supply signals VCC & VSS.

❖ VCC indicates +5v power supply and

❖ VSS indicates ground signal.

• Clock signals
There are 3 clock signals, i.e. X1, X2, CLK OUT.

❖ X1, X2 − A crystal (RC, LC N/W) is connected at these two pins and is used to set
frequency of the internal clock generator. This frequency is internally divided by 2.

❖ CLK OUT − This signal is used as the system clock for devices connected with the
microprocessor.

• Interrupts & externally initiated signals

Interrupts are the signals generated by external devices to request the microprocessor to
perform a task. There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and
INTR. We will discuss interrupts in detail in interrupts section.

❖ INTA − It is an interrupt acknowledgment signal.

❖ RESET IN − This signal is used to reset the microprocessor by setting the program counter
to zero.
❖ RESET OUT − This signal is used to reset all the connected devices when the
 microprocessor is reset.
❖ READY − This signal indicates that the device is ready to send or receive data. If READY
is low, then the CPU has to wait for READY to go high.
❖ HOLD − This signal indicates that another master is requesting the use of the address and
data buses.
❖ HLDA (HOLD Acknowledge) − It indicates that the CPU has received the HOLD request
and it will relinquish the bus in the next clock cycle. HLDA is set to low after the HOLD
signal is removed.
• Serial I/O signals
There are 2 serial signals, i.e. SID and SOD and these signals are used for serial
communication.
❖ SOD (Serial output data line) − The output SOD is set/reset as specified by the SIM
instruction.
❖ SID (Serial input data line) − The data on this line is loaded into accumulator whenever a
RIM instruction is executed.
• Five Hardware Interrupts in 8085
❖ TRAP is a non-maskable interrupt
❖ RST 7.5 is an edge triggered interrupt.
❖ RST 6.5 is a maskable and level triggered interrupt
❖ RST 5.5 is a maskable and level triggered interrupt
❖ INTR is a non-vectored interrupt

ARCHITECTURE OF INTEL 8085 MICROPROCESSOR

The architecture of INTEL 8085 microprocessor is as shown in fig1.4.

THE ALU

• In addition to the arithmetic & logic circuits, the ALU includes the accumulator, which is
part of every arithmetic & logic operation.

• Also, the ALU includes a temporary register used for holding data temporarily during the
execution of the operation. This temporary register is not accessible by the programmer.
 Fig:1.4 Architecture of intel 8085 microprocessor

REGISTERS
GENERAL PURPOSE REGISTERS

• B, C, D, E, H & L (8 bit registers)

• Can be used singly
• Or can be used as 16 bit register pairs BC, DE& HL
• HL used as a data pointer (holds memory address)

ACCUMULATOR (8 BIT REGISTER)

• Store 8 bit data

• Store the result of an operation
• Store 8 bit data during I/O transfer Address
FLAG REGISTER

8 bit register – shows the status of the microprocessor before/after an operation.S (sign flag),
Z (zero flag), AC (auxillary carry flag), P (parity flag) & CY (carry flag)

D7 D6 D5 D4 D3 D2 D1 D0

S Z X AC X P X CY

SIGN FLAG
• Used for indicating the sign of the data in the accumulator
• The sign flag is set if negative (1 – negative)
• The sign flag is reset if positive (0 –positive)

ZERO FLAG
• Is set if result obtained after an operation is 0
• Is set following an increment or decrement operation of that register

CARRY FLAG
• Is set if there is a carry or borrow from arithmetic operation

AUXILLARY CARRY FLAG

• Is set if there is a carry out of bit 3

PARITY FLAG
• Is set if parity is even
• Is cleared if parity is odd

THE PROGRAM COUNTER (PC)

• This is a register that is used to control the sequencing of the execution of instructions.
• This register always holds the address of the next instruction.
• Since it holds an address, it must be 16 bits wide.

THE STACK POINTER

• The stack pointer is also a 16-bit register that is used to point into memory.
 • The memory this register points to is a special area called the stack. The stack is an
area of memory used to hold data that will be retrieved soon.

• The stack is usually accessed in a Last in First out (LIFO) fashion.

NON PROGRAMMABLE REGISTERS

Instruction Register & Decoder
• Instruction is stored in IR after fetched by processor
• Decoder decodes instruction in IR

INTERNAL CLOCK GENERATOR

• 3.125 MHz internally
• 6.25 MHz externally

THE ADDRESS AND DATA BUSSES

• The address bus has 8 signal lines A8 – A15 which are unidirectional.
• The other 8 address bits are multiplexed (time shared) with the 8 data bits.
• So, the bits AD0 – AD7 are bi-directional and serve as A0 – A7 and D0 – D7 at the
same time.
• During the xecution of the instruction, these lines carry the address bits during the
early part, then during the late parts of the execution, they carry the 8 data bits.
• In order to separate the address from the data, we can use a latch to save the value
before the function of the bits changes.

DEMULTIPLEXING AD7-AD0

• From the above description, it becomes obvious that the AD7– AD0 lines are serving
a dual purpose and that they need to be demultiplexed to get all the information.
• The high order bits of the address remain on the bus for three clock periods. However,
the low order bits remain for only one clock period and they would be lost if they are
not saved externally. Also, notice that the low order bits of the address disappear when
they are needed most.

• To make sure we have the entire address for the full three clock cycles, we will use an
external latch to save the value of AD7– AD0 when it is carrying the address bits. We
use the ALE signal to enable this latch.

DEMULTIPLEXING AD7-AD0
Given that ALE operates as a pulse during T1, we will be able to latch the address. Then when
ALE goes low, the address is saved and the AD7– AD0 lines can be used for their purpose as
the bi-directional data lines.

DEMULTIPLEXING THE BUS AD7 – AD0

• The high order address is placed on the address bus and hold for 3 clk periods.
• The low order address is lost after the first clk period, this address needs to be hold
however we need to use latch
• The address AD7 – AD0 is connected as inputs to the latch 74LS373.
• The ALE signal is connected to the enable (G) pin of the latch and the OC – Output
control – of the latch is grounded

ADDRESSING MODES

The microprocessor has different ways of specifying the data for the instruction. These are
called addressing modes.

The 8085 has four addressing modes:

– Implied CMA
– Immediate MVI B, 45
– Direct LDA 4000
– Indirect LDAX B

Load the accumulator with the contents of the memory location whose address is stored in the
register pair BC).

Many instructions require two operands for execution. For example transfer of data between
two registers. The method of identifying the operands position by the instruction format is
known as the addressing mode. When two operands are involved in an instruction, the first
operand is assumed to be in a register Mp itself.

Types of Addressing Modes

• Register addressing

• Direct addressing mode

• Register indirect addressing

• Immediate Addressing mode

 • Implied addressing mode
REGISTER ADDRESSING

This type of addressing mode specifies register or register pair that contains [Link] (only the
register need be specified as the address of the operands).

Example MOV B, A (the content of A is copied into the register B)

DIRECT ADDRESSING MODE

Data is directly copied from the given address to the register.

Example LDA 3000H (The content at the location 3000H is copied to the register A).

REGISTER INDIRECT ADDRESSING

In this mode, the address of operand is specified by a register pair

Example MOV A, M (Move data from memory location specified by H-L pair to accumulator)

IMMEDIATE ADDRESSING MODE

In this mode, the operand is specified within the instruction itself.

Example MVI A, 05 H (Move 05 H in accumulator.)

IMPLIED ADDRESSING MODE

This mode doesn't require any operand. The data is specified by opcode itself.

Example RAL, CMP

INSTRUCTION SET OF 8085

An instruction is a binary pattern designed inside a microprocessor to perform a specific

function. The entire group of instructions that a microprocessor supports is called Instruction
Set. Since the 8085 is an 8-bit device it can have up to 28 (256) instructions. However, the
8085 only uses 246 combinations that represent a total of 74 instructions. Each instruction has
two parts. The first part is the task or operation to be performed. This part is called the —opcode
(operation code). The second part is the data to be operated on. This part is called the operand.

INSTRUCTION SIZE

• Depending on the operand type, the instruction may have different sizes. It will occupy
a different number of memory bytes.
• Typically, all instructions occupy one byte only.
• The exception is any instruction that contains immediate data or a memory address.
• Instructions that include immediate data use two bytes.
• One for the opcode and the other for the 8-bit data.
• Instructions that include a memory address occupy three bytes.
• One for the opcode, and the other two for the 16-bit address.

CLASSIFICATION OF INSTRUCTION SET

• Data Transfer Instruction

• Arithmetic Instructions

• Logical Instructions

• Branching Instructions

• Machine Control Instructions

DATA TRANSFER INSTRUCTIONS

Opcode Operand Description

MOV Rd, Rs M, Rs Rd, M Copy from source to

destination.

This instruction copies the contents of the source register into the destination register. The
contents of the source register are not altered. If one of the operands is a memory location, its
location is specified by the contents of the HL registers. Example: MOV B, C or MOV B, M.

Opcode Operand Description

 MVI Rd, Data M, Data
Move immediate 8-bit

The 8-bit data is stored in the destination register or memory. If the operand is a memory
location, its location is specified by the contents of the H-L registers.
Example: MVI B, 57H or MVI M, 57H.
Opcode Operand Description

LDA 16-bit address Load Accumulator

The contents of a memory location, specified by a 16- bit address in the operand, are copied to
the accumulator. The contents of the source are not altered. Example: LDA 2034H

Opcode Operand Description

LDAX B/D Register Pair Load accumulator indirect

The contents of the designated register pair point to a memory location. This instruction copies
the contents of that memory location into the accumulator. The contents of either the register
pair or the memory location are not altered. Example: LDAX B

Opcode Operand Description

STA 16-bit address Store accumulator direct

The contents of accumulator are copied into the memory location specified by the operand.
Example: STA 2500 H

Opcode Operand Description

STAX Reg. pair Store accumulator indirect

The contents of accumulator are copied into the memory location specified by the contents of
the register pair. Example: STAX B

Opcode Operand Description

SHLD 16-bit address Store H-L registers direct

The contents of register L are stored into memory location specified by the 16-bit address. The
contents of register H are stored into the next memory location. Example: SHLD 2550 H

Opcode Operand Description

XCHG None Exchange H-L with D-E

The contents of register H are exchanged with the contents of register D. The contents of
register L are exchanged with the contents of register E. Example: XCHG

Opcode Operand Description

SPHL None Copy H-L pair to the Stack

Pointer (SP)

This instruction loads the contents of H-L pair into SP. Example: SPHL
 Opcode Operand Description

XTHL None Exchange H–L with top of

stack

The contents of L register are exchanged with the location pointed out by the contents of the
SP. The contents of H register are exchanged with the next location (SP + 1). Example: XTHL

Opcode Operand Description

PCHL None Load program counter with

H-L contents

The contents of registers H and L are copied into the program counter (PC). The contents of
H are placed as the high-order byte and the contents of L as the low-order byte. Example: PCHL

Opcode Operand Description

PUSH Reg. pair Push register pair onto

stack

The contents of register pair are copied onto stack. SP is decremented and the contents of
high-order registers (B, D, H, A) are copied into stack. SP is again decremented and the
contents of low-order registers (C, E, L, Flags) are copied into stack. Example: PUSH B

Opcode Operand Description

POP Reg. pair Pop stack to register pair

The contents of top of stack are copied into register pair. The contents of location pointed out
by SP are copied to the low-order register (C, E, L, Flags). SP is incremented and the contents
of location are copied to the high-order register (B, D, H, A). Example: POP H
 Opcode Operand Description

OUT 8-bit port address Copy data from

accumulator to a port with
8- bit address

The contents of accumulator are copied into the I/O port. Example: OUT 78 H

Opcode Operand Description

IN 8-bit port address Copy data to accumulator

from a port with 8- bit address

The contents of I/O port are copied into accumulator. Example: IN 8C H

ARITHMETIC INSTRUCTIONS

These instructions perform arithmetic operations such as addition, subtraction, increment, and
decrement.

ADDITION

Any 8-bit number, or the contents of register, or the contents of memory location can be added
to the contents of accumulator. The result (sum) is stored in the accumulator. No two other 8-
bit registers can be added directly. Example: The contents of register B cannot be added directly
to the contents of register C.
 Opcode Operand Description

ADD RM Add register or memory to

accumulator

The contents of register or memory are added to the contents of accumulator. The result is
stored in accumulator. If the operand is memory location, its address is specified by H-L pair.
All flags are modified to reflect the result of the addition. Example: ADD B or ADD M

Opcode Operand Description

ADC RM Add register or memory to

accumulator with carry

The contents of register or memory and Carry Flag (CY) are added to the contents of
accumulator. The result is stored in accumulator. If the operand is memory location, its address
is specified by H-L pair. All flags are modified to reflect the result of the addition. Example:
ADC B or ADC M

Opcode Operand Description

ADI 8-bit data Add immediate to

accumulator

The 8-bit data is added to the contents of accumulator. The result is stored in accumulator. All
flags are modified to reflect the result of the addition. Example: ADI 45 H
 Opcode Operand Description

ACI 8-bit data Add immediate to

accumulator with carry

The 8-bit data and the Carry Flag (CY) are added to the contents of accumulator. The result
is stored in accumulator. All flags are modified to reflect the result of the addition. Example:
ACI 45 H

Opcode Operand Description

DAD Reg. pair Add register pair to H-L pair

The 16-bit contents of the register pair are added to the contents of H-L pair. The result is
stored in H-L pair. If the result is larger than 16 bits, then CY is [Link] other flags are changed.
Example: DAD B

SUBTRACTION

Any 8-bit number, or the contents of register, or the contents of memory location can be
subtracted from the contents of [Link] result is stored in the [Link]
is performed in 2’s complement form. If the result is negative, it is stored in 2’s complement
form. No two other 8-bit registers can be subtracted directly.

Opcode Operand Description

SUB RM Subtract register or

memory from accumulator
 The contents of the register or memory location are subtracted from the contents of the
accumulator. The result is stored in accumulator. If the operand is memory location, its address
is specified by H-L pair. All flags are modified to reflect the result of subtraction. Example:
SUB B or SUB M

Opcode Operand Description

SBB RM Subtract register or memory

from accumulator with borrow

The contents of the register or memory location and Borrow Flag (i.e. CY) are subtracted from
the contents of the accumulator. The result is stored in accumulator. If the operand is memory
location, its address is specified by H-L pair. All flags are modified to reflect the result of
subtraction. Example: SBB B or SBB M

Opcode Operand Description

SUI 8-bit data Subtract immediate from

accumulator

The 8-bit data is subtracted from the contents of the [Link] result is stored in
accumulator. All flags are modified to reflect the result of subtraction. Example: SUI 45 H

Opcode Operand Description

SBI 8-bit data Subtract immediate from

accumulator with borrow
 The 8-bit data and the Borrow Flag (i.e. CY) is subtracted from the contents of the
accumulator. The result is stored in [Link] flags are modified to reflect the result of
subtraction. Example: SBI 45 H

INCREMENT/DECREMENT

The 8-bit contents of a register or a memory location can be incremented or decremented by

1. The 16-bit contents of a register pair can be incremented or decremented by 1. Increment or
decrement can be performed on any register or a memory location.

Opcode Operand Description

INR RM Increment register or

memory by 1

The contents of register or memory location are incremented by 1. The result is stored in the
same place. If the operand is a memory location, its address is specified by the contents of H-
L pair. Example: INR B or INR M

Opcode Operand Description

INX R Increment register pair by 1

The contents of register pair are incremented by 1. The result is stored in the same place.
Example: INX H

Opcode Operand Description

DCR R Decrement register or

M memory by 1
 The contents of register or memory location are decremented by 1. The result is stored in the
same place. If the operand is a memory location, its address is specified by the contents of H-
L pair. Example: DCR B or DCR M

Opcode Operand Description

DCX R Decrement register pair by

1

The contents of register pair are decremented by 1. The result is stored in the same place.
Example: DCX H

LOGICAL INSTRUCTIONS

These instructions perform logical operations on data stored in registers, memory and status
flags. The logical operations are:

• AND

• OR

• XOR

• Rotate

• Compare

• Complement AND, OR, XOR

Any 8-bit data, or the contents of register, or memory location can logically have

• AND operation

• OR operation

• XOR operation

with the contents of accumulator. The result is stored in accumulator.

 Opcode Operand Description

ANA RM Logical AND register or

memory with accumulator

The contents of the accumulator are logically ANDed with the contents of register or memory.
The result is placed in the accumulator. If the operand is a memory location, its address is
specified by the contents of H-L pair. S, Z, P are modified to reflect the result of the operation.
CY is reset and AC is set. Example: ANA B or ANA M.

Opcode Operand Description

ANI 8-bit data Logical AND immediate

with accumulator

The contents of the accumulator are logically ANDed with the 8-bit data. The result is placed
in the accumulator. S, Z, P are modified to reflect the [Link] is reset, AC is set. Example:
ANI 86H.

Opcode Operand Description

ORA R Logical OR register or

M memory with accumulator

The contents of the accumulator are logically ORed with the contents of the register or
memory. The result is placed in the accumulator. If the operand is a memory location, its
address is specified by the contents of H-L pair.S, Z, P are modified to reflect the result. CY
and AC are reset. Example: ORA B or ORA M.
 Opcode Operand Description

ORI 8-bit data Logical OR immediate with

accumulator

The contents of the accumulator are logically ORed with the 8-bit data. The result is placed in
the accumulator. S, Z, P are modified to reflect the [Link] and AC are reset. Example: ORI
86H.

Opcode Operand Description

XRA R Logical XOR register or

M memory with accumulator

The contents of the accumulator are XORed with the contents of the register or memory. The
result is placed in the accumulator. If the operand is a memory location, its address is specified
by the contents of H-L pair. S, Z, P are modified to reflect the result of the operation. CY and
AC are reset. Example: XRA B or XRA M.

Opcode Operand Description

XRI 8-bit data XOR immediate with

accumulator

The contents of the accumulator are XORedwith the 8-bit data. The result is placed in the
accumulator. S, Z, P are modified to reflect the result. CY and AC are reset. Example: XRI
86H.

ROTATE

Each bit in the accumulator can be shifted either left or right to the next position as shown in
fig5.
 Opcode Operand Description

RLC None Rotate accumulator left

Fig 1.5. : Work flow of RLC

Each binary bit of the accumulator is rotated left by one position. Bit D7 is placed in the
position of D0 as well as in the Carry flag. CY is modified according to bit D7. S, Z, P, AC are
not affected. Example: RLC.

Opcode Operand Description

RRC None Rotate accumulator right

Each binary bit of the accumulator is rotated right by one position. Bit D0 is placed in the
position of D7 as well as in the Carry flag. CY is modified according to bit D0. S, Z, P, AC are
not affected. Example: RRC.

Opcode Operand Description

RAL None Rotate accumulator left

through carry
 Fig 1.6. : Work flow of RAL

Each binary bit of the accumulator is rotated left by one position through the Carry flag as
shown in fig 6. Bit D7 is placed in the Carry flag, and the Carry flag is placed in the least
significant position D0. CY is modified according to bit D7. S, Z, P, AC are not affected.
Example: RAL.

Opcode Operand Description

RAR None Rotate accumulator right

through carry

Each binary bit of the accumulator is rotated right by one position through the Carry flag. Bit
D0 is placed in the Carry flag, and the Carry flag is placed in the most significant position D7.
CY is modified according to bit D0. S, Z, P, AC are not affected. Example: RAR.

COMPARE

Any 8-bit data, or the contents of register, or memory location can be compares for:

• Equality

• Greater Than

• Less Than

with the contents of accumulator. The result is reflected in status flags.

 Opcode Operand Description

CMP RM Compare register or

memory with accumulator

The contents of the operand (register or memory) are compared with the contents of the
accumulator. Both contents are preserved .The result of the comparison is shown by setting the
flags of the PSW as follows:

• if (A) < (reg/mem): carry flag is set

• if (A) = (reg/mem): zero flag is set

• if (A) > (reg/mem): carry and zero flags are reset.

Example: CMP B or CMP M

Opcode Operand Description

CPI 8-bit data Compare immediate with

accumulator

The 8-bit data is compared with the contents of [Link] values being compared remain
unchanged. The result of the comparison is shown by setting the flags of the PSW as follows:

• if (A) < data: carry flag is set

• if (A) = data: zero flag is set

• if (A) > data: carry and zero flags are reset Example: CPI 89H
COMPLEMENT

The contents of accumulator can be complemented. Each 0 is replaced by 1 and each 1 is

replaced by 0.

Opcode Operand Description

CMA None Complement accumulator

The contents of the accumulator are complemented. No flags are affected. Example: CMA.

Opcode Operand Description

CMC None Complement carry

The Carry flag is complemented. No other flags are affected. Example: CMC.

Opcode Operand Description

STC None Set carry

The Carry flag is set to 1. No other flags are affected. Example: STC.

BRANCHING INSTRUCTIONS

The branching instruction alters the normal sequential flow. These instructions alter either
unconditionally or conditionally.
Branch operations are of two types:
Unconditional branch-- Go to a new location no matter what. Conditional branch-- Go to a
new location if the condition is true.
 Opcode Operand Description

JMP 16-bit address Jump unconditionally

The program sequence is transferred to the memory location specified by the 16-bit address
given in the operand.
Example: JMP 2034 H.

Opcode Operand Description

Jx 16-bit address Jump conditionally

The program sequence is transferred to the memory location specified by the 16-bit address
given in the operand based on the specified flag of the PSW. Replace x with condition
Example: JZ 2034 H. Jump conditionally

Opcode Description Status flag

JC Jump if Carry CY = 1

JNC Jump if no carry CY=0

JP Jump if positive S=0
JM Jump if minus S=1
JZ Jump if Zero Z=1
JNZ Jump if no zero Z=0
JPE Jump if parity even P=1
JPO Jump if parity odd P=0
 Opcode Operand Description

CALL 16-bit address Call unconditionally

The program sequence is transferred to the memory location specified by the 16-bit address
given in the operand. Before the transfer, the address of the next instruction after CALL (the
contents of the program counter) is pushed onto the stack.
Example: CALL 2034 H.

Opcode Operand Description

Cx 16-bit address Call conditionally

The program sequence is transferred to the memory location specified by the 16- bit address
given in the operand based on the specified flag of the PSW. Before the transfer, the address
of the next instruction after the call (the contents of the program counter) is pushed onto the
stack. Replace x with condition
Example: CZ 2034 H. Call Conditionally

Opcode Description Status flag

CC Call if carry CY=1
CNC Call if no carry CY=0
CP Call if positive S=0
CM Call if minus S=1
CZ Call if Zero Z=1
CNZ Call if no zero Z=0
CPE Call if parity even P=1
CPO Call if parity odd P=0
 Opcode Operand Description

RET None Return unconditionally

The program sequence is transferred from the subroutine to the calling program. The two bytes
from the top of the stack are copied into the program counter, and program execution begins at
the new address.
Example: RET.

Opcode Operand Description

Rx None Call conditionally

The program sequence is transferred from the subroutine to the calling program based on the
specified flag of the PSW. The two bytes from the top of the stack are copied into the program
counter, and program execution begins at the new address. Example: RZ. Replace x with
condition

RETURN CONDITIONALLY

Opcode Description Status flag

RC Return if carry CY=1
RNC Return if no carry CY=0
RP Return Call if positive S=0
RM Return if minus S=1
RZ Return if Zero Z=1
RNZ Return if no zero Z=0
RPE Return if parity even P=1
RPO Return if parity odd P=0
 Opcode Operand Description

RST 0-7 Restart (Software

Interrupts)

The RST instruction jumps the control to one of eight memory locations depending upon the
number. These are used as software instructions in a program to transfer program execution to
one of the eight locations. Example: RST 3.

RESTART Address table

Instructions Restart address

RST 0 0000 H
RST 1 0008 H
RST 2 0010 H
RST 3 0018 H
RST 4 0020 H
RST 5 0028 H
RST 6 0030 H
RST 7 0038 H

MACHINE CONTROL INSTRUCTIONS

The control instructions control the operation of microprocessor.

Opcode Operand Description

NOP None No operation

No operation is performed. The instruction is fetched and decoded but no operation is executed.
Usually used for delay or to replace instructions during debugging.
Example: NOP
 Opcode Operand Description

HLT None Halt

The CPU finishes executing the current instruction and halts any further execution. An
interrupt or reset is necessary to exit from the halt state. Example: HLT

Opcode Operand Description

DI None Disable interrupt

The interrupt enable flip-flop is reset and all the interrupts except the TRAP are disabled.
No flags are affected.
Example: DI

Opcode Operand Description

EI None Enable interrupt

The interrupt enable flip-flop is set and all interrupts are enabled. No flags are affected. This
instruction is necessary to re-enable the interrupts (except TRAP).

Example: EI

Operand Description
Opcode

RIM None Read Interrupt Mask

This is a multipurpose instruction used to read the status of interrupts 7.5, 6.5, 5.5 and read
serial data input bit. The instruction loads eight bits in the accumulator with the following
interpretations.

Example: RIM
RIM Instruction

Opcode Operand Description

SIM None Set Interrupt Mask

This is a multipurpose instruction and used to implement the 8085 interrupts 7.5, 6.5, 5.5, and
serial data output. The instruction interprets the accumulator contents as follows.
Example: SIM SIM Instruction
TIMING DIAGRAM

Timing diagram is the display of initiation of read/write and transfer of data operations under
the control of 3-status signals IO / M, S1, and S0. All actions in the microprocessor are
controlled by either leading or trailing edge of the clock.

MACHINE CYCLE
It is the time required by the microprocessor to complete the operation of accessing the memory
devices or I/O devices. In machine cycle various operations like opcode fetch, memory read,
memory write, I/O read, I/O write are performed.

T-STATE

Each clock cycle is called as T-states.

Each machine cycle is composed of many clock cycles. Since, the data and instructions, both
are stored in the memory, the µP performs fetch operation to read the instruction or data and
then execute the instruction. The 3-status signals: IO / M, S1, and S0 are generated at the
beginning of each machine cycle. The unique combination of these 3-status signals identify
read or write operation and remain valid for the duration of the cycle.

Table 1 Machine Cycle Status And Control Signals

Table1 shows details of the unique combination of these status signals to identify different
machine cycles. Thus, time taken by any µP to execute one instruction is calculated in terms
of the clock period. The execution of instruction always requires read and writes operations to
transfer data to or from the µP and memory or I/O devices. Each read/ write operation
constitutes one machine cycle (MC1) as indicated in Fig.1.7. Each machine cycle consists of
many clock periods/ cycles, called T-states.

Fig.1.7 Machine cycle showing clock periods

PROCESSOR CYCLE:

The functions of the microprocessor are divided into fetch and execute cycle of any instruction
of a program. The program is nothing but number of instructions stored in the memory in
sequence. In the normal process of operation, the microprocessor fetches (receives or reads)
and executes one instruction at a time in the sequence until it executes the halt (HLT)
instruction.

INSTRUCTION CYCLE

An instruction cycle is defined as the time required to fetch and execute an instruction. For
executing any program, basically 2-steps are followed sequentially with the help of clocks

• Fetch
• Execute.

The time taken by the µP in performing the fetch and execute operations are called fetch and
execute cycle. Thus, sum of the fetch and execute cycle is called the instruction cycle as
indicated in Fig. 8. Each read or writes operation constitutes a machine cycle. The instructions
of 8085 require 1–5 machine cycles containing 3–6 states (clocks). The 1st machine cycle of
any instruction is always an Op Code fetch cycle in which the processor decides the nature of
instruction. It is of at least 4-states. It may go up to 6-states.

39
 Fig.1.8 Processor cycle

RULES TO IDENTIFY NUMBER OF MACHINE CYCLES IN AN INSTRUCTION:

• If an addressing mode is direct, immediate or implicit then No. of machine cycles =

No. of bytes.

• If the addressing mode is indirect then No. of machine cycles = No. of bytes + 1. Add
+1 to the No. of machine cycles if it is memory read/write operation.

• If the operand is 8-bit or 16-bit address then, No. of machine cycles = No. of bytes
+1.

• These rules are applicable to 80% of the instructions of 8085.

TIMING DIAGRAM OF OPCODE FETCH

The process of Opcode fetch operation requires minimum 4-clock cycles T1, T2, T3, and T4
and is the 1st machine cycle (M1) of every instruction.

Example
Fetch a byte 41H stored at memory location 2105H.
For fetching a byte, the microprocessor must find out the memory location where it is stored.
Then provide condition (control) for data flow from memory to the microprocessor. The
process of data flow and timing diagram of fetch operation are shown in Fig. 9. The
microprocessor fetches Opcode of the instruction from the memory as per the sequence below

• A low IO/M means microprocessor wants to communicate with memory.

• The microprocessor sends a high on status signal S1 and S0 indicating fetch operation.
• The microprocessor sends 16-bit address. AD bus has address in 1st clock of the 1st
machine cycle, T1.
• AD7 to AD0 address is latched in the external latch when ALE = 1.

• AD bus now can carry data.

40
 • In T2, the RD control signal becomes low to enable the memory for read operation.
• The memory places opcode on the AD bus

• The data is placed in the data register (DR) and then it is transferred to IR.

• During T3 the RD signal becomes high and memory is disabled.

• During T4 the opcode is sent for decoding and decoded in T4.

• The execution is also completed in T4 if the instruction is single byte.

• More machine cycles are essential for 2- or 3-byte instructions. The 1st machine cycle
M1 is meant for fetching the opcode. The machine cycles M2 and M3 are required
either read/ write data or address from the memory or I/O devices.

Fig. 1.9 Opcode fetch

Example For Opcode Fetch

• Explain the execution of MVI B, 05H stored at locations indicated below

41
 Fig. 1.10 Timing diagram for MVI B,05H

The MVI B, 05H instruction requires 2-machine cycles (M1 and M2). M1 requires 4-states
and M2 requires 3-states, total of 7-states as shown in Fig. 10. Status signals IO/M, S1 and S0
specifies the 1st machine cycle as the op-code fetch. In T1-state, the high order address {10H}
is placed on the bus A15 ⇔A8 and low-order address {00H} on the bus AD7 ⇔AD0 and ALE
= 1. In T2 -state, the RD line goes low and the data 06 H from memory location 1000H are
placed on the data bus. The fetch cycle becomes complete in T3-state. The instruction is
decoded in the T4-state. During T4-state, the contents of the bus are unknown. With the change
in the status signal, IO/M = 0, S1 = 1 and S0 = 0, the 2nd machine cycle is identified as the
memory read. The address is 1001H and the data byte [05H] is fetched via the data bus. Both
M1 and M2 perform memory read operation, but the M1 is called op-code fetch i.e., the 1st
machine cycle of each instruction is identified as the opcode fetch cycle.

TIMING DIAGRAM OF MEMORY READ

Operation:

42
 • It is used to fetch one byte from the memory.

• It requires 3 T-States.

• It can be used to fetch operand or data from the memory.

• During T1, A8-A15 contains higher byte of address. At the same time ALE is high.
Therefore Lower byte of address A0-A7 is selected from AD0-AD7 as shown in fig
11.
• Since it is memory ready operation, IO/M (bar) goes low.

• During T2 ALE goes low, RD (bar) goes low. Address is removed from AD0-AD7
and data D0-D7 appears on AD0-AD7.
• During T3, Data remains on AD0-AD7 till RD (bar) is at low signal.

Fig 11. Timing Diagram of Memory Read

TIMING DIAGRAM FOR MEMORY WRITE

Operation:

• It is used to send one byte into memory.

• It requires 3 T-States.

43
 • During T1, ALE is high and contains lower address A0-A7 from AD0-AD7.

• A8-A15 contains higher byte of address.

• As it is memory operation, IO/M (bar) goes low.

• During T2, ALE goes low, WR (bar) goes low and Address is removed from AD0-
AD7 and then data appears on AD0-AD7 as in fig 12.
• Data remains on AD0-AD7 till WR (bar) is low.

Fig [Link] Write timing diagram

TIMING DIAGRAM OF IO READ

Operation:

1. It is used to fetch one byte from an IO port.

2. It requires 3 T-States.
3. During T1, The Lower Byte of IO address is duplicated into higher order address bus
A8-A15 as in fig13.
4. ALE is high and AD0-AD7 contains address of IO device.
5. IO/M (bar) goes high as it is an IO operation.
6. During T2, ALE goes low, RD (bar) goes low and data appears on AD0-AD7 as input
from IO device.
7. During T3 Data remains on AD0-AD7 till RD (bar) is low.

44
 Fig [Link] Read timing diagram

TIMING DIAGRAM OF IO WRITE

Operation:

1. It is used to writ one byte into IO device.

2. It requires 3 T-States.
3. During T1, the lower byte of address is duplicated into higher order address bus A8-
A15 as in fig 14.
4. ALE is high and A0-A7 address is selected from AD0-AD7.
5. As it is an IO operation IO/M (bar) goes low.
6. During T2, ALE goes low, WR (bar) goes low and data appears on AD0-AD7 to write
data into IO device.
7. During T3, Data remains on AD0-AD7 till WR(bar) is low.

45
Fig 14. IO Write timing diagram

46
Interrupts

47
INTERRUPT:

An interrupt is a signal initiated by an external device to the microprocessor. Once this signal
is received, the microprocessor completes the execution of the current instruction and responds
to the interrupt

SOFTWARE INTERRUPTS OF 8085

The software interrupts are program instructions. When the instruction is executed, the
processor executes an interrupt service routine stored in the vector address of the software
interrupt instruction. The software interrupts of 8085 are RST 0, RST 1, RST 2, RST 3, RST
4, RST 5, RST 6 and RST 7.

The vector addresses of software interrupts are given in table below

48
 The software interrupt instructions are included at the appropriate (or required) place in the
main program. When the processor encounters the software instruction, it pushes the content
of PC (Program Counter) to stack. Then loads the Vector address in PC and starts executing
the Interrupt Service Routine (ISR) stored in this vector address. At the end of ISR, a return
instruction - RET will be placed. When the RET instruction is executed, the processor POP
the content of stack to PC. Hence the processor control returns to the main program after
servicing the interrupt. Execution of ISR is referred to as servicing of interrupt. All software
interrupts of 8085 are vectored interrupts. The software interrupts cannot be masked and they
cannot be disabled. The software interrupts are RST0, RST1, … RST7 (8 Nos).

HARDWARE INTERRUPTS OF 8085

These are the interrupts provided as signals to the microprocessor. There are five interrupt
signals in 8085. They are Trap, RST 7.5, RST 6.5, RST 5.5 and INTR. The priority of the
interrupts is from TRAP to INTR. The program executed for the service of the interrupting
device is called the service routine.

TRAP

1. This interrupt is a Non-Maskable interrupt (NMI). It is unaffected by any mask or

interrupt enable.

2. TRAP is the highest priority and vectored interrupt(as vector address is fixed i.e.
memory location where to transfer control).

3. TRAP interrupt is edge and level triggered. This means hat the TRAP must go high
and remain high until it is acknowledged.

4. In sudden power failure, it executes a ISR and send the data from main memory to
backup memory.

5. The signal, which overrides the TRAP, is HOLD signal. (i.e., If the processor receives
HOLD and TRAP at the same time then HOLD is recognized first and then TRAP is
recognized).

6. There are two ways to clear TRAP interrupt.

• By resetting microprocessor (External signal)

• By giving a high TRAP ACKNOWLEDGE (Internal signal)

RST 7.5

• The RST 7.5 interrupt is a Maskable interrupt.

49
 • It has the second highest priority.
• It is edge sensitive. i.e. Input goes to high and no need to maintain high state until
it recognized.

• Maskable interrupt

It is disabled by,

• DI, SIM instruction

• System or processor reset.
• After reorganization of interrupt.

RST 6.5 and 5.5

• The RST 6.5 and RST 5.5 both are level triggered (i.e.) Input goes to high and stay
high until it recognized.

• Maskable interrupt

It is disabled by,

• DI, SIM instruction

• System or processor reset.
• After reorganization of interrupt.
• Enabled by EI instruction.
• The RST 6.5 has the third priority whereas RST 5.5 has the fourth priority.

These interrupts are classified further into two classes based on the destination address and
response. Based on the service routine address, interrupts are classified in to vectored and non-
vectored interrupt.

VECTORED INTERRUPT:

If the address of the service routine is known to the microprocessor, i.e. if the service routine
begins at a predefined address, then the interrupts are called vectored interrupts. The vectored
address is calculated as (nx8)16 where n is the number of RST.

For example:

The vectored address of RST 7.5 is 7.5 x 8=60.0

60 in hexadecimal number system is 003C. Therefore the branching address of RST 7.5 is
003C.

Interrupt Address

50
 RST 7.5 003C
RST 6.5 0034
RST 5.5 002C
TRAP (RST 4.5) 0024

NON VECTORED INTERRUPT:

The address of the service routine is not known in prior to the microprocessor. It is sent by the
interrupting [Link] the interrupt flipflop is enabled and INTR is high, microprocessor
executes the current instruction and makes INTA low. Based on the flexibility to enable or
disable interrupt, the interrupts are classified as maskable interrupt and non maskable interrupt.
Maskable Interrupt: Even if the interrupt signals are high, microprocessor will respond to
these signals only when interrupt flip flop is enabled. Example RST 7.5, RST 6.5, RST 5.5,
INTR

Non-Maskable Interrupt: Once the signal is enabled, the microprocessor immediately

responds to this interrupt. Example: TRAP
Stack & subroutines
STACK

Stack is the upper part of the memory used for storing temporary information. It is a Last In
First Out Memory (LIFO). In 8085, it is accessed using PUSH and POP instructions. During
pushing, the stack operates in a decrement then store‖ style. The stack pointer is decremented
first, then the information is placed on the stack. During poping, the stack operates in a use
then increment style. The information is retrieved from the top of the the stack and then the
pointer is incremented. The SP pointer always points to the top of the stack‖.

PROGRAM STATUS WORD (PSW)

The 8085 recognizes one additional register pair called the PSW (Program Status Word). This
register pair is made up of the Accumulator and the Flags registers. It is possible to push the
PSW onto the stack, do whatever operations are needed, then POP it off of the stack. The result
is that the contents of the Accumulator and the status of the Flags are returned to what they
were before the operations were executed.
SUBROUTINES
A subroutine is a group of instructions that will be used repeatedly in different locations of the
program. Rather than repeat the same instructions several times, they can be grouped into a
subroutine that is called from the different locations. In Assembly language, a subroutine can
exist anywhere in the code. However, it is customary to place subroutines separately from the
main program. The 8085 has two instructions for dealing with subroutines. The CALL
instruction is used to redirect program execution to the subroutine. The RET instruction is used
to return the execution to the calling routine.

CALL
CALL 4000H (3 byte instruction)
When CALL instruction is fetched, the MP knows that the next two Memory location contains
16bit subroutine address in the memory.

Fig [Link] flow of CALL instruction

MP Reads the subroutine address from the next two memory location and stores the higher
order 8bit of the address in the W register and stores the lower order 8bit of the address in the
Z register. Push the address of the instruction immediately following the CALL onto the stack
[Return address]. Loads the program counter with the 16-bit address supplied with the CALL
instruction from WZ register as shown in fig 17.

RET (1 byte instruction)

Retrieve the return address from the top of the stack. Load the program counter with the return
address as seen in fig 18.

Fig [Link] flow of RET instruction

The processor can regain the buses only after the Hold is removed. When the Hold is
acknowledged, the Address, Data, RD, WR, and IO/M lines are stated.
I/O data transfer techniques
 8085 Interfacing with I/O devices
There are various communication devices like the keyboard, mouse, printer, etc. So, we need
to interface the keyboard and other devices with the microprocessor by using latches and
buffers. This type of interfacing is known as I/O interfacing.
Microprocessor needs to Identify I/O devices with binary number. I/O devices can be interfaced
in three
steps.
1. Identify the memory location (with address).
2. Generate timing and control signal.
3. Data transfer takes place.
The techniques used for I/O interfacing are
1. Memory mapped I/O
2. I/O mapped I/O or Peripheral mapped I/O

1. Memory-Mapped I/O
• In memory mapped I/O, each device has an address just like a memory location.
• The memory map (64K) is shared between I/O device and system memory.
• Instructions STA/.LDA and MOV are used for data transfer.
• Device is identified by 16-bit address (Space ranges from 0000H –FFFFH).

2. Peripheral Mapped I/O

• 256 input device and 256. output device can be connected.
• It has separate numbering scheme for I/O devices.
• Instructions IN & OUT are used for data transfer.
• Device is identified by 8-bit address (Space ranges from 00H –FFH).

Device Selection and Data Transfer

Data transfer steps

 ❖ For data transfer from input device to processor the following operations are performed
1. The MPU places an 8-bit device address on address bus then decoded.
2. The MPU sends a control signal (IOR or IOW) to enable the I/O device.
3. Data are placed on the data bus for transfer.

❖ Data transfer from processor to output device the following operations are performed.
To send data to O/P device :-
1. The MPU places the device address (output port no.) on the address bus.

Data Transfer Concepts

• The 8085 microprocessor is a parallel device. That means it transfers eight bits of data
simultaneously over eight data lines (parallel I/O mode).

• However in many situations, the parallel I/O mode is either impractical or impossible. For
example, parallel data communication over a long distance becomes very expensive.

• Similarly, parallel data communication is not possible with devices such as CRT terminal or
Cassette tape etc

Types of Data transfer scheme

Data transfer between microprocessor to memory and microprocessor to I/O devices is explained in the following
ways The data transfer can be classified into

1. Parallel data transfer

2. Serial data transfer

I. Parallel data transfer

Parallel data transfer scheme is faster than serial I/O transfer. in parallel data transfer 8-bit data send
all together with 8 parallel wire. It is further divided into

• Programmed I/O
• Interrupt I/O
• DMA
Programmed I/O:

✓ Here the processor has to check whether the I/O device is ready or not through the Ready signal of
the I/O device.
✓ If the ready signal is high then it will send the data to the I/O device.
✓ Otherwise it will continuously check the Ready signal.
 ✓ The processor is busy in checking the Ready signal.
✓ The drawback is wastage of time.

Interrupt I/O:

✓ In this method the I/O device will interrupt the Processor through the INTR signal to indicate to
the processor that it is ready to accept the next data.
✓ Then the processor will send the INTA signal.
✓ Then the processor stops its normal execution and start transferring the data to the I/O device.
DMA:
✓ Using DMA I/O device can directly transfer the data to the Memory using the Address and Data
buses of Processor.
II. Serial data Transfer

✓ Some of the external I/0 devices receive only the serial data. Normally serial communication is used
in the Multiprocessor environment.
✓ In serial I/O mode transfer a single bit of data on a single line at a time. For serial I/O data
transmission mode, 8-bit parallel word is converted to a stream of eight serial bit using parallel-to-
serial converter.
✓ Similarly, in serial reception of data, the microprocessor receives a stream of 8-bit one by one which
are then converted to 8- bit parallel word using serial-to-parallel converter.8051 has two pins for
serial communication.
❖ SID- Serial Input data.
❖ SOD-Serial Output data
DATA TRANSFER SCHEMES
• In a microprocessor-based system, the data transfer takes place between two devices such
as microprocessor and memory, microprocessor and I/O devices and memory and I/O devices.
• A microprocessor based system or a computer may have several I/O devices of different speed.
• A slow I/O device cannot transfer data because it takes some time to get ready.
• To solve this problem of speed mismatch between a microprocessor and I/O devices a number of
data transfer techniques have been developed.

They are classified into two categories.

1. Programmed data transfer scheme
2. DMA (Direct Memory Access) data transfer scheme

Programmed Data Transfer Scheme

• Programmed data transfer scheme are controlled by the CPU.
• Data are transferred an I/O device to the CPU or vice versa under the control of programs.
• These programs are executed by the CPU when an I/O device is ready to transfer data.
 • It is used when small amount of data are to be transferred. It is classified into following
three categories.

Synchronous Data Transfer Scheme

• Synchronous means “at the same time”.
• The device which sends data and the device which receives data are synchronized with the
same clock.
• The data transfer with I/O devices is performed by executing IN or OUT instructions for
I/O mapped I/O devices.

[OR]
• The data transfer with I/O devices is performed by executing memory read/write instruction
for memory mapped I/O devices.
• In this type of data transfer, the status of the I/O device i.e., whether it is ready or not, is
not examined before data are transferred. Hence, this technique is rarely used for I/O devices.

Asynchronous Data Transfer Scheme

• Asynchronous means “at irregular intervals”.
• The device which sends data and the device which receives data are not synchronized with the
same clock.
• This technique of data transfer is used when the speed of an I/O device does not match the
speed of the microprocessor and also the timing characteristic of I/O device is not
predictable.
• The status of the I/O device i.e., whether the device is ready or not is checked by
the microprocessor before the data are transferred.
• If it is not ready, the microprocessor initiates the I/O device to get ready and then
continuously checks the status of the I/O device till the I/O device becomes ready to transfer data.
• When I/O device becomes ready, the microprocessor sends instruction to transfer data.
• This method of data transfer is also called handshaking mode.
• The microprocessor sends an initiating signal to the I/O device to get ready.
• When I/O device becomes ready it sends signals to the processor to indicate that it is
ready. Such signals are called handshake signals.

Interrupt Driven Data Transfer Scheme

• In this scheme, the microprocessor initiates an I/O device to get ready and then it executes
its main program instead of remaining in a program loop to check the status of the I/O device.
• When the I/O device becomes ready to transfer data, it sends a high signal to the
microprocessor through a special input line called an interrupt line.
• In other word, it interrupts the normal processing sequence of the microprocessor.
• On receiving the microprocessor completes the current instruction at hand and then attends the
 I/O device.
• It saves the contents of the program counter on the stack first and then takes up a
subroutine called Interrupt Service Subroutine (ISS).

DMA Transfer Scheme

• DMA transfer scheme is not controlled by the CPU. Data are directly transferred from an
I/O device to the memory or vice versa.
• The data transfer is controlled by the I/O device or a DMA controller. It is used when
large amount of data are to be transferred.
• DMA data transfer scheme is faster than programmed data transfer scheme.
• It is used to transfer data from mass storage devices such as hard disks, floppy disks etc.,
• It is also used for high-speed printers.

DMA data transfer scheme are of the following two types. Burst Mode

• In which the I/O device withdraws the DMA request only after on the data bytes have
been transferred is called burst mode of data transfer.
• It is employed by magnetic disk drives.

Cycle Stealing Technique

• In this technique, a long block of data is transferred by a sequence of DMA cycles.
• In this method after transferring one byte or several bytes the I/O device withdraws
DMA request.
• This method reduces interference in CPU‟s activities.
• The interference can be eliminated completely by designing an interfacing circuitry which can
steal bus cycle for DMA data transfer only when the CPU is not using the system bus.
8086 Microprocessor
INTEL 8086
Features of 8086 Microprocessor:
• Intel 8086 was launched in 1978.
• It was the first 16-bit microprocessor.
• This microprocessor had major improvement over the execution speed of 8085.
• It is available as 40-pin Dual-Inline-Package (DIP).
• It is available in three versions:
a. 8086 (5 MHz)

b. 8086-2 (8 MHz)
c. 8086-1 (10 MHz)
• It consists of 29,000 transistors.
• It has a 16 line data bus and 20 line address bus.
• It could address up to 1 MB of memory.
• It has more than 20,000 instructions.

PIN DIAGRAM OF 8086

Figure 2.1 Pin diagram

AD0-AD15

These lines are multiplexed bidirectional address/data bus. During T1, they carry lower
order 16-bit address. In the remaining clock cycles,they carry 16-bit data. AD0-AD7 carry
lower order byte of data. AD8-AD15 carry higher order byte of data.

A19/S6, A18/S5, A17/S4, A16/S3 [Pin 35-38 (Unidirectional)]

These lines are multiplexed unidirectional address and status bus. During T1, they carry
higher order 4-bit address. In the remaining clock cycles, they carry status signals.

BHE / S7 [Pin 34 (Output)]

BHE stands for Bus High Enable. BHE signal is used to indicate the transfer of data over
higher order data bus (D8 – D15). 8-bit I/O devices use this signal. It is multiplexed with
status pin S7.

RD (Read) [Pin 32 (Output)]

It is a read signal used for read operation. It is an output signal. It is an active low signal.

READY [ Pin 22 (Input)]

This is an acknowledgement signal from slower I/O devices or memory. It is an active

high signal. When high, it indicates that the device is ready to transfer data. When low,
then microprocessor is in wait state.

RESET[Pin 21 (Input)]

It is a system reset. It is an active high signal. When high, microprocessor enters into reset
state and terminates the current activity. It must be active for atleast four clock cycles to
reset the microprocessor.

INTR [Pin 18 (Input)]

It is an interrupt request signal. It is active high. It is level triggered

NMI[Pin 17 (Input)]

It is a non-maskable interrupt signal. It is an active high. It is an edge

triggered interrupt.
TEST[Pin 23 (Input)]

It is used to test the status of math coprocessor 8087. The BUSY pin of 8087 isconnected
to this pin of 8086. If low, execution continues else microprocessor is in wait state.

CLK[Pin 19 (Input)]

This clock input provides the basic timing for processor operation. It is symmetric square
wave with 33% duty cycle. The range of frequency of different versions is 5 MHz, 8 MHz
and 10 MHz.

VCC and VSS[Pin 40 and Pin 20 (Input)]

VCC is power supply signal. +5V DC is supplied through this pin. VSS is ground signal

MN / MX[Pin 33 (Input)]

8086 works in two modes: Minimum Mode, Maximum Mode. If MN/MX is high, it works
in minimum mode. If MN/MX is low, it works in maximum mode. Pins 24 to 31 issue two
different sets of signals. One set of signals is issued when CPU operates in minimum mode.
Other set of signals is issued when CPU operates in maximum mode.

PIN DESCRIPTION FOR MINIMUM MODE

INTA [Pin 24 (Output)]

This is an interrupt acknowledge signal. When microprocessor receives INTR signal, it

acknowledges the interrupt by generating this signal. It is an active low signal

ALE [Pin 25 (Output)]

This is an Address LatchEnable signal. It indicates that valid address is available on bus
AD0 – AD15. It is an active high signal and remains high during T1 state. It is connected
to enable pin of latch 8282.

DEN[Pin 26 (Output)]

This is a Data Enable signal. This signal is used toenable the transceiver 8286. Transceiver
is used to separate the data from the address/data bus. It is an active low signal

DT / R[Pin 27 (Output)]

This is a DataTransmit/Receive signal. It decides the direction ofdata flow through the
transceiver. When it is high, data is transmitted out. When it is low, data is received in.
M / IO[Pin 28 (Output)]

This signal is issued by the microprocessor to distinguish memory access from I/O access.
When it is high, memory is accessed. When it is low, I/O devices are accessed.

WR [Pin 29 (Output)]

It is a Write signal. It is used to write data inmemory or output device depending on the
status of M/IO signal. It is an active low signal

HLDA[Pin 30 (Output)]

It is a Hold Acknowledge signal. It is issued after receiving the HOLD signal. It is an

active high signal

HOLD[Pin 31 (Input)]

When DMA controller needs to use address/data bus, it sends a request to the CPU through
this pin. It is an active high signal. When microprocessor receives HOLD signal, it issues
HLDA signal to the DMA controller.

PIN DESCRIPTION FOR MAXIMUM MODE

QS1 and QS0 [Pin 24 and 25 (Output)]

These pins provide the status of instruction queue.

QS1 QS0 STATUS

0 0 NO OPERATION
0 1 1st byte of opcode from queue
1 0 Empty queue
1 1 Subsequent byte from queue

S0, S1, S2 [Pin 26, 27, 28 (Output)]

These status signals indicate the operation being done by the microprocessor. This
information is required by the Bus Controller 8288. Bus controller 8288 generates all
memory and I/O control signals.

S0 S1 S2 STATUS
0 0 0 Interrupt Acknowledge
0 0 1 I/O Read
0 1 0 I/O Write
 0 1 1 Halt
1 0 0 Opcode Fetch
1 0 1 Memory Read
1 1 0 Memory Write
1 1 1 Passive

LOCK[Pin 29 (Output)]

• This signal indicates that other processors should not ask CPU to relinquish the
system bus. When it goes low, all interrupts are masked and HOLD request is not
granted. This pin is activated by using LOCK prefix on any instruction.

RQ/GT1 and RQ/GT0 [Pin 30 and 31 (Bi-directional)]

• These are Request/Grant pins. Other processors request the CPU through these
lines to release the system bus. After receiving the request, CPU sends
acknowledge signal on the same lines. RQ/GT0 has higher priority than
RQ/GT1.

ARCHITECTURE OF 8086

The microprocessors functions as the CPU in the stored program model of the digital
computer. Its job is to generate all system timing signals and synchronize the transfer of data
between memory, I/O, and itself. The microprocessor also has a S/W function. It must
recognize, decode, and execute program instructions fetched from the memory unit. This
requires an Arithmetic-Logic Unit (ALU) within the CPU to perform arithmetic and logical
(AND, OR, NOT, compare, etc) functions.

The 8086 has pipelined architecture. The 8086 CPU is organized as two separate
processors, called the Bus Interface Unit (BIU) and the Execution Unit (EU).
 Fig : Architecture of 8086

BUS INTERFACE UNIT (BIU)

The function of BIU is to:

• Fetch the instruction or data from memory.

• Write the data to memory.

• Write the data to the port.

• Read data from the port.

INSTRUCTION QUEUE

• To increase the execution speed, BIU fetches as many as six instructionbytes

ahead to time from memory.

• All six bytes are then held in first in first out 6 byte register called instruction
queue.

• Then all bytes have to be given to EU one by one.

• This pre fetching operation of BIU may be in parallel with execution operationof
EU, which improves the speed execution of the instruction.

EXECUTION UNIT (EU)

The functions of execution unit are:

• To tell BIU where to fetch the instructions or data from.

• To decode the instructions.

• To execute the instructions.

The EU contains the control circuitry to perform various internal operations. A decoder in
EU decodes the instruction fetched memory to generate different internal or external control
signals required to perform the operation. EU has 16-bit ALU, which can perform arithmetic
and logical operations on 8-bit as well as 16-bit.

GENERAL PURPOSE REGISTERS OF 8086

These registers can be used as 8-bit registers individually or can be used as 16-bit in pair
to have AX, BX, CX, and DX.

• AX Register: AX register is also known as accumulator register that stores

operands for arithmetic operation like divided, rotate.
• BX Register: This register is mainly used as a base register. It holds the starting
base location of a memory region within a data segment.

• CX Register: It is defined as a counter. It is primarily used in loop instructionto

store loop counter.

• DX Register: DX register is used to contain I/O port address for I/O instruction.
SEGMENT REGISTERS :

Additional registers called segment registers generate memory address when combined with
other in the microprocessor. In 8086 microprocessor, memory is divided into 4 segments as
follow:

Fig.2.3 Memory Segments of 8086

• Code Segment (CS): The CS register is used for addressing a memory location in
the Code Segment of the memory, where the executable program is stored.
• Data Segment (DS): The DS contains most data used by program. Data are accessed
in the Data Segment by an offset address or the content of other register that holds
the offset address.
• Stack Segment (SS): SS defined the area of memory used for the stack
• Extra Segment (ES): ES is additional data segment that is used by some of the
string to hold the destination data.

Flag register in EU is of 16-bit , is shown

Fig : Flag Register of 8086

Flag Register determines the current state of the processor. They are modified automatically
by CPU after mathematical operations, this allows to determine the type of the result, and
to determine conditions to transfer control to other parts of the program. 8086 has 9 flags
and they are divided into two categories:

1. Conditional Flags

2. Control Flags

CONDITIONAL FLAGS

Conditional flags represent result of last arithmetic or logical instruction executed.

Conditional flags are as follows:

1. Carry Flag (CF): This flag indicates an overflow condition for unsigned integer
arithmetic. It is also used in multiple-precision arithmetic.

2. Auxiliary Flag (AF): If an operation performed in ALU generates a carry/barrow

from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), the AF flag is set
i.e. carry given by D3 bit to D4 is AF flag. This is not a general-purpose flag, it is
used internally by the processor to perform Binary to BCD conversion.

3. Parity Flag (PF): This flag is used to indicate the parity of result. If lower order 8-
bits of the result contains even number of 1’s, the Parity Flag is set and for odd
number of 1’s, the Parity Flag is reset.

4. Zero Flag (ZF): It is set; if the result of arithmetic or logical operation is zero else
it is reset.

5. Sign Flag (SF): In sign magnitude format the sign of number is indicated byMSB
bit. If the result of operation is negative, sign flag is set.

6. Overflow Flag (OF): It occurs when signed numbers are added or subtracted. An
OF indicates that the result has exceeded the capacity of machine.

CONTROL FLAGS

Control flags are set or reset deliberately to control the operations of the execution unit.
Control flags are as follows:

1. Trap Flag (TP):

a. It is used for single step control.

b. It allows user to execute one instruction of a program at a time for debugging.

c. When trap flag is set, program can be run in single step mode.
2. Interrupt Flag (IF):

a. It is an interrupt enable/disable flag.

b. If it is set, the maskable interrupt of 8086 is enabled
and if it is reset, the interrupt is disabled.

c. It can be set by executing instruction sit and can be

cleared by executing CLI instruction.

3. Direction Flag (DF):

a. It is used in string operation.

b. If it is set, string bytes are accessed from higher
memory address to lower memory address.

c. When it is reset, the string bytes are accessed

from lower memory address to higher memory
address.

1
I/O Controllers

2
8255 - PROGRAMMABLE PERIPHERAL INTERFACE (PPI )

The Intel 8255 (or i8255) Programmable Peripheral Interface (PPI) chip is a peripheral chip,
is used to give the CPU access to programmable parallel I/O. It can be programmable to transfer
data under various conditions from simple I/O to interrupt I/O. it is flexible versatile and
economical (when multiple I/O ports are required) but somewhat complex. It is an important
general purpose I/O device that can be used with almost any microprocessor.

Fig 3.1: Pin diagram of 8255

FUNCTIONAL BLOCK OF 8255 – PROGRAMMABLE PERIPHERAL INTERFACE

(PPI)

3
The 8255A has 24 I/O pins that can be grouped primarily in two 8-bit parallel ports: A and B
with the remaining eight bits as port C. The eight bits of port C can be used as individual bits
or be grouped in to 4-bit ports: CUpper (Cu) and CLower (CL) as in Figure 2. The function of
these ports is defined by writing a control word in the control register as shown in Figure 3

Fig 3.2. Block diagram of 8255

4
 Fig 3.3 Control word Register format

DATA BUS BUFFER

This three-state bi-directional 8-bit buffer is used to interface the 8255 to the system data bus.
Data is transmitted or received by the buffer upon execution of input or output instructions by
the CPU. Control words and status information are also transferred through the data bus buffer.

READ/WRITE AND CONTROL LOGIC

The function of this block is to manage all of the internal and external transfers of both Data
and Control or Status words. It accepts inputs from the CPU Address and Control busses and
in turn, issues commands to both of the Control Groups.

(CS) Chip Select. A "low" on this input pin enables the communication between the 8255 and
the CPU.

(RD) Read. A "low" on this input pin enables 8255 to send the data or status information to the

5
CPU on the data bus. In essence, it allows the CPU to "read from" the 8255.
(WR) Write. A "low" on this input pin enables the CPU to write data or control words into the
8255.

(A0 and A1) Port Select 0 and Port Select 1. These input signals, in conjunction with the RD
and WR inputs, control the selection of one of the three ports or the control word register. They
are normally connected to the least significant bits of the address bus (A0 and A1).

(RESET) Reset. A "high" on this input initializes the control register to 9Bh and all ports (A,
B, C) are set to the input mode.

A1 A0 SELECTION
0 0 PORT A
0 1 PORT B
1 0 PORT C
1 1 CONTROL

GROUP A AND GROUP B CONTROLS

The functional configuration of each port is programmed by the systems software. In essence,
the CPU "outputs" a control word to the 8255. The control word contains information such as
"mode", "bit set", "bit reset", etc., that initializes the functional configuration of the 8255. Each
of the Control blocks (Group A and Group B) accepts "commands" from the Read/Write
Control logic, receives "control words" from the internal data bus and issues the proper
commands to its associated ports.

PORTS A, B, AND C

The 8255 contains three 8-bit ports (A, B, and C). All can be configured to a wide variety of
functional characteristics by the system software but each has its own special features or
"personality" to further enhance the power and flexibility of the 8255.

Port A One 8-bit data output latch/buffer and one 8-bit data input latch. Both "pull-up" and
"pull-down" bus-hold devices are present on Port A.

Port B One 8-bit data input/output latch/buffer and one 8-bit data input buffer.

6
Port C One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input).
This port can be divided into two 4-bit ports under the mode control. Each 4-bit port contains
a 4-bit latch and it can be used for the control signal output and status signal inputs in
conjunction with ports A and B.

OPERATIONAL MODES OF 8255

There are two basic operational modes of 8255:

• Bit set/reset Mode (BSR Mode).

• Input/Output Mode (I/O Mode).

The two modes are selected on the basis of the value present at the D7 bit of the Control Word
Register. When D7 = 1, 8255 operates in I/O mode and when D7 = 0, it operates in the BSR
mode.

1. BIT SET/RESET (BSR) MODE

The Bit Set/Reset (BSR) mode is applicable to port C only. Each line of port C (PC0 - PC7) can
be set/reset by suitably loading the control word register as shown in Figure 4. BSR mode and
I/O mode are independent and selection of BSR mode does not affect the operation of other
ports in I/O mode.

Fig 3.4: 8255 Control register format for BSR mode

7
• D7 bit is always 0 for BSR mode.
• Bits D6, D5 and D4 are don't care bits.
• Bits D3, D2 and D1 are used to select the pin of Port C.
• Bit D0 is used to set/reset the selected pin of Port C.
• Selection of port C pin is determined as follows:

B3 B2 B1 Bit/pin of port C selected

0 0 0 PC0
0 0 1 PC1
0 1 0 PC2
0 1 1 PC3
1 0 0 PC4
1 0 1 PC5
1 1 0 PC6
1 1 1 PC7

As an example, if it is needed that PC5 be set, then in the control word,

1. Since it is BSR mode, D7 = '0'.

2. Since D4, D5, D6 are not used, assume them to be '0'.
3. PC5 has to be selected, hence, D3 = '1', D2 = '0', D1 = '1'.
4. PC5 has to be set, hence, D0 = '1'.

Thus, as per the above values, 0B (Hex) will be loaded into the Control Word Register (CWR).

D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 1 0 1 1
2. INPUT/OUTPUT MODE

This mode is selected when D7 bit of the Control Word Register is 1. There are three I/O modes:

1. Mode 0 - Simple I/O

2. Mode 1 - Strobed I/O
3. Mode 2 - Strobed Bi-directional I/O

8
 Figure 3. 5: 8255 Control word for I/O mode

• D0, D1, D3, D4 are assigned for lower port C, port B, upper port C and port A
respectively. When these bits are 1, the corresponding port acts as an input port. For
e.g., if D0 = D4 = 1, then lower port C and port A act as input ports. If these bits are 0,
then the corresponding port acts as an output port. For e.g., if D1 = D3
= 0, then port B and upper port C act as output ports as shown in Figure 5.
• D2 is used for mode selection of Group B (port B and lower port C). When D2 = 0,
mode 0 is selected and when D2 = 1, mode 1 is selected.
• D5& D6 are used for mode selection of Group A ( port A and upper port C). The
selection is done as follows:

• As it is I/O mode, D7 = 1.

9
For example, if port B and upper port C have to be initialized as input ports and lower port C
and port A as output ports (all in mode 0):

1. Since it is an I/O mode, D7 = 1.

2. Mode selection bits, D2, D5, D6 are all 0 for mode 0 operation.
3. Port B and upper port C should operate as Input ports, hence, D1 = D3 = 1.
4. Port A and lower port C should operate as Output ports, hence, D4 = D0 = 0.

Hence, for the desired operation, the control word register will have to be loaded with
"10001010" = 8A (hex).

➢ Mode 0 - simple I/O

In this mode, the ports can be used for simple I/O operations without handshaking signals. Port
A, port B provide simple I/O operation. The two halves of port C can be either used together
as an additional 8-bit port, or they can be used as individual 4-bit ports. Since the two halves
of port C are independent, they may be used such that one- half is initialized as an input port
while the other half is initialized as an output port.

The input/output features in mode 0 are as follows:

1. Output ports are latched.

2. Input ports are buffered, not latched.
3. Ports do not have handshake or interrupt capability.
4. With 4 ports, 16 different combinations of I/O are possible.

➢ Mode 0 – input mode

• In the input mode, the 8255 gets data from the external peripheral ports and the CPU
reads the received data via its data bus.
• The CPU first selects the 8255 chip by making CS low. Then it selects the
desired port using A0 and A1 lines.
• The CPU then issues an RD signal to read the data from the external
peripheral device via the system data bus.

➢ Mode 0 - output mode

10
 • In the output mode, the CPU sends data to 8255 via system data bus and then the
external peripheral ports receive this data via 8255 port.
• CPU first selects the 8255 chip by making CS low. It then selects the desired port using
A0 and A1 lines.
CPU then issues a WR signal to write data to the selected port via the system data bus. This
data is then received by the external peripheral device connected to the selected port.
➢ Mode 1

When we wish to use port A or port B for handshake (strobed) input or output operation, we
initialize that port in mode 1 (port A and port B can be initialized to operate in different modes,
i.e., for e.g., port A can operate in mode 0 and port B in mode 1). Some of the pins of port C
function as handshake lines.

For port B in this mode (irrespective of whether is acting as an input port or output port), PC0,
PC1 and PC2 pins function as handshake lines.

If port A is initialized as mode 1 input port, then, PC3, PC4 and PC5 function as handshake
signals. Pins PC6 and PC7 are available for use as input/output lines.

The mode 1 which supports handshaking has following features:

1.
wo ports i.e. port A and B can be used as 8-bit i/o ports.
2.
ach port uses three lines of port c as handshake signal and remaining two signals can
be used as i/o ports.
3.
nterrupt logic is supported.
4.
nput and Output data are latched.

INPUT HANDSHAKING SIGNALS

1. IBF (Input Buffer Full) - It is an output indicating that the input latch contains
information.

2. STB (Strobed Input) - The strobe input loads data into the port latch, which holds
the information until it is input to the microprocessor via the IN instruction.

11
 3. INTR (Interrupt request) - It is an output that requests an interrupt. The INTR pin
becomes a logic 1 when the STB input returns to a logic 1, and is cleared when the
data are input from the port by the microprocessor.

4. INTE (Interrupt enable) - It is neither an input nor an output; it is an internal bit

programmed via the port PC4(port A) or PC2(port B) bit position.

OUTPUT HANDSHAKING SIGNALS

• OBF (Output Buffer Full) - It is an output that goes low whenever data are
output(OUT) to the port A or port B latch. This signal is set to a logic 1 whenever
the ACK pulse returns from the external device.
• ACK (Acknowledge)-It causes the OBF pin to return to a logic 1 level. The ACK
signal is a response from an external device, indicating that it has received the data
from the 82C55 port.

• INTR (Interrupt request) - It is a signal that often interrupts the microprocessor

when the external device receives the data via the signal. this pin is qualified by
the internal INTE(interrupt enable) bit.

• INTE (Interrupt enable) - It is neither an input nor an output; it is an internal bit

programmed to enable or disable the INTR pin. The INTE A bit is programmed
using the PC6 bit and INTE B is programmed using the PC2 bit.

➢ Mode 2

Only group A can be initialized in this mode. Port A can be used for bidirectional handshake
data transfer. This means that data can be input or output on the same eight lines (PA0 - PA7).
Pins PC3 - PC7 are used as handshake lines for port A. The remaining pins of port C (PC0 -
PC2) can be used as input/output lines if group B is initialized in mode 0 or as handshaking for
port B if group B is initialized in mode 1. In this mode, the 8255 may be used to extend the
system bus to a slave microprocessor or to transfer data bytes to and from a floppy disk
controller. Acknowledgement and handshaking signals are provided to maintain proper data
flow and synchronisation between the data transmitter and receiver.

12
INTERFACING 8255 WITH 8085 PROCESSOR

Fig 3.6. Interfacing 8255 with 8085 processor

• The 8255 can be either memory mapped or I/O mapped in the system. In the schematic
shown in above is I/O mapped in the system.

• Using a 3-to-8 decoder generates the chip select signals for I/O mapped devices.

• The address lines A4, A5 and A6 are decoded to generate eight chip select signals
(IOCS-0 to IOCS-7) and in this, the chip select IOCS- 1 is used to select 8255 as
shown in Figure 6.

• The address line A7 and the control signal IO/M (low) are used as enable for the
decoder.

13
• The address line A0 of 8085 is connected to A0 of 8255 and A1 of 8085 is connected
to A1 of 8255 to provide the internal addresses.

• The data lines D0-D7 are connected to D0-D7 of the processor to achieve parallel data
transfer.

• The I/O addresses allotted to the internal devices of 8255 are listed in table.

14
8253(8254) PROGRAMMABLE INTERVAL TIMER:

The 8254 programmable Interval timer consists of three independent 16-bit programmable
counters (timers). Each counter is capable of counting in binary or binary coded decimal. The
maximum allowable frequency to any counter is 10MHz. This device is useful whenever the
microprocessor must control real-time events. The timer in a personal computer is an 8253. To
operate a counter a 16-bit count is loaded in its register and on command, it begins to decrement
the count until it reaches 0. At the end of the count it generates a pulse, which interrupts the
processor. The count can count either in binary or BCD Each counter in the block diagram has
3 logical lines connected to it. Two of these lines, clock and gate, are inputs. The third, labeled
OUT is anoutput.

Fig 3.16 Block Diagram of 8253 programmable interval timer

Data bus buffer- It is a communication path between the timer and the microprocessor. The
buffer is 8-bit and bidirectional. It is connected to the data bus of the microprocessor. Read
/write logic controls the reading and the writing of the counter registers. Control word register,
specifies the counter to be used and either a Read or a write operation. Data is transmitted or
received by the buffer upon execution of INPUT instruction from CPU as shown in figure 16.
The data bus buffer has three basic functions,
• Programming the modes of 8253.
• Loading the count value in times

15
 READING THE COUNT VALUE FROM TIMERS.

Pin Diagram of 8253

The data bus buffer is connected to microprocessor using D7 – D0 pins which are also
bidirectional. The data transfer is through these pins. These pins will be in high-impedance (or
this state) condition until the 8253 is selected by a LOW or CS and either the read operation
requested by a LOW RD on the input or a write operation WR
requested by the input going LOW.

READ/ WRITE LOGIC:

It accepts inputs for the system control bus and in turn generation the control signals for overall
device operation. It is enabled or disabled by CS so that no operation can occur to change the
function unless the device has been selected as the system logic.

CS :
The chip select input is used to enable the communicate between 8253 and the microprocessor
by means of data bus. A low an CS enables the data bus buffers, while
a high disables the buffer. The CS input does not have any effect on the operation of three
times once they have been initialized. The normal configuration of a system employs an decode
logic which actives CS line, whenever a specific set of addresses that correspond to 8253 appear
on the address bus.

RD & WR :

The read ( RD ) and write WR pins central the direction of data transfer on the 8-bit bus. When
the input RD pin is low. Then CPU is inputting data from 8253 in the form of counter value.

16
When WR pins is low, then CPU is sending data to 8253 in the form of mode information or
loading counters. The RD & WR should not both be low simultaneously. When RD & WR pins
are HIGH, the data bus buffer is disabled.
A0 & A1:
These two input lines allow the microprocessor to specify which one of the internal register in
the 8253 is going to be used for the data transfer. Fig shows how these two lines are used to
select either the control word register or one of the 16-bit counters.

CONTROL WORD REGISTER:

It is selected when A0 and A1 . It the accepts information from the data bus buffer and stores
it in a register. The information stored in then register controls the operation mode of each
counter, selection of binary or BCD counting and the loading of each counting and the loading
of each count register. This register can be written into, no read operation of this content is
available.
COUNTERS:

Each of the times has three pins associated with it. These are CLK (CLK) the gate (GATE) and
the output (OUT).

17
CLK:

This clock input pin provides 16-bit times with the signal to causes the times to decrement
maxm clock input is 2.6MHz. Note that the counters operate at the negative edge (H1 to L0) of
this clock input. If the signal on this pin is generated by a fixed oscillator then the user has
implemented a standard timer. If the input signal is a string of randomly occurring pulses, then
it is called implementation of a counter.

GATE:

The gate input pin is used to initiate or enable counting. The exact effect of the gate signal
depends on which of the six modes of operation is chosen.

OUTPUT:

The output pin provides an output from the timer. It actual use depends on the mode of operation
of the timer. The counter can be read —in the fly‖ without inhibiting gate pulse or clock input.

CONTROL REGISTER

MODES OF OPERATION

Mode 0 Interrupt on terminal count

Mode 1 Programmable one shot
Mode 2 Rate Generator
Mode 3 Square wave rate Generator
Mode 4 Software triggered strobe
Mode 5 Hardware triggered strobe

Mode 0: The output goes high after the terminal count is reached. The counter stops if the Gate
is low.. The timer count register is loaded with a count (say 6) when the WR line is made low
by the processor. The counter unit starts counting down with each clock pulse. The output goes
high when the register value reaches zero. In the mean time if the GATE is made low the count
is suspended at the value(3) till the GATE is enabled again .

18
CLK

WR

2 1
OUT

GATE

Mode 0 count when Gate is high (enabled)

CLK

WR

2 1
OUT

GATE

Mode 0 count when Gate is low temporarily (disabled) Mode 1 Programmable mono-shot

The output goes low with the Gate pulse for a predetermined period depending on the counter.
The counter is disabled if the GATE pulse goes momentarily [Link] counter register is loaded
with a count value as in the previous case (say 5). The output responds to the GATE input and
goes low for period that equals the count down period of the register (5 clock pulses in this
period). By changing the value of this count the duration of the output pulse can be changed.
If the GATE becomes low before the count down is completed then the counter will be

19
suspended at that state as long as GATE is low. Thus it works as a mono-shot.

CLK

WR

GATE (trigger)

5 4 3 2 1
OUT

Mode 1 The Gate goes high. The output goes low for the period depending on the count

CLK

WR

GATE (trigger)

OUT

Mode 1 The Gate pulse is disabled momentarily causing the counter to stop.

Mode 2 Programmable Rate Generator

In this mode it operates as a rate generator. The output goes high for a period that equals the

20
time of count down of the count register (3 in this case). The output goes low exactly for one
clock period before it becomes high again. This is a periodic operation.

CLK

WR

GATE

2 1

OUT

Mode 2 Operation when the GATE is kept high

CLK

WR

GATE

OUT 2 1

Mode 2 operation when the GATE is disabled momentarily.

Mode 3 Programmable Square Wave Rate Generator

It is similar to Mode 2 but the output high and low period is symmetrical. The outputgoes high
after the count is loaded and it remains high for period which equals the count down period of
the counter register. The output subsequently goes low for an equal period and hence generates
a symmetrical square wave unlike Mode 2. The GATE has no role here.

21
CLK

WR
n=

OUT (n=5)

Mode3 Operation: Square Wave generator

Mode 4 Software Triggered Strobe

In this mode after the count is loaded by the processor the count down starts. The output goes
low for one clock period after the count down is complete. The count down can be suspended
by making the GATE low . This is also called a software triggered strobe as the count down is
initiated by a program.

CLK

WR

OUT

2 1

Mode 4 Software Triggered Strobe when GATE is high

Mode 5 Hardware Triggered Strobe

The count is loaded by the processor but the count down is initiated by the GATE pulse. The
transition from low to high of the GATE pulse enables count down. The output goes low for
one clock period after the count down is complete.

22
CLK

WR

GATE

OUT
5 4 3 2 1

Mode 5 Hardware Triggered Strobe

PROGRAMMABLE INTERRUPT CONTROLLER-8259

FEATURES OF 8259

1. 8086, 8088 Compatible

2. MCS-80, MCS-85 Compatible
3. Eight-Level Priority Controller
4. Expandable to 64 Levels
5. Programmable Interrupt Modes
6. Individual Request Mask Capability
7. Single +5V Supply (No Clocks)
8. Available in 28-Pin DIP and 28-Lead PLCC Package
9. Available in EXPRESS
10. Standard Temperature Range
11. Extended Temperature Range

The Intel 8259A Programmable Interrupt Controller handles up to eight vectored priority
interrupts for the CPU. It is cascadable for up to 64 vectored priority interrupts without
additional circuitry. It is packaged in a 28-pin DIP, uses NMOS technology and requires a

23
single a5V supply. Circuitry is static, requiring no clock input. The 8259A is designed to
minimize the software and real time overhead in handling multi-level priority interrupts. It has
several modes, permitting optimization for a variety of system requirements. The 8259A is
fully upward compatible with the Intel 8259. Software originally written for the 8259 will
operate the 8259A in all 8259 equivalent modes (MCS-80/85, Non-Buffered, Edge Triggered).
Pin Diagram of 8259 is shown in figure 17.

Fig.3.17 Pin Diagram of 8259

PIN DESCRIPTION OF 8259

24
25
 Fig.3. 18 Block Diagram of 8259

A more desirable method would be one that would allow the microprocessor to be executing
its main program and only stop to service peripheral devices when it is told to do so by the
device itself. In effect, the method would provide an external asynchronous input that would
inform the processor that it should complete whatever instruction that is currently being
executed and fetch a new routine that will service the requesting device. Once this servicing is
complete, however, the processor would resume exactly where it left off. This method is called
Interrupt. It is easy to see that system throughput would drastically increase, and thus more
tasks could be assumed by the micro-computer to further enhance its cost effectiveness. Block
Diagram of 8259 is shown in figure 3.18.

The Programmable Interrupt Controller (PIC) functions as an overall manager in an Interrupt-

Driven system environment. It accepts requests from the peripheral equipment, determines
which of the in-coming requests is of the highest importance (priori-ty), ascertains whether the
incoming request has a higher priority value than the

26
level currently being serviced, and issues an interrupt to the CPU based on this determination.

The 8259A is a device specifically designed for use in real time, interrupt driven
microcomputer systems. It manages eight levels or requests and has built-in features for
expandability to other 8259A's (up to 64 levels). It is programmed by the system's software as
an I/O peripheral. A selection of priority modes is available to the programmer so that the
manner in which the requests are processed by the 8259A can be configured to match his
system requirements. The priority modes can be changed or reconfigured dynamically at any
time during the main program. This means that the complete interrupt structure can be defined
as required, based on the total system environment.

INTERRUPT REQUEST REGISTER (IRR) AND IN-SERVICE REGISTER (ISR)

The interrupts at the IR input lines are handled by two registers in cascade, the Interrupt
Request Register (IRR) and the In-Service (ISR). The IRR is used to store all the interrupt
levels which are requesting service; and the ISR is used to store all the interrupt levels which
are being serviced.

PRIORITY RESOLVER

This logic block determines the priorites of the bits set in the IRR. The highest priority is
selected and strobed into the corresponding bit of the ISR during INTA pulse.

INTERRUPT MASK REGISTER (IMR)

The IMR stores the bits which mask the interrupt lines to be masked. The IMR operates on the
IRR. Masking of a higher priority input will not affect the interrupt request lines of lower
quality.

INT (INTERRUPT)

This output goes directly to the CPU interrupt input. The VOH level on this line is designed to
be fully compatible with the 8080A, 8085A and 8086 input levels.

27
INTA (INTERRUPT ACKNOWLEDGE)

INTA pulses will cause the 8259A to release vectoring information onto the data bus. The
format of this data depends on the system mode (mPM) of the 8259A.

DATA BUS BUFFER

This 3-state, bidirectional 8-bit buffer is used to inter-face the 8259A to the system Data Bus.
Control words and status information are transferred through the Data Bus Buffer.

READ/WRITE CONTROL LOGIC

The function of this block is to accept Output commands from the CPU. It contains the
Initialization Command Word (ICW) registers and Operation Command Word (OCW)
registers which store the various control formats for device operation. This function block also
allows the status of the 8259A to be transferred onto the Data Bus.

CS (CHIP SELECT)

A LOW on this input enables the 8259A. No reading or writing of the chip will occur unless
the device is selected.

WR (WRITE)

A LOW on this input enables the CPU to write con-trol words (ICWs and OCWs) to the 8259A.

RD (READ)

A LOW on this input enables the 8259A to send the status of the Interrupt Request Register
(IRR), In Service Register (ISR), the Interrupt Mask Register (IMR), or the Interrupt level onto
the Data Bus.
A0

This input signal is used in conjunction with WR and RD signals to write commands into the
various command registers, as well as reading the various status registers of the chip. This line
can be tied directly to one of the address lines.

INTERRUPT SEQUENCE

28
The powerful features of the 8259A in a microcomputer system are its programmability and
the interrupt routine addressing capability. The latter allows direct or indirect jumping to the
specific interrupt routine requested without any polling of the interrupting devices. The normal
sequence of events during an interrupt depends on the type of CPU being used.

The events occur as follows in an MCS-80/85 sys-tem:

• One or more of the INTERRUPT REQUEST lines (IR7±0) are raised high, setting
the correspond-ing IRR bit(s).
• The 8259A evaluates these requests, and sends an INT to the CPU, if appropriate.
• The CPU acknowledges the INT and responds with an INTA pulse.

• Upon receiving an INTA from the CPU group, the highest priority ISR bit is set,
and the correspond-ing IRR bit is reset. The 8259A will also release a CALL
instruction code (11001101) onto the 8-bit Data Bus through its D7±0 pins.
• This CALL instruction will initiate two more INTA pulses to be sent to the 8259A
from the CPU group.
• These two INTA pulses allow the 8259A to re-lease its preprogrammed
subroutine address onto the Data Bus. The lower 8-bit address is released at the
first INTA pulse and the higher 8-bit address is released at the second INTA pulse.
• This completes the 3-byte CALL instruction re-leased by the 8259A. In the AEOI
mode the ISR bit is reset at the end of the third INTA pulse. Otherwise, the ISR
bit remains set until an appropriate EOI command is issued at the end of the interrupt
sequence.
• The events occurring in an 8086 system are the same until step 4.

• Upon receiving an INTA from the CPU group, the highest priority ISR bit is set
and the corresponding IRR bit is reset. The 8259A does not drive the Data Bus
during this cycle.

• The 8086 will initiate a second INTA pulse. During this pulse, the 8259A releases
an 8-bit pointer onto the Data Bus where it is read by the CPU.

• This completes the interrupt cycle. In the AEOI mode the ISR bit is reset at the
end of the second INTA pulse. Otherwise, the ISR bit remains set until an
appropriate EOI command is issued at the end of the interrupt subroutine.

If no interrupt request is present at step 4 of either sequence (i.e., the request was too short in
duration) the 8259A will issue an interrupt level 7. Both the vectoring bytes and the CAS lines

29
will look like an interrupt level 7 was requested.

When the 8259A PIC receives an interrupt, INT be-comes active and an interrupt acknowledge
cycle is started. If a higher priority interrupt occurs between the two INTA pulses, the INT line
goes inactive immediately after the second INTA pulse. After an un- specified amount of time
the INT line is activated again to signify the higher priority interrupt waiting for service. This
inactive time is not specified and can vary between parts. The designer should be aware of this
consideration when designing a sys-tem which uses the 8259A. It is recommended that proper
asynchronous design techniques be followed.

INITIALIZATION COMMAND WORDS

Whenever a command is issued with A0 e 0 and D4 e 1, this is interpreted as Initialization

Command Word 1 (ICW1). ICW1 starts the initialization sequence during which the following
automatically occur.

• The edge sense circuit is reset, which means that following initialization, an interrupt
request (IR) input must make a low-to-high transition to generate an interrupt.
• The Interrupt Mask Register is cleared.

• IR7 input is assigned priority 7.

• The slave mode address is set to 7.

• Special Mask Mode is cleared and Status Read isset to IRR.

• If IC4 e 0, then all functions selected in ICW4are set to zero. (Non-Buffered mode(,no
Auto-EOI, MCS-80, 85 system).

• Initialization Command Word Format is as shown in figure 3.19.

30
31
Fig 3.19 . Initialization Command Word Format

32
OPERATION COMMAND WORDS

After the Initialization Command Words (ICWs) are programmed into the 8259A, the chip is
ready to accept interrupt requests at its input lines. However, during the 8259A operation, a
selection of algorithms can command the 8259A to operate in various modes through the
Operation Command Words (OCWs). Operation Command Word format is as shown in figure
20

Fig . Operational Control Words

33
 Fig 3.20 Operation Command Word Format

DMA CONTROLLER 8257

The Direct Memory Access or DMA mode of data transfer is the fastest amongstall the modes
of data transfer. In this mode, the device may transfer data directly to/from memory without
any interference from the CPU. The device requests the CPU (through aDMA controller) to
hold its data, address and control bus, so that the device may transfer data directly to/from
memory. The DMA data transfer is initiated only after receiving HLDA signal from the CPU.
Intel’s 8257 is a four channel DMA controller designed to be interfaced with their family of
microprocessors. The 8257, on behalf of the devices, requests the CPU for bus access using
local bus request input i.e. HOLD in minimum mode. In maximum mode of the microprocessor
RQ/GT pin is used as bus request input. On receiving the HLDA signal (in minimum mode) or
RQ/GT signal (in maximum mode) from the CPU, the requesting devices gets the access of
the bus, and it completes the required number of DMA cycles for the data transfer and then
hands over the control of the bus back to the CPU.

INTERNAL ARCHITECTURE OF 8257

The internal architecture of 8257 is shown in figure. The chip support four DMA channels, i.e.
four peripheral devices can independently request for DMA data transfer

34
through these channels at a time. The DMA controller has 8-bit internal data buffer, a read/write
unit, a control unit, a priority resolving unit along with a set of registers.

The 8257 performs the DMA operation over four independent DMA channels. Each of four
channels of 8257 has a pair of two 16-bit registers, viz. DMA address register and terminal
count register.

There are two common registers for all the channels, namely, mode set register and status
register. Thus there are a total of ten registers. The CPU selects one of these ten registers using
address lines Ao-A3. Table shows how the Ao-A3 bits may be used for selecting one of these
registers.

DMA ADDRESS REGISTER

Each DMA channel has one DMA address register. The function of this register is to store the
address of the starting memory location, which will be accessed by the DMA channel. Thus
the starting address of the memory block which will be accessed by the device is first loaded
in the DMA address register of the channel. The device that wants to transfer data over a DMA
channel, will access the block of the memory with the starting address stored in the DMA
Address Register.

TERMINAL COUNT REGISTER

Each of the four DMA channels of 8257 has one terminal count register (TC). This 16-bit
register is used for ascertaining that the data transfer through a DMA channel ceases or stops
after the required number of DMA cycles. The low order 14-bits of the terminal count register
are initialized with the binary equivalent of the number of required DMA cycles minus one.
After each DMA cycle, the terminal count register content will be decremented by one and
finally it becomes zero after the required number of DMA cycles are over. The bits14 and 15
of this register indicate the type of the DMA operation (transfer). If the device wants to write
data into the memory, the DMA operation is called DMA write operation. Bit 14 of the register
in this case will be set to one and bit 15 will be set to zero.

35
STATUS REGISTER

The status register of 8257 is shown in figure. The lower order 4-bits of this register contain
the terminal count status for the four individual channels. If any of these bits is set, it indicates
that the specific channel has reached the terminal count condition.

These bits remain set till either the status is read by the CPU or the 8257 is reset. The update
flag is not affected by the read operation. This flag can only be cleared by resetting 8257 or by
resetting the auto load bit of the mode set register. If the update flag is set, the contents of the
channel 3 registers are reloaded to the corresponding registers of channel 2 whenever the
channel 2 reaches a terminal count condition, after transferring one block and the next block is
to be transferred using the autoload feature of 8257.

The update flag is set every time, the channel 2 registers are loaded with contents of the channel
3 registers. It is cleared by the completion of the first DMA cycle of the new block. This register
can only read.

DATA BUS BUFFER, READ/WRITE LOGIC, CONTROL UNIT AND PRIORITY

RESOLVER

The 8-bit. Tristate, bidirectional buffer interfaces the internal bus of 8257 with the external
system bus under the control of various control signals. In the slave mode, the read/write logic
accepts the I/O Read or I/O Write signals, decodes the Ao-A3 lines and either writes the
contents of the data bus to the addressed internal register or reads the

36
contents of the selected register depending upon whether IOW or IOR signal is activated.

In master mode, the read/write logic generates the IOR and IOW signals to control the data
flow to or from the selected peripheral. The control logic controls the sequences of operations
and generates the required control signals like AEN, ADSTB, MEMR, MEMW, TC and
MARK along with the address lines A4-A7, in master mode. The priority resolver resolves the
priority of the four DMA channels depending upon whether normal priority or rotating priority
is programmed.

SIGNAL DESCRIPTION OF 8257

DRQ0-DRQ3

These are the four individual channel DMA request inputs, used by the peripheral devices for
requesting the DMA services. The DRQ0 has the highest priority while DRQ3 has the lowest
one, if the fixed priority mode is selected.

DACK0-DACK3:

These are the active-low DMA acknowledge output lines which inform the requesting
peripheral that the request has been honoured and the bus is relinquished by the CPU. These
lines may act as strobe lines for the requesting devices

.Pin Description of 8257

37
 Architecture of 8257
Do-D7:

These are bidirectional, data lines used to interface the system bus with theinternal data bus of
8257. These lines carry command words to 8257 and status wordfrom 8257, in slave mode, i.e.
under the control of [Link] data over these lines may be transferred in both the directions.
When the 8257 is thebus master (master mode, i.e. not under

38
CPU control), it uses Do-D7 lines to send higherbyte of the generated address to the latch. This
address is further latched using ADSTBsignal. the address is transferred over Do-D7 during
the first clock cycle of the DMAcycle. During the rest of the period, data is available on the
data bus.

IOR:

This is an active-low bidirectional tristate input line that acts as an input in theslave mode. In
slave mode, this input signal is used by the CPU to read internal registersof [Link] line acts
output in master mode. In master mode, this signal is used to readdata from a peripheral during
a memory write cycle.

IOW:

This is an active low bidirection tristate line that acts as input in slave mode to load the
contents of the data bus to the 8-bit mode register or upper/lower byte of a 16-bit DMA address
register or terminal count register. In the master mode, it is a control output that loads the data
to a peripheral during DMA memory read cycle (write to peripheral).

CLK:

This is a clock frequency input required to derive basic system timings for theinternal operation
of 8257.

RESET :

This active-high asynchronous input disables all the DMA channels by clearing the mode
register and tristates all the control lines.

Ao-A3:

These are the four least significant address lines. In slave mode, they act as input which select
one of the registers to be read or written. In the master mode, they are the four least significant
memory address output lines generated by 8257.

39
CS:

This is an active-low chip select line that enables the read/write operations from/to 8257, in
slave mode. In the master mode, it is automatically disabled to prevent the chip from getting
selected (by CPU) while performing the DMA operation.

A4-A7:

This is the higher nibble of the lower byte address generated by 8257 during the master mode
of DMA operation.

READY:

This is an active-high asynchronous input used to stretch memory read and writecycles of 8257
by inserting wait states. This is used while interfacing slower peripherals.

HRQ:

The hold request output requests the access of the system bus. In the noncascaded8257 systems,
this is connected with HOLD pin of CPU. In the cascade mode, this pin of a slave is connected
with a DRQ input line of the master 8257, while that of the master is connected with HOLD
input of the CPU.

HLDA :

The CPU drives this input to the DMA controller high, while granting the bus tothe device.
This pin is connected to the HLDA output of the CPU. This input, if high, indicates to the DMA
controller that the bus has been granted to the requesting peripheral by the CPU.

MEMR:

This active –low memory read output is used to read data from the addressed memory locations
during DMA read cycles.

MEMW :
This active-low three state output is used to write data to the addressed memory location during
DMA write operation.

40
ADST :

This output from 8257 strobes the higher byte of the memory address generated by
the DMA controller into the latches.

AEN:

This output is used to disable the system data bus and the control the bus driven by
the CPU, this may be used to disable the system address and data bus by using the
enable input of the bus drivers to inhibit the non-DMA devices from responding
during DMA operations. If the 8257 is I/O mapped, this should be used to disable
the other I/O devices, when the DMA controller addresses is on the address bus.

TC:

Terminal count output indicates to the currently selected peripherals that thepresent
DMA cycle is the last for the previously programmed data block. If the TC STOP bit
in the mode set register is set, the selected channel will be disabled at the end of the
DMA cycle. The TC pin is activated when the 14-bit content of the terminal count
register of the selected channel becomes equal to zero. The lower order 14 bits of the
terminal count register are to be programmed with a 14-bit equivalent of (n-1), if n
is the desired number of DMA cycles.

MARK:

The modulo 128 mark output indicates to the selected peripheral that the current
DMA cycle is the 128th cycle since the previous MARK output. The mark will be
activated after each 128 cycles or integral multiples of it from the beginning if the
data block (the first DMA cycle), if the total number of the required DMA cycles
(n) is completely divisible by 128.

Vcc:

This is a +5v supply pin required for operation of the circuit. GND: This is a return
line for the supply (ground pin of the IC).