ANALOG LAYOUT DESIGN

COMPLETE HANDBOOK
Backend VLSI Engineering
Beginner to Industry Expert

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Compiled by Senior Analog Layout Engineers from

NVIDIA • Intel • Qualcomm • Texas Instruments • Broadcom

18 Parts | 500+ Interview Q&A | Industry Projects | Career Roadmap

Analog Layout Design Handbook — Confidential Training Material | Page 1

Analog Layout Design Handbook — Confidential Training Material | Page 2
 PART 1
SEMICONDUCTOR FUNDAMENTALS

Part 1: Semiconductor Fundamentals

Before you touch a layout tool, you need to understand the physics of the devices you're placing and routing.
This part builds the foundation from atomic structure to PN junctions — the building blocks of every circuit you
will ever lay out.

1.1 Atomic Structure

Every solid material is made of atoms. An atom has a nucleus (protons + neutrons) surrounded by electrons in
shells (orbitals). The outermost shell is called the valence shell.
Key Concept: Silicon (Si) has 4 valence electrons. This is why silicon is ideal for semiconductors — it can form 4
covalent bonds, creating a stable crystal lattice.
In a pure silicon crystal, each atom shares its 4 electrons with 4 neighboring atoms forming a diamond cubic
lattice. At 0K, all electrons are bound — no free carriers exist.
📌 NOTE: Silicon is the most common semiconductor. Germanium (Ge) and Gallium Arsenide (GaAs/GaN) are also
used, especially in RF and power applications (Qualcomm RF chips use GaN).

1.2 Energy Bands

When billions of atoms come together, discrete energy levels broaden into energy bands:
• Valence Band (VB): Highest filled energy band. Electrons here are bound to atoms.
• Conduction Band (CB): Lowest empty energy band. Electrons here are free to move.
• Band Gap (Eg): Energy gap between VB and CB. Determines material type.
Eg(Si) = 1.12 eV at 300K | Eg(Ge) = 0.67 eV | Eg(GaAs) = 1.42 eV |
Eg(SiO2) = ~9 eV
Physical intuition: Think of VB as a parking lot (full, no movement) and CB as a highway (empty, free movement).
The band gap is the wall between them.
Conductors: Overlapping VB and CB — electrons always free (metals: Al, Cu, W used in interconnects)
Insulators: Large Eg (>5 eV) — electrons cannot cross gap (SiO2 used as gate oxide)
Semiconductors: Moderate Eg (0.5–3 eV) — conductivity controllable by doping or applied fields

1.3 Intrinsic Semiconductors

Pure silicon with no impurities. At room temperature (300K), thermal energy breaks some bonds, generating
electron-hole pairs.
ni(Si, 300K) ≈ 1.5 × 10^10 cm^-3

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 ni² = Nc × Nv × exp(-Eg/kT) [mass action law]
Carriers: Electrons (n) in CB and Holes (p) in VB. Holes are vacancies that behave like positive charges.
For intrinsic: n = p = ni → n × p = ni²
🎯 INTERVIEW TIP: NVIDIA/Intel often ask: 'Why does intrinsic carrier concentration increase with temperature?'
Answer: Thermal energy breaks more bonds → more electron-hole pairs → ni increases exponentially. This is why
analog circuits are temperature-sensitive!

1.4 Extrinsic Semiconductors (Doping)

Adding controlled impurities (dopants) to silicon dramatically increases conductivity and controls carrier type.

N-Type Doping (Donors)

Add Group V atoms (Phosphorus P, Arsenic As, Antimony Sb). They have 5 valence electrons — 4 bond with Si, 1
is donated to CB.
n ≈ ND (donor concentration) | p = ni²/ND
• Majority carriers: Electrons
• Minority carriers: Holes
• Fermi level moves toward conduction band

P-Type Doping (Acceptors)

Add Group III atoms (Boron B, Indium In). They have 3 valence electrons — create holes in VB.
p ≈ NA (acceptor concentration) | n = ni²/NA
• Majority carriers: Holes
• Minority carriers: Electrons
• Fermi level moves toward valence band
📌 NOTE: In layout, NMOS transistors are formed in P-type substrate (or P-well). PMOS transistors are formed in N-
well. Understanding doping is critical for understanding guard rings and latch-up!
🎯 INTERVIEW TIP: Qualcomm Interview: 'What is the difference between n-type and p-type substrate?' Know doping
concentrations, carrier types, and implications for well formation.

1.5 PN Junction
When P-type and N-type semiconductors are joined, a PN junction forms — the fundamental building block of
diodes, BJTs, and MOSFETs.

Formation of Depletion Region

• Electrons from N-side diffuse into P-side (concentration gradient drives diffusion)
• Holes from P-side diffuse into N-side
• Recombination at junction leaves behind ionized donors (+) on N-side and ionized acceptors (-) on P-side
• This charged region is the Depletion Region (W_dep)
• Electric field builds up opposing further diffusion → equilibrium reached
Built-in Potential: Vbi = (kT/q) × ln(NA × ND / ni²)
At room temperature: Vbi(Si) ≈ 0.6–0.7V

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 Depletion Width: W = sqrt(2ε/q × Vbi × (NA+ND)/(NA×ND))

Depletion Region Width

xn = W × NA/(NA + ND) [penetration into N-side]
xp = W × ND/(NA + ND) [penetration into P-side]
Physical insight: The depletion width penetrates more into the lightly doped side. This is critical for
understanding MOSFET short-channel effects.

1.6 Drift and Diffusion Currents

Drift Current
Current due to electric field. Carriers move in response to applied field E.
Jdrift = q(n×μn + p×μp) × E
μn(Si): ~1400 cm²/V·s (electron mobility)
μp(Si): ~450 cm²/V·s (hole mobility)
NMOS has higher drive current than PMOS because electron mobility > hole mobility by ~3×. This is why in
CMOS, PMOS width is typically 2–3× larger than NMOS to match drive strength.

Diffusion Current
Current due to concentration gradient. Carriers diffuse from high concentration to low.
Jdiff = q×Dn×(dn/dx) - q×Dp×(dp/dx)
Einstein Relation: Dn/μn = Dp/μp = kT/q = VT (thermal voltage)
At 300K: VT = kT/q = 26 mV

1.7 Diode Operation

Forward Bias
Apply positive voltage to P-side, negative to N-side. Reduces barrier → large current flows.
I = IS × (exp(V/VT) - 1) [Shockley equation]
IS = saturation current ~ 10^-15 A for Si

Reverse Bias
Apply negative voltage to P-side. Increases barrier → only tiny reverse saturation current flows.
• Depletion width increases with reverse bias
• Junction capacitance decreases (used in varactors for PLL VCO tuning!)

Diode Capacitances
Junction Capacitance (Cj): Depletion charge stored at junction
Cj = Cj0 / (1 - V/Vbi)^m where m = 0.5 for abrupt junction
Diffusion Capacitance (Cd): Minority carrier charge storage in quasi-neutral regions (forward bias only)
Layout implication: Every drain/source diffusion of a MOSFET has junction capacitance. Minimizing diffusion area
reduces parasitic Cdb and Csb, improving speed.

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 🎯 INTERVIEW TIP: Texas Instruments asks: 'How does reverse bias affect junction capacitance?' Answer: Increasing
reverse bias widens depletion region → larger charge per unit voltage change... wait, no — wider depletion means
larger plate separation → Cj = εA/W decreases. TI uses varactors (reverse-biased diodes) in PLLs for VCO frequency
tuning.

1.8 Key Summary Table — Semiconductor Basics

Parameter Formula/Value Layout Relevance

Intrinsic Carrier (ni) 1.5×10¹⁰ cm⁻³ @ 300K Leakage current increases with ni →
temperature sensitivity

Thermal Voltage (VT) kT/q = 26 mV @ 300K Sets minimum operating voltages for
bias circuits

Electron Mobility (μn) ~1400 cm²/V·s NMOS faster → size PMOS 2-3× wider

Hole Mobility (μp) ~450 cm²/V·s PMOS slower → need larger devices

Built-in Potential (Vbi) ~0.7V for Si Determines threshold voltage, body

effect

Junction Capacitance Cj0/(1-V/Vbi)^m Parasitic at drain/source — minimize

diffusion area

Analog Layout Design Handbook — Confidential Training Material | Page 6

 PART 2
MOSFET FUNDAMENTALS

Part 2: MOSFET Fundamentals

The MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is the heart of all modern ICs. As an analog
layout engineer, you must understand MOSFETs at a deep physical level — how they work, what degrades them,
and how layout choices directly impact their performance.

2.1 MOSFET Structure

An NMOS transistor has:
• P-type substrate (body/bulk)
• N+ source and drain diffusions (heavily doped)
• Gate oxide (SiO2 or High-k dielectric) above channel
• Polysilicon or metal gate above gate oxide
• Four terminals: Gate (G), Drain (D), Source (S), Body (B)
Physical dimensions:
Channel Length (L): Distance from source to drain edge under gate
Channel Width (W): Perpendicular to current flow
Oxide Thickness (tox): Gate insulator thickness (e.g., ~1.5nm at 7nm
node)
Key ratio: W/L ratio determines drive strength and speed. Doubling W doubles current; halving L also increases
current but worsens many effects.
📌 NOTE: In layout, the drawn W and L may differ from electrical W and L due to enclosures, biases, and process
effects. Always account for layout-dependent effects (LDE).

2.2 Threshold Voltage (Vth)

Vth is the gate voltage at which the channel inverts (starts conducting). It's one of the most critical device
parameters.
Vth = VFB + 2φF + sqrt(2εsi×q×NA×2φF) / Cox
Where:
• VFB = Flat-band voltage (depends on gate-oxide charge, work function difference)
• φF = Fermi potential = (kT/q)×ln(NA/ni)
• Cox = Gate oxide capacitance = εox/tox
• NA = Body doping concentration

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What Affects Vth?
Factor Effect on Vth Layout Impact

↑ NA (body doping) ↑ Vth Heavier doped P-well → higher NMOS Vth

↓ tox (thinner oxide) ↓ Vth (more gate control) Scaled nodes have thinner ox → better control but
leakage

↑ VBS (body bias) ↑ Vth (Body Effect) Float body or connect to supply in layout

↓ L (shorter channel) ↓ Vth (DIBL/SCE) Short devices have lower Vth → mismatch risk

Temperature ↑ ↓ Vth (~-2mV/°C) Circuits must work at Tmax = 125°C or 150°C

2.3 Regions of Operation

Cutoff Region (VGS < Vth)
Device is OFF. Only subthreshold leakage flows. In digital, this is the '0' state. In analog, we exploit subthreshold
for ultra-low power designs (IoT).
ID(subthreshold) = ID0 × exp(VGS/(n×VT)) × (1 - exp(-VDS/VT))

Linear/Triode Region (VGS > Vth, VDS < VGS - Vth)

Channel exists from source to drain. Device acts like a voltage-controlled resistor.
ID = μn×Cox×(W/L) × [(VGS-Vth)×VDS - VDS²/2]
For small VDS: ID ≈ μn×Cox×(W/L) × (VGS-Vth) × VDS → Ron =
1/(μn×Cox×(W/L)×(VGS-Vth))
Layout use: Pass gates, switches, and current-steering elements often operate in triode.

Saturation Region (VGS > Vth, VDS ≥ VGS - Vth)

Channel pinches off at drain. Current becomes nearly independent of VDS — acts as current source.
ID = (μn×Cox/2) × (W/L) × (VGS - Vth)² [long-channel]
ID = (1/2)×kn×(W/L)×(VGS-Vth)² where kn = μn×Cox
This is the primary region for analog amplifiers. The transconductance gm determines gain.
gm = ∂ID/∂VGS = μn×Cox×(W/L)×(VGS-Vth) = sqrt(2×μn×Cox×(W/L)×ID)
ro = 1/(λ×ID) [output resistance due to channel length modulation]
Intrinsic Gain: Av = -gm×ro = -gm/(λ×ID)
🎯 INTERVIEW TIP: NVIDIA/Qualcomm interview: 'What is gm and why does it matter in analog layout?' gm × ro =
intrinsic gain of a MOSFET. Higher gm with lower ID means better power efficiency. Layout affects gm through W/L
and matching.

2.4 Body Effect

When source and body are at different potentials, Vth increases — this is the body effect.
Vth(VSB) = Vth0 + γ×(sqrt(|2φF + VSB|) - sqrt(|2φF|))
γ = sqrt(2×εsi×q×NA) / Cox [body effect coefficient, ~0.3–0.5 V^0.5]

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Layout implication:
• In stacked transistors (cascode), the source of upper device is not at VSS → body effect increases Vth
• Always connect body to appropriate supply (NMOS body to VSS, PMOS body to VDD) unless deliberately
floating for specific design
• In deep N-wells, NMOS body can be isolated and biased independently — useful for reducing substrate
coupling
⚠️COMMON MISTAKE: Forgetting to connect body taps (substrate contacts) is a common layout mistake that leads
to latch-up and floating body effects.

2.5 Channel Length Modulation

In saturation, the pinch-off point moves toward the source as VDS increases → effective channel shortens → ID
increases slightly.
ID = (kn/2)×(W/L)×(VGS-Vth)² × (1 + λ×VDS)
λ ≈ 1/(VA) [λ = channel length modulation parameter]
VA ∝ L [Early voltage proportional to channel length]
Layout implication: Longer channel length L → larger VA → better output impedance ro. Analog circuits use long-
L devices (e.g., 2× minimum L) for higher gain and better matching.
🎯 INTERVIEW TIP: Why do analog designers use longer channel devices? To increase VA (Early voltage), improving
output resistance ro = VA/ID. Also reduces Vth mismatch (Pelgrom's law: σVth ∝ 1/sqrt(W×L)).

2.6 DIBL — Drain-Induced Barrier Lowering

In short-channel devices, the drain electric field penetrates into the channel and lowers the potential barrier at
the source — effectively lowering Vth.
ΔVth = -DIBL × VDS [DIBL coefficient typically 20–100 mV/V]
Physical intuition: In long-channel devices, the drain field is shielded by the channel. In short-channel, the drain
field reaches the source region.
• DIBL increases as L decreases
• DIBL increases leakage in OFF state (VGS = 0 but high VDS)
• Analog concern: DIBL degrades current source accuracy (VDS-dependent ID)
⚠️COMMON MISTAKE: In cascode current mirrors, DIBL can cause drain-current mismatch if VDS differs between
transistors. Keep VDS equal or use long L.

2.7 Velocity Saturation

In short channels, the high electric field causes carrier velocity to saturate — no longer proportional to E.
v = μ×E / (1 + E/Esat) → vsat ≈ 10^7 cm/s for electrons
ID(sat, with [Link]) = W×Cox×vsat×(VGS - Vth - VDS,sat/2)
In velocity saturation: ID becomes linear in (VGS - Vth) rather than quadratic. This occurs for E > Esat = vsat/μ ≈
4×10^4 V/cm.
Layout implication: In advanced nodes (7nm, 5nm), velocity saturation is always significant. The classical
(W/L)×Cox×(VGS-Vth)²/2 model is inaccurate. SPICE models (BSIM4, BSIM-CMG) capture this.

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2.8 Short Channel Effects (SCE)
As channel length shrinks, multiple second-order effects degrade transistor behavior:

Effect Cause Impact / Mitigation

Vth Roll-off Drain/source depletion overlaps channel Vth decreases with shorter L → use
longer L in analog

DIBL Drain field lowers source barrier Higher off-state leakage → longer L, halo
implants

Punch-through Source-drain depletion regions touch Catastrophic current flow → halo

implants prevent

Hot Carrier Injection High-E near drain → carriers inject into Vth shift, ID degradation → limit VDS,
oxide use LDD

Velocity Saturation Carrier velocity limited ID linear in Vgs at short L

Gate Leakage Thin tox → tunneling High-k dielectrics (HfO2) used in <28nm

2.9 Leakage Mechanisms

1. Subthreshold Leakage
Isub = I0 × W/L × exp((VGS-Vth)/(n×VT)) × (1 - exp(-VDS/VT))
Exponentially sensitive to Vth and temperature. At 125°C, leakage can be 100× higher than at 25°C.

2. Gate Tunnel Leakage

Direct tunneling through ultra-thin gate oxide (<3nm). Solved by high-k dielectrics (HfO2 εr≈25 vs SiO2 εr≈3.9)
which achieve same Cox at 5× thicker physical oxide.

3. GIDL — Gate-Induced Drain Leakage

Occurs at VGS = 0, high VDS. High field near drain bends bands → band-to-band tunneling generates electron-
hole pairs → leakage current. Critical in SRAM hold mode.

4. Junction Leakage
Ij = IS × (exp(V/VT) - 1) ≈ -IS for reverse bias
Reverse-biased source/drain junctions to substrate. Increases with temperature and junction area.
📌 NOTE: Layout minimization: Minimize drain/source junction area (use shared diffusion, avoid large drain fingers)
to reduce junction leakage. Critical for low-power analog.

2.10 Hot Carrier Injection (HCI)

Near the drain in saturation, the electric field is highest. Electrons gain kinetic energy ('hot') and can:
• Inject into gate oxide → trapped charge → Vth shifts permanently
• Create interface states → mobility degradation
• Cause ID to decrease or increase over device lifetime

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 Maximum electric field: Emax ≈ (VDS - VGS + Vth) / (2×λp) [where λp
≈ L/10]
Mitigation: Use Lightly Doped Drain (LDD) structures to spread the field. In layout, ensure routing doesn't violate
maximum VDS specs.
🎯 INTERVIEW TIP: Reliability question at Intel/Qualcomm: 'How does hot carrier injection degrade a MOSFET?'
Answer: HCI creates interface traps and oxide trapped charge near the drain, shifting Vth, reducing gm, and
increasing 1/f noise. LDD structures mitigate by spreading the peak field.

2.11 NBTI — Negative Bias Temperature Instability

Specific to PMOS under negative gate bias (VGS = -VDD). Silicon-hydrogen bonds at Si-SiO2 interface break,
creating interface traps.
ΔVth = A × t^n × exp(-Ea/kT) [n ≈ 0.25, Ea ≈ 0.1 eV]
• Vth magnitude increases with time → PMOS weakens
• Partially recoverable when stress removed
• Accelerated by high temperature and high VGS
• Critical for analog circuits where PMOS operates in continuous stress
⚠️COMMON MISTAKE: In analog layout, ensure critical PMOS devices (especially in differential pairs and bias
circuits) operate at or below reliability voltage specs. Never exceed VGS,max.

2.12 Process Corners

Process corners represent the statistical extremes of fabrication:

Corner NMOS PMOS Impact

TT (Typical) Typical Typical Nominal design point

SS (Slow-Slow) Slow Slow Worst case for speed, timing

FF (Fast-Fast) Fast Fast Worst case for power, leakage

SF (Slow-Fast) Slow Fast Worst case for some analog ratios

FS (Fast-Slow) Fast Slow Worst case for other analog ratios

Layout engineers must verify that all post-layout simulations pass at all required corners and temperatures (e.g.,
SS/−40°C and FF/+125°C are common extremes for analog).

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 PART 3
CMOS FUNDAMENTALS

Part 3: CMOS Fundamentals

CMOS (Complementary MOS) uses complementary pairs of NMOS and PMOS transistors. The fundamental
CMOS gate is the inverter. Understanding CMOS inverter behavior is essential for layout analysis.

3.1 CMOS Inverter

A CMOS inverter has a PMOS (pull-up) and NMOS (pull-down) with shared input and output:
• Input HIGH (VDD): NMOS ON, PMOS OFF → Output LOW (0)
• Input LOW (0): NMOS OFF, PMOS ON → Output HIGH (VDD)
• No DC path from VDD to GND in either stable state → Zero static power!
Switching Point (VM): When Vin = Vout
VM ≈ (Vth,n + r×(VDD - |Vth,p|)) / (1 + r) where r = sqrt(kp/kn)
For symmetric switching (VM = VDD/2): Make kp = kn by sizing Wp/Wn = μn/μp ≈ 2–3×
📌 NOTE: In analog layout, CMOS inverters are used as amplifiers (biased in transition region), comparators, and
logic gates. The matching of NMOS and PMOS directly impacts switching point.

3.2 Noise Margins

Noise margin defines how much noise a logic gate can tolerate while still operating correctly.
NMH = VOH - VIH [High noise margin]
NML = VIL - VOL [Low noise margin]
For CMOS: VOH ≈ VDD, VOL ≈ 0, VIH and VIL from VTC curve. Larger noise margins → more robust design.
🎯 INTERVIEW TIP: Broadcom/AMD: 'How does W/L ratio affect noise margin of a CMOS inverter?' Changing W/L
shifts VM. If PMOS is weaker (Wp too small), high-to-low transition happens at lower Vin → NMH decreases.

3.3 Propagation Delay

tpHL = 0.69 × Ron,n × CL [high to low output transition]
tpLH = 0.69 × Ron,p × CL [low to high output transition]
tp = (tpHL + tpLH) / 2 [average propagation delay]
CL = load capacitance = Cgate_next + Cwire + Cdrain_current
Layout impact: Wire length directly adds to CL. Long routes slow down the signal. Buffer insertion is needed for
long nets.

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3.4 Power Dissipation
Dynamic Power
Pdynamic = α × CL × VDD² × f
Where α = activity factor (0 to 1), f = clock frequency, CL = total capacitance.
Layout implication: Reducing wire capacitance and minimizing routing length directly reduces dynamic power.
This is especially critical for high-speed chips.

Static Power
Pstatic = Ileak × VDD
From subthreshold, gate, and junction leakage. Dominant in modern advanced nodes. Layout must minimize
parasitic junctions and use proper Vth devices.

Short-Circuit Power
Pshort = Ipeak × VDD × tr × f [during input transition]
Both NMOS and PMOS briefly conduct simultaneously during input transition. Short transition times minimize
this.
Total Power = Pdynamic + Pstatic + Pshort,circuit

3.5 Rise and Fall Time

tr = 2.2 × Ron,p × CL [10%–90% rise time]
tf = 2.2 × Ron,n × CL [90%–10% fall time]
For equal rise/fall time: size PMOS to have equal drive strength as NMOS → Wp = Wn × (μn/μp).
⚠️COMMON MISTAKE: A common layout mistake is not accounting for asymmetric drive strengths in analog
output stages. If PMOS is undersized, rise time is much slower than fall time, distorting output waveforms.

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 PART 4
FABRICATION PROCESS

Part 4: CMOS Fabrication Process

Understanding fabrication is CRITICAL for analog layout engineers. Every layout decision (minimum spacing,
enclosure rules, stacking) comes from fabrication constraints. This section explains the key process steps.

4.1 Starting Material

• P-type silicon wafer (typically 200mm or 300mm diameter)
• Wafer resistivity: ~10–20 Ω·cm (determines substrate doping)
• Crystalline orientation: <100> preferred for CMOS (lower interface state density)

4.2 Oxidation
Silicon reacts with oxygen (or water vapor) at high temperature to form SiO2.
Si + O2 → SiO2 [Dry oxidation: slower, better quality, thinner]
Si + 2H2O → SiO2 + 2H2 [Wet oxidation: faster, thicker, worse
quality]
Key insight: Growing 1nm SiO2 consumes ~0.46nm of silicon (silicon oxidizes INTO the wafer). Total thickness:
tox(SiO2) ≈ 2.17 × xSi(consumed).
Uses in CMOS:
• Gate oxide (thin: 1–5nm) — dry, high quality
• Field oxide / LOCOS (thick: 300–500nm) — wet, isolation
• Hard mask for implant blocking

4.3 Lithography
Lithography transfers a circuit pattern (mask) onto the wafer using light:
1. Apply photoresist (PR) — light-sensitive polymer layer
2. Expose with UV/DUV/EUV light through a mask (reticle)
3. Develop: Positive PR — exposed areas dissolve; Negative PR — unexposed areas dissolve
4. Etch, implant, or deposit using PR as a mask
5. Strip PR

Resolution Limit
Minimum feature size: R = k1 × λ / NA [Rayleigh criterion]

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Where λ = wavelength, NA = numerical aperture, k1 = process factor (~0.28)

Technology Light Source Wavelength Node (example)

DUV (ArF) ArF laser 193nm 65nm–14nm with immersion+multi-

patterning

EUV Plasma 13.5nm 7nm, 5nm, 3nm, 2nm

4.4 Etching
Wet Etching
Chemical etching isotropic (etches in all directions). Example: HF etches SiO2 selectively over Si.
Problem: Undercuts features, poor dimensional control for sub-100nm patterns.

Dry (Plasma) Etching — RIE

Reactive Ion Etching uses plasma of reactive gases. Anisotropic (etches mostly downward). Critical for sub-
100nm patterning.
• High aspect ratio etching for contacts, vias, trenches
• Etch selectivity: Must etch target material without damaging underlying layers
• Plasma damage can create interface states → reliability issue

4.5 Ion Implantation

Doping is done by shooting ions (P, As, B) at high energy into the wafer. Key parameters:
Range (Rp): Average depth of implanted ions = f(energy, ion mass,
target material)
Dose: Total ions per cm² = determines doping concentration
After implant, anneal at ~1000°C activates dopants (moves into substitutional sites) and repairs crystal damage.
Layout relevance: Halo/pocket implants are self-aligned to gate — controlled by lithography and etch. Well
implants define NMOS/PMOS device territories.

4.6 STI — Shallow Trench Isolation

STI electrically isolates adjacent transistors. Process:
6. Define active areas with nitride mask
7. Etch trenches (~350nm deep) into silicon
8. Grow thin oxide liner (~5nm)
9. Fill with CVD SiO2 (or high-density plasma oxide)
10. CMP to planarize — stop on nitride
11. Strip nitride
Layout rules from STI:
• Minimum active-to-active spacing (determines STI width)
• STI stress affects mobility (tensile → NMOS faster; compressive → PMOS faster)

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 • LOD (Length of Diffusion) effect: Transistors near STI edge have different Vth and mobility
⚠️COMMON MISTAKE: LOD (Length of OD) effect: MOSFET at the edge of an active region has different
characteristics than one in the center. In matched layouts, ensure ALL matched devices have identical LOD on both
sides — this requires dummy devices at the edges.

4.7 Well Formation

Twin-well CMOS process:
• P-Well: Implant boron into n-type substrate → NMOS devices formed here
• N-Well: Implant phosphorus into p-type substrate → PMOS devices formed here
• Deep N-Well (DNW): Available in some processes — isolates P-well from substrate (reduces substrate noise
coupling, enables NMOS body biasing)
📌 NOTE: In layout: NMOS always in P-well (or substrate), PMOS always in N-well. The well taps (substrate contacts)
must be placed close to every device to prevent latch-up.

4.8 Gate Formation

12. Grow gate oxide (dry, ultra-thin, high quality)
13. Deposit polysilicon (doped n+ or p+) or metal gate
14. Deposit hard mask (Si3N4 or SiO2)
15. Lithography + Etch → define gate
16. Self-aligned source/drain extensions (LDD) implant
17. Sidewall spacer deposition + etch (oxide or nitride)
18. S/D implant (high dose, activated by anneal)

Poly Gate vs Metal Gate

Old CMOS used n+ poly (NMOS) and p+ poly (PMOS) gates. Problem: Poly depletion effect (thin depletion layer
in poly) effectively increases tox → reduced Cox.
Modern CMOS (45nm+): High-k/Metal gate (HKMG). HfO2 as dielectric + TiN/TaN as gate metal. Eliminates poly
depletion and gate leakage.
🎯 INTERVIEW TIP: Intel/TSMC interview: 'Why switch from SiO2/poly to high-k/metal gate?' To scale equivalent
oxide thickness (EOT) without gate leakage tunneling. HfO2 has εr≈25 vs SiO2 εr=3.9 → can use physically thicker
film with same capacitance → less tunneling.

4.9 Contact and Via Formation

Contacts (M0 to OD/PO)
19. Deposit pre-metal dielectric (PMD): SiO2 or low-k material
20. CMP planarize
21. Lithography + etch contact holes down to source/drain or poly
22. Ti/TiN barrier deposition
23. W (tungsten) CVD fill
24. CMP to remove excess W

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Rule: Contacts are critical for current flow. Always use maximum number of contacts for high-current devices.
Contact resistance adds to Ron and causes IR drop.
Rc = ρc / Ac [contact resistance; ρc ~ 10^-8 Ω·cm² for silicide
contacts]

4.10 Metallization — Backend of Line (BEOL)

Multiple metal layers (M1 to M10+ in modern nodes) carry signals and power:

Layer Material Typical Sheet R Usage

M1–M3 Cu (damascene) ~0.1 Ω/□ Local connections, cell routing

M4–M6 Cu ~0.05 Ω/□ Semi-global routing, power rails

M7–M10 Cu (thick) ~0.02 Ω/□ Global routing, supply distribution, inductors

AP (Alucap) Al ~0.05 Ω/□ Top metal for wire bond pads, inductors

4.11 FinFET Process

At 22nm and below (Intel's 22nm in 2011 was first commercial FinFET), planar MOSFETs lost gate control. FinFET
uses a 3D fin structure:
• Silicon fin rises vertically from the substrate
• Gate wraps around three sides of the fin (tri-gate)
• Superior electrostatic control: virtually eliminates DIBL and subthreshold leakage
• Width is quantized: W = n × Wfin (n = number of fins)
IDS ∝ n × Wfin / Lg
Layout differences from planar:
• W/L no longer continuously variable — must use integer number of fins
• Fin pitch is fixed — determines minimum device spacing
• Multi-patterning required for fin definition at 7nm (SADP or SAQP)
• Well proximity effects differ from planar — new layout rules apply
🎯 INTERVIEW TIP: FinFET interview (NVIDIA/Intel): 'Why did we move to FinFETs?' Electrostatic control: in planar
below 22nm, SCE (DIBL, punch-through) were unmanageable. FinFET gate wraps around fin on 3 sides → much
better channel control → lower Vmin, lower leakage.

4.12 Multi-Patterning
Since EUV wasn't available until 7nm, features smaller than 193nm immersion resolution require multi-
patterning (printing multiple masks at coarser pitch):

LELE — Litho-Etch-Litho-Etch
Two separate lithography + etch steps. Pattern split into two colors. Overlay error between exposures → design
rule: same-color spacing > 1 pitch, different-color spacing can be < 1 pitch.

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SADP — Self-Aligned Double Patterning
Deposit spacers on mandrels, remove mandrels → two features per original. More accurate than LELE, used for
fins and metal layers at 10nm/7nm.
Layout implication: Coloring rules apply. Two shapes must be 'color-compatible' — EDA tools automatically color
but may fail if shapes are too close or form odd loops. Layout engineers must understand coloring errors in DRC.

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 PART 5
ANALOG CIRCUIT BASICS

Part 5: Analog Circuit Basics & Layout Implications

Every analog circuit topology has specific layout requirements. This section covers the most important analog
building blocks with both circuit intuition and layout-specific guidance.

5.1 Current Mirrors

Basic Current Mirror
A current mirror copies a reference current IREF to one or more outputs. The simplest uses two identical
MOSFETs sharing a gate voltage.
IOUT/IREF = (W/L)out / (W/L)ref [ratio of W/L]
Layout requirements for a basic current mirror:
• Both transistors must be in saturation (VDS,out ≥ VGS - Vth)
• Identical orientation, no STI stress difference → use interdigitation or common centroid
• Matched devices: same W, L, number of fingers, orientation
• Both devices in same well, equidistant from tap contacts
• Vias and metal routing must be symmetric to avoid additional IR drop mismatch

Cascode Current Mirror

Adds cascode transistors above the basic mirror to increase output impedance:
Rout = gm,cas × ro,cas × ro,M1 [much higher than basic mirror]
Layout additions:
• Now 4 transistors total (2 input, 2 output side)
• Cascode gate bias line must be routed symmetrically
• Common centroid arrangement for all 4 devices ideal
• Extra caution for VMIN: cascode requires more voltage headroom

5.2 Differential Pair

The differential pair is the heart of every op-amp, OTA, and comparator. Two matched MOSFETs share a tail
current source.
ΔID = gm × VID / 2 [for small VID]
CMRR = gm × RTAIL [common-mode rejection ratio]
Layout requirements for differential pair:
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 • CRITICAL: Perfect symmetry is mandatory — any layout asymmetry directly adds to input offset voltage
• Common centroid placement (e.g., ABBA or AB/BA pattern)
• Identical routing for gates: matched wire length, same number of vias
• Identical routing for drains: same parasitic capacitance on both outputs
• Dummy devices on outer edges to match STI/LOD environment
• Same well distance and well proximity for both devices
• Deep N-well if available to isolate from substrate noise
Input Offset Voltage due to mismatch: VOS = ΔVth + (VGS-Vth)/2 × ΔW/W
- ΔL/L)
🎯 INTERVIEW TIP: Most common analog interview question: 'Why do differential pairs need common centroid
layout?' Answer: Gradient cancellation. If Vth has a linear gradient across the die, placing M1 and M2 symmetrically
around the gradient midpoint causes the Vth error in M1 and M2 to cancel, minimizing VOS.

5.3 Cascode Amplifier

Cascode (common gate) transistor stacked above common source transistor provides high gain and high output
impedance.
Gain: Av = -gm × (gm,cas × ro,cas × ro) [very high gain]
Output impedance: Rout ≈ gm,cas × ro,cas × ro
Layout considerations:
• Input device and cascode often share diffusion (saves area, reduces Cdb)
• Gate of cascode needs clean bias — bypass cap nearby in layout
• Drain of input device (= source of cascode) is an internal high-impedance node — shield from substrate noise
• Bias voltage routing must be low-resistance to prevent noise coupling

5.4 Folded Cascode OTA

A folded cascode OTA has the cascode current 'folded' to allow PMOS input pair with PMOS cascode + NMOS
cascode for wide output swing.
Gm = gm,input [transconductance = input pair gm]
Rout = (gm,n × ro,n × ro,n_tail) || (gm,p × ro,p × ro,p_bias)
DC Gain = Gm × Rout
This is one of the most common analog blocks you'll lay out. Layout priorities:
• Input differential pair: highest matching priority — common centroid mandatory
• PMOS bias/cascode: matched pair — interdigitation
• NMOS cascode: can be less perfectly matched if NMOS bias is well-controlled
• Output node: high impedance — minimize coupling from noisy nets
• Tail current source: single device or cascode — away from supply bounce
• Bypass capacitors on all bias nodes in layout

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5.5 Bandgap Reference
A bandgap reference generates a voltage proportional to silicon bandgap (~1.2V) that is nearly temperature-
independent by summing a PTAT (proportional to absolute temperature) voltage and a CTAT (complementary to
AT) voltage.
VREF = VBE + k × VT × ln(n) [where n = area ratio of BJT pair]
d(VREF)/dT = 0 at design point [TC cancellation]
Layout is extremely critical:
• BJT (PNP) devices must be tightly matched — common centroid in 2×4 or 4×4 array
• Resistors must be matched — interdigitation + dummy ends
• Temperature gradients cause VREF TC variation — symmetric placement on die
• Keep circuit away from high-power blocks (power FETs, drivers) to minimize thermal gradients
• Substrate contacts surround the entire circuit to block substrate noise
• Power supply bypass cap as close as possible to VREF circuit

5.6 LDO — Low Dropout Regulator

LDO provides a regulated output voltage lower than VIN. Key elements: error amplifier (OTA), pass transistor
(large PMOS), feedback resistors, and compensation capacitor.
VOUT = VREF × (1 + R1/R2) [where R1, R2 are feedback resistors]
Dropout Voltage: VDO = VIN - VOUT,min = VSD,pass_transistor at rated
current
Layout considerations:
• Pass transistor: LARGE device carrying full load current — electromigration rules critical
• Place pass transistor with proper current density on all drain/source connections
• Error amplifier: matched differential pair — common centroid
• Feedback resistors: must be matched — interdigitated
• Output capacitor connection: minimize ESL (series inductance) — wide metal, multiple vias
• Ground return path: provide low-resistance path from load back to LDO ground pin
• Thermal management: pass transistor at high load dissipates power — may need thermal via array

5.7 PLL — Phase-Locked Loop

A PLL synchronizes an output oscillator to a reference frequency. Key blocks: PFD (Phase Frequency Detector),
Charge Pump, Loop Filter, VCO, and Frequency Divider.

VCO — Voltage-Controlled Oscillator

KVCO = df/dV [VCO gain, Hz/V]
Layout: Ring oscillators or LC VCOs. LC VCO needs a spiral inductor (top metal, large area) — must be placed
away from other circuits to minimize magnetic coupling.

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Charge Pump
Converts PFD output pulses to current that charges/discharges loop filter. Layout: UP and DOWN current
sources must be exactly matched. Use common centroid mirroring.

Loop Filter
Sets PLL bandwidth and stability. Typically R+C or R+C1+C2. Layout: place close to charge pump output, minimize
parasitic coupling.

5.8 ADC Blocks

Common ADC architectures:

ADC Type Speed Resolution Key Layout Concern

Flash Fastest (GS/s) Low (4–6 bit) 2^N-1 comparators — symmetry,

routing

SAR Medium (MS/s) Medium-High (10–16 DAC capacitor array matching

bit)

Pipeline High (100MS/s+) Medium (10–14 bit) Residue amplifier offset, cap matching

Sigma-Delta Low-Medium (kS/s– High (16–24 bit) Modulator OTA noise, DAC linearity
MS/s)

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 PART 6
LAYOUT BASICS

Part 6: Layout Basics

This is where theory meets practice. Analog layout engineering requires mastery of layers, design rules, and how
every drawn shape maps to a fabricated structure.

6.1 Layout Layers and Their Physical Meaning

Layer Name Physical Meaning DRC Rules Analog Consideration

NWell N-type well implant Min width, min spacing, Must contain all PMOS; needs
region overlap of PMOS active well tap

OD/Active/ Silicon active (source, Min width, min spacing Minimize junction area to reduce
Diffusion drain, channel) Cjdb, leakage

PO/Poly Gate electrode, gate Min length (Lmin), min Poly resistance adds noise; use
length spacing, must cross OD metal over poly for bias

Contact (CT) W plug from M1 to Size fixed (~0.1×0.1μm), Use maximum contacts for low
OD/Poly min spacing, enclosure resistance

M1–Mx Copper interconnect Min width, spacing, area, Wider = lower R = less IR drop;
layers density rules follow EM rules

Via (V1–Vx) W/Cu plug between Fixed size, min spacing, Multiple vias in parallel for high
metal layers metal enclosure current

NP/PP (Implant) N+/P+ implant → S/D Must cover OD with Source of stress, affects Vth near
doping margin, spacing from gate boundaries

6.2 Design Rules

Design rules (DRC) are constraints from the foundry that guarantee the layout can be manufactured. Every rule
has a physical reason:

Why rules exist:

• Minimum width: Narrower than minimum → open circuit during lithography/etch (line gets destroyed)
• Minimum spacing: Less than minimum → two features may merge and short circuit
• Minimum enclosure: e.g., Contact must be fully inside OD — if not, contact may land outside silicon
• Minimum overlap: e.g., Poly must extend beyond OD by ≥ X — prevents leakage paths at edge
Example Rule: M1 minimum width = 0.06μm (TSMC 7nm)

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 Example Rule: Contact size = 0.1×0.1μm, spacing ≥ 0.1μm, OD enclosure
≥ 0.01μm

6.3 MOSFET in Layout: NMOS and PMOS

NMOS transistor layers:
25. P-Well (or substrate) — base
26. OD (active) rectangle — defines source, drain area
27. PP (P+ implant) for S/D doping → NO, actually NP (N+ implant) for NMOS S/D
28. Poly rectangle crossing OD — defines gate
29. Contacts on S/D OD and poly gate
30. M1 connections to S, D, G
📌 NOTE: The intersection of OD and PO (poly) creates the transistor channel. This is the most important concept in
layout — the channel exists only where poly crosses active silicon.

6.4 Guard Rings

Guard rings are rings of substrate contacts (for NMOS) or N-well contacts (for PMOS) surrounding devices to:
• Collect substrate minority carriers → prevent latch-up
• Reduce substrate resistance between devices
• Isolate sensitive analog circuits from digital noise
• Required by foundry rules around high-voltage devices

Types:
P+ Guard Ring: P+ diffusion tied to VSS — surrounds NMOS, collects holes, prevents PNPN latch-up trigger
current
N+ Guard Ring: N+ diffusion in N-well tied to VDD — surrounds PMOS, collects electrons
Double Guard Ring: Both P+ (inner) and N+ (outer) — maximum protection
Latch-up trigger current: Itrig = VDD / (β1 × β2 × R_sub) [must
exceed for triggering]
🎯 INTERVIEW TIP: Latch-up question (always asked): 'Why do we use guard rings?' To collect injected minority
carriers before they reach adjacent wells and trigger the parasitic PNPN thyristor (SCR). The guard ring lowers the
holding current path impedance so latch-up cannot be sustained.

6.5 Substrate and Well Taps

Every active circuit must have bias connections to body/bulk:
• NMOS: P-well/substrate must be connected to VSS via P+ diffusion contacts (taps)
• PMOS: N-well must be connected to VDD via N+ diffusion contacts
• Rule of thumb: Tap spacing ≤ 20μm for standard digital; ≤ 10μm for analog; even closer for radiation-
hardened designs
• In layout: place taps on both sides of every transistor row
⚠️COMMON MISTAKE: Missing substrate taps is one of the most common junior layout engineer mistakes. It
causes floating body (erratic Vth), latch-up risk, and increased substrate noise.

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6.6 DRC — Design Rule Check
DRC is an automated verification step (run in Calibre DRC or Assura DRC) that checks all drawn shapes against
the foundry design rule manual (DRM).
• Runs after layout is complete, before tape-out
• Zero DRC violations mandatory for tapeout
• Some 'waivers' are allowed with foundry approval for known-good layouts
Common DRC errors and causes:

DRC Error Likely Cause Fix

Metal spacing violation Routes too close together Increase spacing or reroute

Contact enclosure violation Contact placed too close to OD Move contact away from edge
edge

Well spacing violation N-well too close to adjacent N-well Merge wells or increase spacing

Poly not over OD Poly extends beyond active without Check poly end-of-line rules
proper rules

Metal density violation Too little/much metal in some area Add/remove metal fill shapes

6.7 LVS — Layout vs. Schematic

LVS extracts the netlist from layout and compares it to the schematic netlist. Every device and connection must
match exactly.
Common LVS errors:
• Short: Two nets unintentionally connected in layout (overlapping shapes)
• Open: Net not connected (missing contact, via, or metal)
• Port mismatch: Layout pin name doesn't match schematic pin name
• Device mismatch: W/L or number of fingers differs between layout and schematic
• Extra device: Layout has an unintentional parasitic diode or transistor
LVS tools: Calibre nmLVS, Synopsys Hercules, Mentor Calibre.
📌 NOTE: Always run LVS before PEX. An LVS-clean layout guarantees correct topology. PEX then adds parasitics on
top of the correct netlist.

6.8 PEX — Parasitic Extraction

PEX extracts all parasitic R and C from the layout. This is critical for analog because parasitics significantly affect:
• Gain-bandwidth product (GBW) of amplifiers — gate capacitance loads gm
• Phase margin — parasitic poles from routing capacitance
• Settling time — RC time constants from routing
• Noise — resistive thermal noise (kTR) and capacitive coupling
After PEX, run post-layout simulation to verify all specs including PVT corners.
Parasitic R: R = ρ × L / (W × t) = Rs × L/W [sheet resistance model]

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Parasitic C: C = ε × A / d + Cfringe [parallel plate + fringe]

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 PART 7
MATCHING TECHNIQUES

Part 7: Matching Techniques

Matching is the art of making two or more devices have identical electrical characteristics. In analog circuits,
even tiny mismatches translate directly to errors: offset voltage in op-amps, gain error in DACs, phase noise in
PLLs. This section covers every matching technique used in industry.

7.1 Why Mismatch Occurs

Sources of Mismatch:
• Random (stochastic) variation: Line edge roughness, dopant fluctuation — unavoidable
• Systematic gradient: Oxide thickness gradient, temperature gradient, implant gradient across chip
• Proximity effects: STI stress, well proximity, LOD (Length of OD) effect
• Orientation difference: Devices oriented differently see different stress, mobility
• Metal routing asymmetry: Different wire resistance/capacitance on each device terminal

7.2 Pelgrom's Law (Mismatch Model)

The most fundamental mismatch model in analog design. Random Vth mismatch between two nominally
identical transistors:
σ²(ΔVth) = AVth² / (W × L)
σ(ΔVth) = AVth / sqrt(W × L)
Where AVth is the Pelgrom coefficient (~2–5 mV·μm for standard CMOS processes).
Physical intuition: As device area increases, the number of dopant atoms under the gate increases, so statistical
fluctuations average out better.

Current Mismatch (Pelgrom extended):

σ²(ΔID/ID) = (gm/ID)² × σ²(ΔVth) + σ²(Δ(W/L)/(W/L))
For saturation: σ(ΔID/ID) ≈ (2/VGT) × AVth/sqrt(WL) + AβR/sqrt(WL)
🎯 INTERVIEW TIP: Pelgrom's law: critical interview question at every company! Key points: (1) σVth ∝ 1/sqrt(WL), so
larger devices have less mismatch. (2) Operating at lower VGT (VGS-Vth) amplifies Vth mismatch into current
mismatch. (3) Pelgrom coefficient AVth is process-specific — ask foundry.

7.3 Unit Device Approach

Instead of drawing one W/8L transistor, draw 8 unit transistors of W/L, each with identical geometry:
• All units are identical in drawn W and L
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 • All units in the same orientation and same well region
• Ratios achieved by connecting different numbers of units in parallel
Example: 4:1 current mirror using unit devices
• Reference: 1 unit → IREF
• Output: 4 units in parallel → 4×IREF
• Better matching than a single device 4× wider — avoids edge effects
📌 NOTE: Unit device approach is standard practice for all analog matched devices. It ensures every device sees
identical process, stress, and proximity environment.

7.4 Interdigitation
Instead of placing two devices side by side (A, B), interleave their fingers (A, B, A, B, ...) to average out linear
gradients.

How it works:
Suppose Vth has a linear gradient: Vth(x) = Vth0 + G×x
Side-by-side: ΔVth = G×(position_B - position_A) — large error
Interdigitated ABAB: Positions are 1,2,3,4 → A at 1,3 and B at 2,4
Vth(A) = Vth0 + G×1/4 + Vth0 + G×3/4 / 2 = Vth0 + G×1/2
Vth(B) = Vth0 + G×2/4 + Vth0 + G×4/4 / 2 = Vth0 + G×3/4
Wait — the cancellation is better with common centroid (ABBA). Interdigitation alone cancels linear gradients
for equal-area devices.
Applications: Matched resistor pairs, matched transistor pairs, capacitor arrays.

7.5 Common Centroid Layout

The gold standard for matching. Both devices are placed symmetrically about a common center so that any
gradient (linear, quadratic, or higher order) cancels.

ABBA Pattern (2 transistor matching):

Divide each transistor into two halves: A = A1A2, B = B1B2
Arrange as: A1 B1 B2 A2 (or A1 B1 | B2 A2 — 1D common centroid)
Now A1 and A2 are symmetric about the center, as are B1 and B2.

2D Common Centroid:
Better cancellation in both X and Y. Use a 2×4 or 4×4 matrix.
Example for a 2-transistor match (A vs B) in a 2×4 matrix:
Row 1: A B B A
Row 2: B A A B
Each device is placed at locations symmetric about the center in both X and Y → cancels both X and Y gradients.

Rules for Common Centroid:

• All units must have the same centroid → symmetry about geometric center

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 • Both units must occupy same total area
• Connections must maintain symmetry (routes symmetric about axis of symmetry)
• Dummy devices at boundaries to equalize edge environment
• Keep pattern compact to minimize higher-order gradient effects
🎯 INTERVIEW TIP: Interview scenario: 'Draw a common centroid layout for a 1:2 current mirror.' A has 1 unit, B has
2 units. 3-unit array: B A B. This is a 1D common centroid. For 2D: use 4 units with A=1, B=2: A B B A top row and A B
B A bottom row, but weight accordingly.

7.6 Dummy Devices

Dummy devices are non-functional copies of the real device placed at the edges of an array to:
• Equalize the STI/LOD environment for all active devices (every device has a neighbor on both sides)
• Balance etch loading (pattern density) → more uniform etch depth
• Reduce well proximity effect variation
• Provide symmetric gate poly end conditions
Layout of dummy devices:
• Same W and L as active devices
• Gate connected to fixed potential (GND for NMOS dummies, VDD for PMOS dummies) — so they stay OFF
• Source and drain tied to same potential
• Surrounded by contacts/metal like active devices (to match optical proximity)
⚠️COMMON MISTAKE: Dummy devices with floating gate are NEVER acceptable. A floating gate can charge up
and cause unpredictable behavior, including turning on unintentionally.

7.7 Gradient Cancellation Techniques

Linear Gradient → Common Centroid or ABBA cancels completely

Quadratic Gradient → Need 4+ units with proper arrangement

For a 1:3 mirror (A vs 3×B), arrange as: B A B B B and it doesn't work well. Better: use 4 total (B B A B → doesn't
cancel either). Best approach: Use a 4-unit array: A B B A top, B A A B bottom — then A has 4 cells, B has 4 cells
→ cannot do 1:3 directly. Solution: use 1:3 where A=1 unit and B=3 units in a 4-unit array as B A B B (quasi-
centroid), accepting that 1:3 in true centroid requires non-trivial arrangements.
📌 NOTE: For arbitrary ratios (like 1:3), perfect common centroid is hard. Use the LARGEST integer ratio that allows
centroid (e.g., 1:1 for two equal devices) and scale with bias if needed, or carefully arrange odd ratios.

7.8 Orientation Effects

MOSFET characteristics differ based on orientation due to silicon crystal anisotropy and stress:
• Transistors rotated 90° from each other may have 2–5% different mobility
• All matched devices must have IDENTICAL orientation — same direction of current flow
• In standard cell rows, horizontal orientation (current flows in X) is typical
• Never mix horizontal and vertical device orientation in a matched group
⚠️COMMON MISTAKE: A 90° rotated transistor in a matched pair is a serious layout error. Even if dimensions are
identical, piezoresistive effect from STI stress creates systematically different mobility → permanent offset.

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7.9 Device Fingers
Instead of one wide transistor (W=10μm), use multiple parallel fingers (e.g., 10 fingers of W=1μm each):

Why use fingers?

• Reduces gate resistance (Rgate): Rgate_finger = Rg/(N²) for parallel fingers with both-end contacts → lower
thermal noise from gate resistance
• Reduces drain/source parasitic junction area → lower Cdb, Csb
• Allows more regular layout for matching
• Enables shared source/drain diffusion between adjacent fingers → smaller area
Rgate = ρpoly × L / (W × tpoly) × 1/3 [for one-end contacted gate]
Rgate(N fingers) = Rgate_1finger / N [with gate contacted at one
end]
Rgate(N fingers, both ends) = Rgate_1finger / (4N) [contacted at
both ends]
Finger selection rule: For low noise designs (LNA, VCO), maximize N (many narrow fingers) to minimize Rgate
and thus thermal noise contribution (4kT×Rgate).
🎯 INTERVIEW TIP: NVIDIA interview: 'Why do you use multiple fingers for RF transistors?' Gate resistance
contributes thermal noise: in²=4kT/Rgate. Many narrow fingers contacted at both ends minimizes Rgate
dramatically. Also reduces gate RC delay for high-frequency operation.

7.10 Current Density Matching

Electromigration reliability requires limiting current density. For matching current mirrors, also ensure:
• All mirrored devices operate at same VGS−Vth
• Same inversion coefficient (IC = ID / (2n × μ × Cox × VT² × W/L))
• If different currents: use proportional W/L with unit-device approach

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 PART 8
PASSIVE DEVICES

Part 8: Passive Devices — Layout and Parasitics

Passive devices (resistors, capacitors, inductors) are as critical as transistors in analog layout. Their accuracy,
matching, and parasitic properties dominate performance in many circuits.

8.1 Resistors
Types and Properties:
Resistor Type Sheet R (Ω/□) TC (ppm/°C) Tolerance Best Use

N+ Diffusion ~70 Ω/□ +1500 to +2000 ±30% Rough, non-critical

P+ Diffusion ~150 Ω/□ +1500 to +2000 ±30% Rough, non-critical

N-Well ~1000 Ω/□ +4000 to +8000 ±30% Unique uses: ESD

Poly (silicided) ~7 Ω/□ +1500 ±20% Digital pull-up/down

Poly (non-silicided) ~200–300 Ω/□ +100 to +500 ±15% Preferred analog resistor

P+ Poly (precision) ~1k Ω/□ ~0 to +100 ±0.1% matched Bandgap, DAC, precision

RNWELL (Hi-R) ~1–10 kΩ/□ High ±50% Very large R (MΩ)

Poly Resistor Layout (Most Common in Analog):

• Define resistor body as non-silicided poly rectangle
• Value = Rs × L/W (number of squares × sheet resistance)
• End caps (contacts) contribute end resistance → account in simulation with head/tail bias
• For matching: use unit resistors (same L and W) connected in series/parallel
• Interdigitate matched resistors
• Dummy poly segments on both ends of array to equalize optical proximity
• Surround with same-material poly for consistent stress environment
R = Rs × (L/W) + 2×Rcontact [including contact resistance at ends]
Matching: ΔR/R = sqrt(2) × AR / sqrt(W × L) [Pelgrom for resistors]

8.2 MIM Capacitor (Metal-Insulator-Metal)

MIM cap is a dedicated capacitor built between two metal layers (e.g., M4 and M5) with a thin insulator (SiN or
HfO2) between them.

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 C = ε0 × εr × A / d [d ≈ 30–50nm for SiN MIM]
Typical density: 1–2 fF/μm² [much better than MOM at same area]

MIM Layout:
• Use maximum allowed area within power budget
• Bottom plate (lower metal) should be shielded from substrate noise
• For matched caps: use common centroid array — e.g., 8 unit caps arranged in 4×2 or 2×4
• Keep top plate connection symmetrical for matched caps
• Avoid routing over MIM (degrades oxide, adds parasitic)
• Poly plates under MIM should be avoided (excessive parasitic to gate)

MIM Parasitics:
• Bottom plate parasitic cap to substrate: ~5–10% of MIM value
• Series resistance from metal layers — minimize with wide connection
• Temperature coefficient: ~30–50 ppm/°C

8.3 MOM Capacitor (Metal-Oxide-Metal)

MOM cap uses interdigitated metal fingers within the same layer or between adjacent layers. Exploits fringe
capacitance between fingers.
C ≈ Cfringe × N × Lfinger × Nfinger [fringe-dominant for narrow
fingers]
MOM advantages:
• No special process layer needed — uses standard metal
• Can be placed in any metal layer
• Better Q factor (higher resonance frequency) than MIM
• Scalable with technology node (higher density at smaller nodes)
MOM disadvantages:
• Lower density than MIM for same area
• Sensitive to metal width/spacing variations → matching harder

8.4 Varactor (Voltage-Variable Capacitor)

Varactors are used in VCOs (PLLs) to tune oscillation frequency with a control voltage.

Types:
Junction Varactor: Reverse-biased PN junction. C = Cj0 / (1 - V/Vbi)^0.5. Simple but high series resistance.
MOS Varactor (Inversion-mode): NMOS in N-well, gate to N-well. High Cv range but abrupt transition.
Accumulation-mode MOS (A-MOS): NMOS in N-well biased in accumulation. Best Q for RF, preferred in LC-
VCOs.
Tuning range: fmax/fmin = sqrt(Cmax/Cmin)

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Varactor Layout:
• Symmetric placement around VCO differential tank circuit
• Matched pair layout (common centroid) for differential VCO symmetry
• Control voltage routing: low-R, shielded metal to minimize noise injection into VCO
• Minimize parasitic capacitance to substrate (use deep N-well isolation)

8.5 Spiral Inductor

Inductors are used in RF circuits (LNA, VCO, matching networks) and formed as metal spirals on top metal layers.
L ≈ μ0 × n² × Davg × c1 / (1 + c2 × ρ) [Mohan formula, ρ = fill
ratio]
Q = ωL / R_series [Quality factor]

Design Choice Effect on L Effect on Q

More turns (n↑) L ∝ n² Q decreases (more series R)

Wider metal (W↑) Slight increase (larger Davg) Q increases (lower R) up to skin
effect limit

Larger outer diameter L increases Q increases but substrate loss

increases

Use top metals (low Rs) Same L Q increases significantly

Patterned ground shield Slight decrease (image effect) Q increases (reduced substrate
coupling)

Spiral Inductor Layout Rules:

• Use top 1–2 metal layers (AP, M9, M8) — lowest sheet resistance
• Underpass (different metal layer) to bring inner terminal out
• Patterned ground shield: M1 stripes perpendicular to inductor radius — prevents eddy currents, reduces Cox
• Keep distance from adjacent metals ≥ inductor diameter (magnetic coupling)
• No active circuits under inductor — magnetic coupling induces noise
• For differential pairs: symmetric inductor (center-tapped) or differential layout
🎯 INTERVIEW TIP: RF layout interview: 'Why put a patterned ground shield under a spiral inductor?' PGS intercepts
E-field (reducing capacitive coupling to substrate) while the pattern breaks (perpendicular stripes) prevent eddy
currents from flowing in closed loops — so magnetic Q isn't degraded.

Analog Layout Design Handbook — Confidential Training Material | Page 33

 PART 9
RELIABILITY

Part 9: Reliability — Causes, Prevention, and Layout Solutions

Reliability is non-negotiable in IC design. A chip that passes all specs but fails in the field after 3 months is
worthless. This section covers all major reliability mechanisms with physical explanations and layout mitigation
strategies.

9.1 Electromigration (EM)

Electromigration is the gradual displacement of metal atoms caused by momentum transfer from conducting
electrons. Over time, this creates voids (opens) and hillocks (shorts).

Physics:
Electron wind force: F = Z* × e × ρ × J
Where Z* = effective valence (~1–4 for Cu), J = current density

Black's Equation (Mean Time to Failure):

MTF = A × J^-n × exp(Ea / kT)
Where: A = geometry constant, n ≈ 2 (Blech), Ea ≈ 0.5–1.0 eV, T = temperature
Implications:
• Doubling current density reduces MTF by 4× (for n=2)
• 10°C temperature rise roughly halves MTF
• EM is worst at hottest, highest-current nodes

EM Design Rules in Layout:

Metal Layer Max DC Current Density Max RMS AC Current Density

M1 (narrow, 0.1μm) ~1 mA/μm width ~2 mA/μm width

M3 (intermediate) ~2–3 mA/μm width ~4–6 mA/μm width

M8/AP (thick) ~5–10 mA/μm width ~15–20 mA/μm width

Via ~0.1–0.5 mA per via ~0.2–1 mA per via

EM Prevention in Layout:
• Calculate current through every metal segment: I / (width × thickness)
• Use minimum required metal width based on foundry EM tables (ITAP — current per width)

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 • Power rails (VDD, GND) use widest possible metal — usually thick top metals
• Always use multiple vias: single via is a weak point — EM creates void at via → open
• For high-current paths (LDO pass device, output driver): use metal fill and wide structures
• Consider bidirectional AC current: RMS applies → AC allows 2× DC rule for some layers
🎯 INTERVIEW TIP: EM interview — always asked: 'What causes electromigration and how do you prevent it in
layout?' Electron wind + momentum transfer → metal atom migration → void/hillock. Prevention: limit J < JMAX,
widen metal, use multiple vias, lower temperature, short segments (Blech short length effect).

9.2 IR Drop
IR drop is the voltage loss along resistive power supply rails. It reduces VDD at internal nodes, degrading
performance and potentially causing logic failures.
VDD_internal = VDD_external - I × R_rail
R_rail = Rs × L / W [sheet resistance × squares]

Why IR Drop Matters in Analog:

• Bandgap reference: Even 10mV VDD drop can affect VREF accuracy
• LDO: Input supply drop causes dropout → output falls out of regulation
• Bias circuits: Shared supply rail IR drop modulates bias currents
• Sensitive nets: Any resistive drop on a high-gain node amplifies noise

IR Drop Mitigation in Layout:

• Widen power rails — use thick metals (M8, M9, AP) for VDD/GND distribution
• Use multiple parallel paths for supply current
• Place bypass capacitors (decoupling caps) close to sensitive circuits
• Star topology: bring supply directly from PAD to each block, avoid long daisy-chain
• Separate analog and digital VDD → avoid digital transient noise on analog supply
Decoupling cap requirement: ΔV ≤ I × Δt / C → C ≥ I × Δt / ΔV
⚠️COMMON MISTAKE: Sharing a power rail between a high-current digital block and a sensitive analog circuit is a
very common mistake. The digital switching current causes mV-level IR drops and rail bounce that appear as noise
in the analog circuit.

9.3 Antenna Effect

During plasma etching and metal deposition, charge accumulates on floating metal/poly nodes. This charge can
flow through a MOSFET gate oxide, causing permanent damage (oxide breakdown or Vth shift).

How it works:
• Plasma process creates ions and electrons
• A long wire (large area) connected to a gate accumulates charge from the plasma
• Gate oxide (thin: 1–5nm) cannot withstand even small currents → damage occurs
Antenna Ratio = Metal Area / Gate Oxide Area connected [typically
limited to 400:1]

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DRC Check:
Antenna DRC rules check that the ratio of metal/poly area at each intermediate process step (when gate is
exposed) does not exceed the foundry limit.

Prevention:
• Antenna diodes: Add reverse-biased diode from net to VDD/VSS → during etching, diode provides discharge
path for accumulated charge
• Jump to higher metal early: If M1 wire is too long, via up to M2 at some point → breaks the M1 antenna
chain
• Layout: Automatically flagged by Calibre antenna DRC → engineer must add antenna diode or reroute
🎯 INTERVIEW TIP: Antenna DRC question: 'What is an antenna violation and how do you fix it?' The metal area ratio
to gate oxide exceeds the foundry limit, risking gate oxide damage during plasma processing. Fix: either add a
protective diode (bleeder diode) on the net, or jump to a higher metal layer to break the antenna.

9.4 ESD — Electrostatic Discharge

ESD is a brief, high-current discharge event (nanoseconds) that can deliver hundreds to thousands of volts,
destroying gate oxide or melting metal.

ESD Protection Models:

HBM (Human Body Model): ±2kV, 1.5kΩ + 100pF — simulates human touching chip
CDM (Charged Device Model): ±500V — simulates chip itself discharging
MM (Machine Model): ±200V, 200pF — simulates automated equipment

ESD Protection Structures:

• Input ESD: Diodes to VDD and GND clamp voltage at pad → protects gate
• Power clamp: Large NMOS or SCR between VDD and GND — triggered during ESD → provides low-Z current
path
• Signal clamp: Small diodes on all I/O pins

ESD Layout Rules:

• All I/O must have ESD protection — verified by ERC (Electrical Rules Check)
• ESD devices must have short, wide metal to handle kA peak currents
• ESD power clamp width often 100–500μm — massive device
• Ballasting resistors (100–500 Ω) in series with ESD diodes — ensures uniform turn-on
• Metal bus from pad to ESD device must handle peak ESD current without EM damage
⚠️COMMON MISTAKE: Never route sensitive analog signals (especially gate nodes) without ESD protection. A
single ESD event can instantly destroy a 1.5nm gate oxide. Even internal nodes connected to pads through long
wires need protection.

9.5 Latch-Up
Latch-up is a condition where a parasitic PNPN thyristor (SCR) between the supply and ground is triggered,
causing a low-impedance short that either locks up the circuit or destroys it.

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Parasitic SCR Structure:
In any CMOS process, there is always a parasitic PNP (PMOS source = P+, N-well = N, P-substrate = P) and a
parasitic NPN (N+ source = N, P-substrate = P, N-well = N) BJT. These two BJTs form a feedback loop.
Latch-up condition: βPNP × βNPN > 1

Trigger conditions:
• Supply voltage spike that forward-biases a junction
• I/O voltage going below GND or above VDD
• Current injection from external source (ESD)
• Minority carrier injection from n-well diodes

Prevention in layout:
• Minimize n-well to p-substrate distance (increases βs but reduces R_sub)
• Maximum substrate/well tap density (reduces substrate resistance → reduces injected current effect)
• Guard rings around every block (especially I/O cells)
• Separate I/O power domains from core domain
• ESD power clamp is also latch-up protection (provides current path before SCR triggers)
🎯 INTERVIEW TIP: Latch-up vs ESD: Both can be triggered by voltage spikes, but ESD is fast (ns) and one-time; latch-
up is sustained (requires VDD to maintain). Fixing ESD doesn't necessarily fix latch-up and vice versa.

9.6 TDDB — Time-Dependent Dielectric Breakdown

Gradual degradation of gate oxide under continuous high electric field. Over time, defects accumulate and
create a conductive path through the oxide → hard breakdown (device fails immediately) or soft breakdown
(oxide becomes leaky).
E-model: Lifetime ∝ exp(-γ × Eox) [γ ≈ 3–5 cm/MV]
V-model: Lifetime ∝ exp(-β × Vox)
Prevention:
• Never exceed maximum VGS specified by foundry for the process node
• For I/O transistors, use thick oxide (IO) devices that handle higher voltages
• Layout: Ensure no DC voltage stress exceeds reliability spec in any corner/temp scenario

9.7 Self-Heating and Thermal Effects

High power density causes localized heating, which:
• Decreases carrier mobility (ID decreases with T) — negative feedback for NMOS bias stability
• Decreases Vth (≈ -2mV/°C) — affects bias points
• Increases leakage exponentially
• Accelerates all degradation mechanisms (EM, NBTI, HCI, TDDB)
Thermal resistance: Rth = ΔT / P [K/W]
ΔT = P × Rth = I²×Ron × Rth
Layout thermal management:

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• Spread high-power devices across die (don't cluster)
• Use thermal via arrays below power devices → conduct heat to PCB through package
• Keep bandgap reference and other temperature-sensitive circuits away from power dissipating devices
• In FinFET: self-heating is worse because fins have poor thermal conductivity to substrate

Analog Layout Design Handbook — Confidential Training Material | Page 38

 PART 10
ADVANCED ANALOG LAYOUT

Part 10: Advanced Analog Layout — Complete Circuit Examples

10.1 Differential Pair Layout — Detailed
Step-by-step layout of a differential pair (M1, M2) with tail current source (M3) and load devices:

Step 1: Plan the floorplan

• Differential pair (M1, M2) centered in the block
• Tail current source (M3) below center
• Load devices (M4, M5) above M1, M2
• All NMOS on bottom (P-well), all PMOS on top (N-well)

Step 2: M1 and M2 layout (critical)

• Common centroid: Use 4 fingers total → M1 fingers at positions 1,4 and M2 fingers at positions 2,3 (BAAB
arrangement)
• OR: Use 8 unit fingers: M2 M1 M1 M2 M2 M1 M1 M2 (BAAББАА B)
• Shared source diffusion between adjacent fingers → reduces area and Cs parasitic
• Gate contacts on both sides of each finger → minimize Rgate
• Drain metal: M1 drains connect to OUT+ side, M2 drains to OUT- side
• CRITICAL: Make OUT+ and OUT- routings perfectly mirror-symmetric

Step 3: Dummy transistors

• Add 2 dummy fingers on each outer edge (total 2+8+2 = 12 finger array)
• Dummy gates: connect to VDD for PMOS, VSS for NMOS (keep OFF)
• Dummy source/drain: connect to appropriate supply

Step 4: Connections
• Common source node: connect with low-resistance ring of metal
• Gate inputs (IN+ to M1, IN- to M2): bring from same direction, same layer, symmetric
• Output metals: symmetric width, same layer

Step 5: Guard ring

• P+ substrate ring around entire diff pair → to VSS
• Additional N-well ring if in deep N-well → to VDD

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10.2 Current Mirror Layout — Detailed
Simple Current Mirror (1:N):
• M_ref (1 unit) and M_out (N units) — use interdigitation: M_out M_ref M_out ...
• Diode-connected M_ref: gate connected to drain with a via — this node is IREF input
• Shared gate bus between M_ref and all M_out gates — low-resistance metal bus
• Source: all connected to VSS with star routing from a common node
• Drain of M_out: connect to circuit output — high impedance node, minimize coupling

High-Accuracy Cascode Mirror:

• 4 devices: M1 (input side bottom), M3 (input side cascode), M2 (output side bottom), M4 (output side
cascode)
• 2D common centroid in a 2×2 or 4×4 array for better matching
• VCAS (cascode gate) must be clean — bypass with local cap
• Kelvin connections for reference diode (separate sense and force connections)

10.3 Two-Stage Op-Amp Layout

Architecture review:
• Stage 1: Differential input pair (PMOS or NMOS) + current mirror load + tail current source
• Stage 2: Common source amplifier (single transistor, large W/L) + current source load
• Compensation: Miller cap (Cc) between output of Stage 1 and Stage 2 output

Layout priority:
• Highest priority: Input differential pair matching (common centroid, dummy devices)
• Second priority: Current mirror load matching (interdigitation)
• Third priority: Miller compensation cap placement (close to output of stage 1)
• Miller cap (Cc): MIM cap preferred, bottom plate to output of stage 1, top plate to op-amp output
• Stage 2 transistor: Large W/L → many fingers, strong drive, low output impedance for loaded op-amp
• Input pins: Bring in parallel, shielded metal (M3 routed between M2 shields)

Common mistakes in op-amp layout:

• Input routes of different lengths → parasitic capacitance mismatch → increased offset
• Cc placement too far from Stage 1 output → series resistance in Cc → reduces phase margin
• Digital noise coupling into sensitive Stage 1 output node → oscillation or increased noise

10.4 Bandgap Reference Layout

Block structure:
• Core: Two PNP BJTs (Q1 with area A, Q2 with area n×A), startup circuit, amplifier, resistors (R1, R2, R3)

BJT layout:
• P-type substrate acts as collector, N-well as base, P+ emitter

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 • Q2 = n×Q1 → use n unit BJTs for Q2, all identical to Q1, in common centroid arrangement
• Emitter matching critical → all emitters same geometry, same orientation, common centroid 2D array

Resistor layout:
• All resistors: same type (poly, P+ poly or precision resistor option)
• R1 and R2 must be well matched → interdigitate with dummies
• Avoid current flow along gradient direction → route current perpendicular to gradient

Overall placement:
• Place entire bandgap away from power devices and oscillators
• Deep N-well isolation for all devices
• Symmetric layout about center of BJT array
• Bypass cap (100fF–1pF) on VREF output and on VPTAT internal node
• Multiple guard rings: P+ ring to VSS around N-well, N+ ring to VDD around circuit boundary

10.5 SAR ADC Layout

SAR ADC key components:
• Input track/hold switch (bootstrapped NMOS or T-switch)
• Capacitor DAC (CDAC): binary-weighted cap array (C, 2C, 4C, ..., 2^N × C)
• Comparator: StrongARM latch or preamplifier + latch
• SAR logic: Successive approximation register

CDAC Layout — the heart of SAR ADC accuracy:

• All capacitors must be unit capacitors (Cu) — binary weighting achieved by connecting 1, 2, 4, 8, ... units
together
• Use MIM or MOM caps — MIM preferred for higher density and better matching
• Common centroid arrangement for CDAC — 2D array with dummy caps on boundary
• For N-bit ADC: 2^N unit caps + dummies → large array (e.g., 12-bit needs 4096 units minimum)
• Bottom plate routing: single connection from comparator input — minimize parasitic
• Top plate: each unit top plate connects to either VIN or VREF or GND via switch
• Switch routing must be symmetric — same R for all switches
Mismatch requirement for N-bit: σ(Cu)/Cu < 1/(2^N × sqrt(2)) [must
meet for LSB accuracy]
For 12-bit: σ/Cu < 0.017% → requires large unit cap and good
matching

Comparator layout:
• Critical: parasitic capacitance at comparator input must be minimal → determine sensitivity floor
• Strong-Arm latch: NMOS and PMOS pairs in cross-coupled regeneration
• Common centroid for cross-coupled pair and reset devices
• Clock routing: balanced to both halves of latch → minimize kick-back noise

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• Differential input: symmetric routing from CDAC output to comparator input

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 PART 11
PARASITICS

Part 11: Parasitics — Extraction, Analysis, and Mitigation

Every physical structure in a layout has parasitic R and C. Understanding where they come from and how to
minimize them is essential for analog layout engineering.

11.1 Sources of Parasitic Resistance

Source Typical Value Formula Mitigation

Metal wire M1: ~0.1 Ω/□ R = Rs × L/W Wider wire, shorter route,
upper metals

Contact/Via ~5–20 Ω per contact R = ρc / Ac Use maximum contacts/vias

Poly gate ~100 Ω/□ R = Rpoly × L/(W×N²) Multiple fingers, contact both
ends

Source/Drain silicide ~3–10 Ω/□ R = Rsil × L/W Wide silicide, multiple contacts

N-well ~1000 Ω/□ R = Rnw × L/W Well contacts all around

11.2 Sources of Parasitic Capacitance

Parallel Plate Capacitance:
C = ε0 × εr × A / d
Between metal and substrate, between adjacent metal layers, between poly and diffusion.

Fringe Capacitance:
Cfringe ≈ 2 × ε0 × εr / π × ln(1 + 2t/s) [t = metal height, s =
spacing]
At sub-10nm nodes, fringe capacitance can dominate over parallel plate for narrow wires.

Key capacitances in analog layout:

• CGS, CGD: Gate-to-source/drain overlap capacitance — sets fT, affects high-freq response
• CDB, CSB: Drain/source junction to substrate — limits bandwidth
• Cmetal-metal: Coupling between adjacent signal lines — crosstalk, noise
• Cmetal-substrate: Every wire has capacitance to substrate — slows signal, contributes noise

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11.3 Crosstalk
Coupling capacitance between adjacent wires causes signal interference:
Vcoupled = Vaggressor × Ccoupling / (Ccoupling + Cload)
For digital switching: Vcoupled ≈ Vaggressor × Cc / (Cc +
Cvictim_load)

Analog crosstalk is particularly harmful:

• Digital clock coupling into analog input → ADC clock spurs
• VCO output coupling into PLL reference → phase noise degradation
• Power supply noise coupling into analog signal → PSRR degradation

Layout solutions:
• Route analog and digital signals on different metal layers
• Use shielding: route GND or VDD wire between aggressor and victim
• Maintain physical separation ≥ 3× wire pitch between sensitive analog and digital routes
• Use ground plane (mesh of GND metal) below sensitive analog circuits
• Guard traces: dedicated GND wire running parallel to sensitive signal

11.4 Substrate Noise

Digital circuits switch at high frequency → inject noise into the substrate through:
• Drain-to-substrate junction capacitance (when N+ drain switches)
• Body effect modulation of nearby devices
• Substrate resistance conducts noise to sensitive circuits

Layout solutions:
• Place analog circuits far from digital cores on the die
• Use deep N-well (DNW) isolation for critical analog blocks — creates reverse-biased junction barrier
• Dense substrate contacts between analog and digital blocks — low R substrate tap reduces noise voltage
• Guard ring of substrate contacts surrounds analog block
• Separate ground pads for analog and digital
🎯 INTERVIEW TIP: Substrate noise question at Qualcomm: 'How do you isolate RF circuits from digital noise on the
same die?' Use deep N-well under RF block, dense P+ ring to VSS_ANALOG, separate VDD and VSS domains, wide
separation on die floorplan, and use differential circuit topologies (reject common-mode substrate noise).

11.5 Shielding Techniques

Wire Shielding:
• Parallel shield: Route GND wire between aggressor and victim
• Coaxial shield: Sandwich sensitive wire between GND wires on same layer and metal layers above/below
• Differential routing: Route + and - signals as tightly coupled pair → noise couples equally to both → rejected
by differential receiver

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Capacitor Bottom Plate Shielding:
• Always connect bottom plate (closer to substrate) to the lower-impedance node
• For CDAC in SAR: bottom plate to comparator input (high-Z) means substrate noise couples — add extra
shielding layer below CDAC

Inductor Shielding:
• Patterned ground shield (PGS) below inductor
• No solid metal plate (would form short-circuited loop → reduce Q) — use stripes perpendicular to field lines

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 PART 12
FLOORPLANNING

Part 12: Analog Floorplanning

Floorplanning is the first step after schematic completion. Poor floorplanning causes problems that are nearly
impossible to fix in routing. A good floorplan minimizes parasitics, maximizes matching, and reduces noise
coupling.

12.1 Signal Flow Planning

The fundamental principle: arrange blocks in the order of signal flow to minimize wire length.
• Input block → processing block → output block → left to right or top to bottom
• Feedback paths should be short — long feedback routes add phase delay
• High-impedance nodes (op-amp output, CDAC bottom plate) should have minimum metal and be shielded
• Clock distribution: minimize skew, maximize symmetry, keep away from sensitive analog

12.2 Analog-Digital Separation

On a mixed-signal chip, strict separation of analog and digital is mandatory:
• Analog blocks: bandgap, OTA, PLL, ADC front-end — far from switching digital logic
• Digital blocks: SAR logic, decoder, shift register — can tolerate supply noise
• Buffer zone: substrate contact ring (guard ring) between analog and digital domains
• Separate power domains: AVDD, AGND for analog; DVDD, DGND for digital
• Boundary: ADC/DAC interface is at the boundary — place there with careful isolation

12.3 Power Planning

Analog power planning is more complex than digital — every block may have its own supply domain.

Key principles:
• Star topology: Each sensitive analog block gets its own supply connection from the pad
• No daisy-chain: Never power Block B from the supply rail of Block A if B is noisy
• Bypass caps: Every analog supply domain needs at least one bypass cap (1pF–10nF depending on frequency)
• Well-distributed VDD/GND: Use wide top-metal rails for main power distribution
• Separate inductor power: VCO supply isolated from all other supplies

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12.4 Grounding Strategy
Bad grounding is the #1 cause of analog IC noise problems.
• Single-point ground: All analog references ultimately connect to a single clean ground point
• Current return paths: Every current must have a low-impedance return path → loops = antennas
• Kelvin connections: For precision measurements, use separate force and sense connections to eliminate
contact resistance error
• Ground plane: Use M1 or M2 as a ground plane below sensitive circuits → shields from substrate, provides
low-R return path
• Digital-analog ground connection: Single point only (star ground) at the package level if possible
⚠️COMMON MISTAKE: Common mistake: Connecting digital GND bus through a shared trace that carries analog
ground return currents. Even 10mA digital switching current through 1 Ω shared resistance creates 10mV analog
ground bounce.

12.5 Placement of Matched Devices

Hierarchy of matching placement priority:
31. Differential pair: Common centroid, center of block, away from edges
32. Bandgap BJTs: Common centroid 2D array, temperature-stable location
33. Current mirror: Interdigitation or common centroid, close together
34. Precision resistors: Interdigitation, perpendicular to gradient
35. MIM caps in DAC: Full 2D common centroid array
📌 NOTE: Always consider the temperature gradient on the die. Hot spots (power devices, output drivers) create
temperature gradients that cause systematic Vth and mobility variation. Place sensitive circuits equidistant from all
heat sources.

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 PART 13
VERIFICATION FLOW

Part 13: Complete Verification Flow — DRC, LVS, PEX, and

Simulation
Verification is the quality gate before tapeout. A systematic verification flow ensures that the fabricated chip
matches the design intent.

13.1 DRC Flow (Calibre DRC)

Setup:
36. In Virtuoso Layout: Calibre → Run DRC
37. Select foundry DRC rule file (.drc or .svrf)
38. Set correct layer mapping (GDSII layer map)
39. Enable all relevant checks (minimum width, spacing, density, antenna)

DRC Results and Debug:

• Calibre DRV opens showing violations highlighted in layout
• Each error has a rule name, description, and polygon location
• Fix violations one rule at a time, starting from the lowest layer (active → poly → contacts → metals)
• Re-run DRC after fixing to confirm no new violations introduced

Common DRC debug workflow:

40. Filter by rule to group similar errors
41. Navigate to first violation in layout
42. Understand physical cause → fix minimum violation
43. Run incremental DRC if available
44. After batch fix: run full DRC again

13.2 LVS Flow (Calibre nmLVS)

Setup:
45. Export schematic netlist from Virtuoso ADE/Schematic
46. In Virtuoso Layout: Calibre → Run LVS
47. Select LVS rule file, schematic netlist, layout netlist
48. Run extraction + comparison

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LVS Error Types and Fixes:
Error Type What it means Common Cause / Fix

Net Short Two nets connected in Overlapping metal shapes. Use Edit → Merge or Split
layout but not in schematic shapes. Check if via accidentally connects wrong layers.

Net Open Net broken in layout Missing contact or via. Use metal highlight to trace net.

Device mismatch W/L or type differs Check if layout W/L matches schematic. Recalculate
finger count.

Extra device Layout has device not in Parasitic diode formed by well/diffusion junction. Add
schematic device to schematic or remove from layout.

Missing device Schematic device not in Device not placed or its connections missing. Check port
layout names.

13.3 PEX Flow (Parasitic Extraction)

PEX setup (Calibre xRC or QRC):
49. Run DRC-clean and LVS-clean layout through Calibre xRC or StarRC
50. Select extraction accuracy (full-chip RC, RC+ capacitance coupling, or R+CC)
51. Select technology RCEF file from foundry
52. Generate extracted netlist (.spi or .cdl format with parasitics)

Types of extraction:
C-only: Faster, extracts only capacitances — good for digital timing
RC: Extracts both R and C — standard for analog
RCC: Full coupling capacitance — mandatory for high-speed and RF

Post-PEX netlist debug:

• Large unexpected parasitic R → long thin metal route → fix by widening or rerouting
• Large parasitic C on sensitive node → many wires overhead → add shielding or reroute
• Coupling between differential signals → they should be equal (same Ccoupling) → fix routing asymmetry

13.4 Post-Layout Simulation

After PEX, simulate the extracted netlist to verify all specifications:

In Cadence Virtuoso ADE:

53. Load extracted netlist (usually via cellview 'av_extracted' or imported Spectre deck)
54. Run same testbenches as pre-layout: DC, AC, Transient, Noise, Monte Carlo
55. Compare pre- vs post-layout results — identify degradations
56. If specs fail: identify worst parasitics, fix layout, re-extract, re-simulate

Common post-layout issues:

• Reduced GBW: Gate parasitic C loads input → lower gm_effective → fix by reducing Cgg at input

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 • Reduced phase margin: Parasitic pole from routing → may need Cc adjustment
• Increased offset voltage: Routing asymmetry added Cgs mismatch → fix routing symmetry
• Oscillation: Long feedback path adds phase → shorten feedback or add compensation

13.5 Monte Carlo Analysis

Monte Carlo simulation statistically characterizes circuit behavior over process and mismatch variation:
• Process MC: Varies global process parameters (all devices shift together) → simulates lot-to-lot variation
• Mismatch MC: Varies individual device parameters independently → simulates within-die mismatch
• Combined MC: Both simultaneously — most realistic but slowest
Typical MC runs: 200–1000 samples for 3σ confidence
3σ yield requirement: Pass rate > 99.73% → need ~1000+ samples to
characterize well
🎯 INTERVIEW TIP: MC question at TI/Broadcom: 'How many MC runs do you need to characterize 6σ yield?' For 6σ,
you need about 10^9 samples in direct MC — impractical. Use importance sampling or corner analysis for tail
events. For 3σ: 1000 samples gives ~±0.5σ uncertainty.

13.6 Corner Analysis

Simulate at all PVT (Process-Voltage-Temperature) corners:
• Process: TT, SS, FF, SF, FS (sometimes added: corner for each device type)
• Voltage: VDD ± 10% (or as specified)
• Temperature: -40°C, +25°C, +85°C, +125°C (sometimes +150°C)
For a standard analog block, this gives 5 × 3 × 4 = 60 corner simulations minimum.
Critical corners for analog:
• Gain: Worst at SS (low gm) / +125°C (low μ)
• Bandwidth: Worst at FF (more parasitic C but higher gm — usually OK) / SS checks for minimum BW
• Offset: Monte Carlo at TT/27°C shows statistical distribution
• Stability: All corners must have positive phase margin
• Power: FF/+125°C usually gives maximum leakage power

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 PART 14
FINFET AND ADVANCED NODES

Part 14: FinFET and Advanced Node Layout

14.1 FinFET Structure
In a FinFET (Fin Field-Effect Transistor), the channel is a thin vertical silicon fin. The gate wraps around three
sides (tri-gate). Key differences from planar:

Parameter Planar MOSFET FinFET

Channel geometry Horizontal, 2D Vertical fin, 3D

Gate control One side (top) Three sides (tri-gate)

SCE immunity Poor for L < 20nm Excellent — fin width ≈ L/2

Width quantization Continuous W Discrete: W = n × Wfin

Body contact Direct to substrate Fin body mostly floating (poor body
contact)

Self-heating Heat conducts through substrate easily Poor: fin surrounded by SiO2

Matching W/L freely scalable W quantized → matching in discrete

steps

14.2 FinFET Layout Rules (Key Differences)

• Fin pitch is fixed (e.g., 27nm at TSMC 7nm): cannot place fins at arbitrary positions
• All fins in a given poly track must have same length → no mixing of L
• Gate pitch is fixed in some processes — poly on regular grid (CFET: contact-over-active-gate)
• Width: W = n × (Wfin + Hfin × 2) for tri-gate, approximately W = n × Wfin
• End-of-line (EOL) rules for poly: spaces at poly end are tightly constrained
• Multi-patterning: Fins require SADP or SAQP → coloring constraints on fin shapes

14.3 Matching in FinFET

Pelgrom's law still applies but with modified coefficients:
σ(ΔVth) = AVth / sqrt(n × Wfin × Lg)
Because W is quantized in units of fin pitch, matching improvement is in steps. Cannot continuously increase W
for better matching — must jump from n to n+1 fins.

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 • Common centroid: Arrange fins of both devices alternately (fin interdigitation)
• Dummy fins must still be used at boundaries
• Gate routing across fins: same metal, same via type, same length
• Self-heating mismatch: If both devices carry different currents, they heat differently → Vth difference →
current ratio error. Keep matched devices at equal current

14.4 GAA — Gate-All-Around (Beyond FinFET)

At 3nm and below, GAA (also called nanosheet or nanowire FET) replaces FinFET. The gate wraps around all four
sides of horizontal nanosheets.
• Better electrostatic control than FinFET → lower Vth roll-off, less DIBL
• Multiple nanosheets stacked → higher effective width per fin pitch
• CFET (Complementary FET): Stack NMOS on PMOS vertically — extreme density
• Layout rules change significantly: 2D layout represents 3D nanosheet stacks
🎯 INTERVIEW TIP: TSMC/Samsung 3nm GAA interview: 'What is GAA and why move from FinFET?' In FinFET, gate
on 3 sides leaves one side (bottom) uncontrolled → limits scaling. In GAA/nanosheet, gate surrounds all 4 sides →
best electrostatic control → allows gate length scaling to <10nm with acceptable SCE.

14.5 EUV Lithography

EUV (Extreme Ultraviolet, λ=13.5nm) enables single-patterning of features that previously required multiple
LELE/SADP/SAQP steps at 7nm/5nm/3nm nodes.
• Photon energy: 91.5 eV — requires all-reflective optics (no transmission optics at this wavelength)
• Low source power → slow exposure → productivity challenge
• Stochastic effects: Low photon count → random line edge roughness (LER) at small features
• For layout: Still have minimum pitch rules, but coloring constraints are relaxed vs. multi-patterning
• EUV mask rules differ from DUV — designer must understand new forbidden pitch rules

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 PART 15
INTERVIEW PREPARATION

Part 15: 500+ Interview Questions with Detailed Answers

This section covers interview questions from beginner to advanced level, organized by topic and company. Study
every question — many appear across multiple top companies.

15.1 Beginner Level Questions

Semiconductor Basics
Q: What is a semiconductor?
A: A material with electrical conductivity between a conductor and insulator, with a band gap of 0.1–3 eV.
Si (Eg=1.12eV) and GaAs (Eg=1.42eV) are examples. Conductivity can be controlled by doping,
temperature, or electric field — making them ideal for transistors.

Q: What is the difference between n-type and p-type semiconductor?

A: N-type: Doped with donor (Group V) atoms like Phosphorus — has extra electrons → majority carriers
are electrons. P-type: Doped with acceptor (Group III) atoms like Boron — has holes → majority carriers
are holes. N-type has Fermi level closer to conduction band; p-type has it closer to valence band.

Q: What is a depletion region?

A: At a PN junction, electrons from N-side and holes from P-side recombine near the junction, leaving
behind ionized donors (+) on N-side and ionized acceptors (-) on P-side. This charged region, devoid of
free carriers, is the depletion region. It creates a built-in electric field (~0.7V for Si) that opposes further
diffusion.

Q: What is threshold voltage (Vth)?

A: The minimum gate-to-source voltage at which a sufficient channel is created to allow current to flow
between drain and source. Below Vth, the device is OFF (subthreshold leakage only). Typical values: 0.3–
0.5V for low-power CMOS at advanced nodes.

Q: What are the three regions of MOSFET operation?

A: Cutoff (VGS < Vth): Device OFF, only leakage. Linear/Triode (VGS > Vth, VDS < VGS-Vth): Device acts as
resistor — Ron = 1/(μCox(W/L)(VGS-Vth)). Saturation (VGS > Vth, VDS ≥ VGS-Vth): Current source — ID =
(μCox/2)(W/L)(VGS-Vth)².

Q: What is gm (transconductance)?
A: The ratio of change in drain current to change in gate voltage at constant VDS. gm = ∂ID/∂VGS =
μCox(W/L)(VGS-Vth) = sqrt(2μCox(W/L)ID). It is the key analog 'gain knob' — higher gm means more

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 current change per volt of input signal. gm×ro gives the intrinsic voltage gain of a single transistor.

Q: What is the body effect?

A: When VSB (source-to-body voltage) ≠ 0, the threshold voltage increases: Vth = Vth0 + γ(sqrt(|2φF +
VSB|) - sqrt(|2φF|)). Physical cause: Reverse bias between source and body increases depletion charge
under the channel, requiring more gate charge to invert. Critical in stacked transistors where body bias
varies.

Q: What is latch-up?
A: A destructive phenomenon in CMOS where a parasitic PNPN thyristor (formed by NPN and PNP BJTs
inherent in the CMOS structure) is triggered, creating a low-impedance VDD-to-GND path that can
permanently damage the chip. Triggered by voltage spikes or high injected currents. Prevented by guard
rings and well taps.

Q: What is DRC?
A: Design Rule Check — automated verification that every drawn shape in the layout meets the foundry's
manufacturing requirements (minimum width, spacing, enclosure, overlap). Zero DRC violations are
required before tapeout. Run with Calibre DRC or Assura.

Q: What is LVS?
A: Layout vs. Schematic — verification that the netlist extracted from the layout exactly matches the
schematic netlist (same devices, same connections). Catches opens, shorts, and device mismatches
introduced during layout. Run with Calibre nmLVS.

Layout Basics
Q: What layers are needed to draw an NMOS transistor?
A: 1) P-Well or P-substrate, 2) OD/Active region (silicon island), 3) NP implant (N+ for S/D), 4) Poly
crossing OD (defines gate), 5) Contacts on S/D OD and poly, 6) M1 connecting to G, S, D. The intersection
of Poly and OD IS the transistor — the channel is formed where poly crosses silicon.

Q: What is a guard ring and why is it used?

A: A ring of substrate contacts (P+ ties to VSS for NMOS; N+ ties to VDD for PMOS) surrounding a device
or block. Purpose: (1) Collect minority carriers to prevent latch-up, (2) Reduce substrate resistance to
minimize noise propagation, (3) Required by foundry for high-voltage devices. Double guard rings (P+
inner + N+ outer) give maximum protection.

Q: Why do we use multiple fingers in a transistor layout?

A: Multiple fingers: (1) Reduce gate resistance Rgate ∝ 1/N, reducing thermal noise (4kT×Rgate), (2)
Reduce drain/source junction area → lower parasitic capacitance, (3) Enable shared drain/source
diffusion between adjacent fingers → saves area, (4) Better matching in interdigitated layouts, (5) Allow
practical layout of very wide transistors.

Q: What is the purpose of dummy devices?

A: Dummy devices (non-functional copies at array edges) serve to: (1) Equalize the STI/LOD environment
for all active devices — every device 'sees' a neighbor on both sides, (2) Balance etch loading for uniform

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 pattern density, (3) Provide symmetric optical proximity correction environment, (4) Reduce well
proximity effect variation. Dummies must have gate connected to a fixed potential (not floating).

Q: What is an antenna violation and how do you fix it?

A: An antenna violation occurs when a metal or poly shape connected only to a gate oxide has an area
ratio (metal area / gate oxide area) exceeding the foundry's limit (typically 400:1). During plasma
processing, charge accumulates on the large metal antenna → can rupture the gate oxide. Fix: (1) Add an
antenna diode (reverse-biased diode to VDD/VSS provides discharge path), or (2) Jump to a higher metal
layer to break the continuous antenna area.

15.2 Intermediate Level Questions

Matching and Mismatch
Q: What is Pelgrom's law?
A: Pelgrom's law describes random Vth mismatch between two nominally identical transistors: σ(ΔVth) =
AVth / sqrt(W×L), where AVth is the Pelgrom coefficient (~2–5 mV·μm for typical CMOS). Implications: (1)
Larger W×L → better matching, (2) Operating at small VGT amplifies Vth mismatch into larger ΔID/ID, (3)
Cannot improve matching beyond AVth limit — set by process. Extended Pelgrom also includes β
mismatch.

Q: Why is common centroid layout used for differential pairs?

A: A differential pair requires that both transistors see identical electrical conditions. Any Vth gradient
across the die creates an offset. In common centroid layout, devices M1 and M2 are placed symmetrically
about a common center (e.g., ABBA pattern). Any linear gradient in Vth adds the same amount to both
M1 and M2 → the differential Vth mismatch (ΔVth = Vth1 - Vth2) cancels to zero for linear gradients. This
directly minimizes input offset voltage.

Q: What is the LOD (Length of Diffusion) effect?

A: The LOD effect (also called WPE — Well Proximity Effect near wells, or STI stress) describes how a
MOSFET's Vth and mobility change based on how far it is from the STI boundary. Devices at the edge of
an active region have compressive stress from STI → different Vth and μ than devices in the center.
Mitigation: Use dummy devices at OD edges to push active devices away from the STI boundary, ensuring
all matched devices have identical LOD on both sides.

Q: How does orientation affect matching?

A: Silicon is anisotropic: crystal properties differ along different axes. Transistors rotated 90° relative to
each other have different electron/hole mobility due to piezoresistive effects. STI stress also differs with
orientation. Result: rotating a transistor 90° can change its ID by 2–5%. All matched transistors MUST
have identical orientation (same direction of current flow from source to drain).

Q: What is interdigitation and when is it used?

A: Interdigitation means interleaving fingers of matched devices: ABABAB... instead of AAABBB. It cancels
linear gradients along the interdigitation axis. Used when: (1) Common centroid is not required (e.g., less
critical matching), (2) Two devices need moderate matching (resistors, capacitors, non-input transistors),
(3) Routing is simpler with interdigitation than full centroid. For critical pairs (diff pair input), use common
centroid instead of/in addition to interdigitation.

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Reliability
Q: Why does electromigration occur?
A: Electromigration is the momentum transfer from electrons to metal atoms (usually Cu) as current
flows. At high current density, electron 'wind' gradually displaces metal atoms from their lattice positions,
creating voids (open circuit) upstream and hillocks (potential short) downstream. Rate governed by
Black's equation: MTF ∝ J^(-n) × exp(Ea/kT). Threshold current density is the key spec — exceed it and
the metal eventually fails.

Q: How do you prevent electromigration in layout?

A: 1) Calculate current density for every metal segment: J = I / (W × t), keep J < foundry JMAX spec. 2) Use
appropriate metal width: look up current-carrying capacity tables from PDK. 3) Use multiple vias (parallel
via arrays) — single via is the weakest point in any current path. 4) Use thicker upper metals for high-
current supply rails. 5) Minimize operating temperature (keep Tjunction low). 6) For AC signals, use RMS
current (AC is less harmful than DC for EM).

Q: What causes NBTI?

A: NBTI (Negative Bias Temperature Instability) in PMOS: When VGS < 0 (PMOS on), high field breaks Si-H
bonds at Si-SiO2 interface → creates interface traps → Vth magnitude increases → PMOS weakens over
time. Follows power law: ΔVth ∝ t^0.25 × exp(-Ea/kT). Recovery occurs when bias is removed (H can re-
passivate). Mitigated by: operating below maximum VGS spec, using HfO2 (less NBTI than SiO2).

Q: What is the antenna effect, and what is an antenna ratio?

A: Antenna effect: During plasma etching/deposition, charge accumulates on conductors connected to
gate oxide. If the charge cannot dissipate, it damages the thin gate oxide. Antenna Ratio = Area of
connected conductor / Area of gate oxide at each process step. Foundry limits: typically 400:1 for metal,
200:1 for poly. Violations caught by antenna DRC check. Fix: antenna diode or route through higher
metal.

Circuit Layout
Q: How do you lay out a high-accuracy bandgap reference?
A: Key steps: 1) BJT pair in 2D common centroid array (Q2=nQ1), all same emitter size/orientation. 2)
Precision poly resistors (P+ poly, non-silicided) in interdigitated arrangement with dummy ends. 3) Op-
amp: matched diff pair in centroid, away from thermal gradients. 4) Entire circuit surrounded by P+ guard
ring and N-well ring. 5) Deep N-well isolation. 6) Bypass caps on VREF and VPTAT nodes. 7) Place away
from power devices. 8) Symmetric supply connections.

Q: What are the key matching requirements for a current DAC?

A: A current DAC uses a binary-weighted array of current sources (unit current I, 2I, 4I, ..., 2^(N-1)I). Key
requirements: 1) All unit current sources identical (Pelgrom: σI/I ∝ 1/sqrt(WL)), 2) Unit devices in
common centroid array, 3) Thermometer-coded MSBs for better linearity (glitch reduction), 4) All unit
transistors same VGS (shared diode-connected reference), 5) Output switches symmetric routing, 6) Deep
N-well isolation from substrate noise, 7) Separate AVDD from DVDD.

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15.3 Advanced Level Questions
Q: What limits the matching of a capacitor array in a SAR ADC?
A: Several effects: 1) Systematic: capacitance per unit area varies across die due to oxide thickness
gradient → common centroid array cancels first-order gradient. 2) Random: edge effects on each cap →
larger unit caps (Pelgrom: σC/C ∝ 1/sqrt(A)). 3) Fringe variation: fringe cap at edges varies with spacing
variation → use common inner/outer topology. 4) Bottom-plate parasitic to substrate: must be uniform
→ common centroid ensures same substrate proximity. 5) Top-plate routing resistance: must be
symmetric. The minimum unit capacitance is set by the required DNL/INL and Pelgrom matching.

Q: How do you minimize 1/f noise in an analog layout?

A: 1/f noise (flicker noise) in MOSFET: S_ID = KF × ID^AF / (Cox × L² × f). Strategies: 1) Large gate area
(W×L) reduces 1/f noise ∝ 1/(WL). 2) PMOS has lower KF than NMOS → use PMOS for sensitive input
stages (e.g., PMOS diff pair in OTA). 3) Avoid shared contacts that create hot spots. 4) Keep device at low
VGS-Vth (lower ID for given gm). 5) In layout: minimize interfaces (no partial channel contacts). 6) Use
chopper stabilization (circuit technique) to up-convert 1/f above signal band.

Q: Explain how substrate noise couples into an analog circuit and how to mitigate it at layout level.
A: Coupling mechanism: Digital CMOS switching injects current into P-substrate through drain-substrate
junction capacitance (Cdb). This current flows through finite substrate resistance to reach nearby analog
circuit bodies, modulating Vth of analog devices (body effect). Mitigation: 1) Physical separation (most
effective for large wavelength noise). 2) Deep N-well under analog block creates reverse-biased P/N
junction barrier that blocks substrate current. 3) P+ guard ring with multiple contacts creates low-
resistance path to analog VSS, diverting injected current. 4) Differential design rejects common-mode
substrate noise. 5) Separate VSS planes for analog and digital, connected only at single point.

Q: How does multi-patterning affect analog layout?

A: Multi-patterning (SADP/SAQP at 7nm/5nm) creates layout constraints: 1) Coloring: Each shape must be
assigned a 'color' (mask); shapes that would be too close in the same mask must be on different masks.
EDA tools auto-color but can fail on odd-loop conflicts. 2) Overlay error: LELE has ≈4nm overlay between
two masks → creates systematic spacing variation → avoid placing matched devices on different color
boundaries. 3) Forbidden pitches: Some pitches are disallowed if they cause coloring conflicts. 4) Impact
on matching: Avoid routes across coloring boundaries for matched nets — the 2D print variation at
boundary can cause systematic mismatch.

Q: Design a 5-bit current-steering DAC layout from scratch. What are your key considerations?
A: Architecture: 5-bit = 31 unit current sources in thermometer code (top 4 bits) + 1-bit binary LSB. Layout
plan: 1) Unit NMOS current source: L = 2×Lmin for better λ (output impedance), W set by current density
and Pelgrom. 2) Array: 31+1 sources in 6×6 = 36 unit array (4 dummies). Common centroid 2D
arrangement. 3) Row/column decoder: binary to thermometer — keep digital decoder far from current
source array with guard ring isolation. 4) Output switches: NMOS/PMOS complementary pairs —
matched, placed at boundary of current array. 5) Output bus: differential current outputs to load —
symmetric routing, equal parasitics on IOUT+ and IOUT-. 6) Bias circuit: cascode current mirror for high-
impedance source — common centroid, shielded. 7) Deep N-well for entire array. 8) Separate AVDD,
DVDD planes.

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15.4 Company-Specific Questions
NVIDIA
Q: How do you achieve low-jitter PLL layout for GPU applications?
A: Key layout: 1) VCO inductor: top 2 metals (thick, low R), differential symmetric, patterned GND shield,
no active circuits below. 2) VCO transistors: deep N-well, common centroid varactor pair, symmetric tail.
3) Charge pump: UP/DOWN current sources in exact common centroid — any mismatch creates
reference spur. 4) Loop filter: place immediately next to CP output, minimize routing. 5) Divider: shielded
from VCO output (magnetic coupling). 6) Reference input: shielded, clean routing, no crosstalk. 7) Supply:
multiple separate VDD domains (VCO_VDD, CP_VDD, etc.) each with own bypass. 8) Phase noise target: <-
130 dBc/Hz @1MHz offset → demands careful substrate isolation.

Q: What is IR drop analysis and how do you run it in a GPU chip?

A: IR drop analysis calculates VDD reduction due to resistive power rails: VDD_node = VDD_pad - Σ(I ×
R_rail_segment). In GPU with billions of transistors switching simultaneously, worst-case IR drop can
exceed 100mV. Flow: 1) Extract complete power grid (Calibre or Voltus). 2) Apply switching activity (from
power estimation or simulation). 3) Calculate static IR (DC analysis) and dynamic IR (transient, from decap
response). 4) Fix: widen rails, add more vias, add decoupling caps, or restructure grid. NVIDIA GPU chips
do this at full-chip level with sign-off tools (Cadence Voltus/Virtuoso IR).

Intel
Q: What makes FinFET layout different from planar layout in Intel's 7nm process?
A: Key differences: 1) Discrete width: W = n × Wfin (~7nm fin, 27nm pitch) — cannot use W=15nm, must
use 1 or 2 fins. 2) Fixed poly pitch: Contacted poly pitch (CPP) ~57nm at Intel 7nm. 3) Routing constraints:
M0 and M1 are very tight pitch → many routing DRC rules. 4) Multi-patterning: Fins use SAQP (4 colors),
M1 may use SADP → strict coloring rules. 5) Self-heating: FinFET fins surrounded by STI oxide → poor
thermal conductivity → self-heating much worse. 6) No body contact: Fin body largely floating → floating
body effects in some circuits. 7) Strain engineering: Built-in stress (embedded SiGe for PMOS, SiP for
NMOS) → cannot add separate stress structures.

Qualcomm
Q: How do you lay out an RF LNA input matching network?
A: LNA layout key considerations: 1) ESD at antenna input: use inductive (ESD coil) or diode pair —
minimize ESD cap (each pF degrades NF by ~0.3 dB at 5GHz). 2) Input matching inductor: spiral inductor in
top 2 metals, symmetric for differential. 3) Source degeneration inductor (Ls): critical for noise matching
— place at NMOS source, tight coupling to gate inductor. 4) Gate transistor: Multi-finger NMOS with gate
contacted at BOTH ends (minimize Rgate → minimize Fmin = 1 + 2πf×Cgs×sqrt(γ×δ/α×RS×Rg)). 5) Metal
routing to gate: ≤50 Ω for NF < 1dB at 5GHz → extremely wide or short routes. 6) Bond wire inductance:
part of matching network — account in simulation. 7) No crossovers over transistor → coupling.

Texas Instruments
Q: How do you lay out a precision 16-bit DAC for instrumentation?
A: 16-bit DAC requirements: DNL < 0.5 LSB = 7.6μV for 0.5V FS. Key layout: 1) R-2R ladder or segmented
current-steering with unit resistors/current sources. 2) Resistor matching: Pelgrom σR/R = AR/sqrt(WL) <
0.001% → very large unit resistors (wide W, long L) in centroid 2D array. 3) All resistors same poly type,

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 same orientation, same enclosure. 4) Kelvin connections for precision reference. 5) Output amplifier:
zero-offset OTA with chopper → interdigitated PMOS diff pair. 6) Decoupling on reference voltage (VREF)
must be very clean → isolated supply. 7) No substrate noise coupling → deep N-well, maximum guard
rings. 8) Temperature gradient management → symmetric die placement.

Broadcom
Q: Explain your approach to laying out a 56Gbps SerDes lane.
A: 56Gbps SerDes (PAM-4, 28GBaud) layout: 1) Differential pair TX output: matched routing to bond
pad/bump, <0.1mm routing, controlled impedance (100Ω diff). 2) RX input: ESD (1kV HBM via inductive
scheme, <30fF total), matched to 100Ω diff impedance. 3) CDR (Clock Data Recovery): VCO inductor on
top metal, matched phase detector. 4) TX driver: large CML driver, EM-clean supply, bypass immediately
on die. 5) Equalizer (DFE): digital intensive — separate domain from analog CDR. 6) Eye diagram: post-
layout sim must show open eye at 56Gbps with all PVT corners. 7) DFE feedback path: critical timing —
absolute minimum routing length. 8) Top-level floorplan: TX and RX of each lane side-by-side, shield TX
from RX (isolation).

Samsung
Q: What are the unique challenges of DRAM analog layout?
A: DRAM analog: 1) Sense amplifier (SA): most critical matched structure in chip. Cross-coupled PMOS
and NMOS latch — any mismatch → bit cell sensing error. Use absolute minimum area common centroid.
2) Word line driver: high drive strength → wide metal EM, self-heating concern. 3) Charge pump:
generates sub-1V and >3V from VDD — layout must handle high voltage (use IO/thick-oxide devices). 4)
Reference voltage (VREF): controls sensing threshold — extreme temperature and process sensitivity. 5)
Array address decoder: high fanout → large drivers → careful IR drop and EM. 6) Refresh circuit: periodic
high-current pulses → EM in supply rails. 7) PHY (DDR5): source-synchronous → tight skew matching on
CLK and DQ lanes.

Micron
Q: How do you ensure NAND Flash analog circuit reliability?
A: NAND Flash analog: 1) High voltage generation (charge pump to 16–20V for programming): Use
HVNMOS (thick ox, extended junction) devices. EM rules for high-current pump. 2) Sensing: very sensitive
pre-amplifier (cell current ~nA) — extreme matching, zero substrate noise allowed. 3) Verify charge pump
voltage: post-layout simulation with extracted parasitic capacitances (huge impact on pump efficiency). 4)
Program/erase voltage stress: devices see 20V for μs pulses → TDDB and HCI reliability critical. Use
rounded corners in poly to avoid field crowding. 5) Temperature compensation: pump voltage must track
temperature. Bandgap reference with < ±1% TC. 6) Word line leakage: GIDL from unselected cells → tight
layout of access transistors.

15.5 Additional Critical Interview Questions

Q: What is the difference between weak inversion, moderate inversion, and strong inversion?
A: Weak inversion (subthreshold, VGS < Vth): Exponential ID-VGS. Best gm/ID ratio (current efficiency) →
used in ultra-low power circuits. Moderate inversion (VGS ≈ Vth): Transition region. Strong inversion (VGS
>> Vth): Classic square-law region. ID ∝ (VGS-Vth)². Layout: In weak inversion, W must be very large for
same current → large area devices, excellent matching due to Pelgrom (large WL).

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Q: How do you measure offset voltage of an op-amp in post-layout simulation?
A: Set up unity-gain feedback configuration: Vout connected to V-. Apply a reference voltage to V+. Run
DC sweep or DC operating point. VOS = Vout - V+ at equilibrium. For Monte Carlo mismatch simulation:
Run 1000 MC mismatch-only iterations. Extract VOS distribution → mean (systematic offset) and σ
(random offset). σVOS should be < 1 LSB for ADC applications or per spec. In layout: Improve by
maximizing input pair WL, ensuring symmetric routing, adding dummy devices.

Q: What is PSRR and how does layout affect it?

A: Power Supply Rejection Ratio: PSRR = ΔVout/ΔVDD | Vout ideally constant. Poor PSRR means supply
noise appears at output. Layout affects PSRR through: 1) Tail current source impedance (high Rout →
better PSRR). 2) Supply line coupling to sensitive nodes (minimize parasitic caps from VDD rail to diff pair
gates or drains). 3) Symmetric routing: if VDD couples equally to both halves, differential circuits reject it.
4) Bypass caps: large bypass at VDD of bias circuits → low-impedance supply → PSRR improves at high
frequency. Measured: AC simulation from VDD to Vout at each frequency.

Q: What is the significance of flicker noise corner frequency?

A: Flicker noise (1/f) power density: Sv = Kf / (Cox × W × L × f). Flicker corner frequency fc: where 1/f noise
equals thermal noise. fc = Kf × gm / (4kT × Cox × WL × α). At f > fc: thermal noise dominates. At f < fc: 1/f
dominates. For audio ADCs (fs = 48kHz, signal band 0–20kHz): 1/f noise is critical → use large PMOS input
devices (lower Kf for PMOS). For RF circuits (f > 1GHz): 1/f is irrelevant (far below signal band). Layout
impact: Larger WL → lower fc → less 1/f noise in band.

Q: Why are current mirrors used instead of resistors for biasing?

A: Resistor biasing has poor PSRR and TC: IBIAS = (VDD - VBE) / R → depends on VDD directly. Current
mirror copies a reference current (from bandgap): IBIAS = IREF × (W/L)out / (W/L)ref → independent of
VDD (as long as VDS > VODsat). Also, current mirrors can achieve very precise ratios if well-matched.
Layout: Current mirror ratio accuracy limited by Pelgrom matching → larger devices for better accuracy.
Cascode mirror gives even higher output impedance → better PSRR.

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 PART 16
INDUSTRY PROJECTS

Part 16: Step-by-Step Industry Layout Projects

This section provides complete walkthroughs of real analog layout projects. Follow each step exactly as you
would in industry using Cadence Virtuoso.

Project 1: Basic Current Mirror (1:2 Ratio)

Specifications:
• IREF = 10μA, IOUT = 20μA
• NMOS, TSMC 180nm, L = 0.5μm (2× Lmin), W = 4μm, 2 fingers each
• Target current mismatch: < 0.5%

Step 1: Schematic
• Place M_ref: W=4μm, L=0.5μm, 2 fingers. Gate connected to drain (diode-connected).
• Place M_out: W=4μm, L=0.5μm, 2 fingers × 2 = 4 fingers total (or 2 devices of same size, 2 in parallel).
• Connect all sources to VSS, all gates together.
• Verify simulation: IOUT/IREF = 2.00 ± 0.01

Step 2: Floorplan
• 3-section array: M_out(2 fingers) | M_ref(2 fingers) | M_out(2 fingers) → interdigitated
• Add 1 dummy finger on each outer edge → total 8 fingers
• P-well region below, VSS below that

Step 3: Active and Poly

• Draw single OD rectangle spanning all 8 fingers (shared diffusion across all)
• Draw poly crossing OD at each gate position (equal spacing = L + spacer)
• Extend poly beyond OD on both ends (per DRC enclosure rule)
• Verify: M_ref poly at position 3, M_out poly at positions 2, 4
• Dummy poly at positions 1, 8 (tie to VSS)

Step 4: Contacts and Metal

• Place contacts: maximum allowed in S/D between each poly pair
• Place contacts on each poly gate (both sides preferred)
• M1 routing: VSS rail below — connects to all sources via contacts

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 • M1 gate rail: horizontal bar connecting gates of M_ref and both M_out
• M1 drain of M_ref: connect up to IREF input port
• M1 drains of M_out: two drain nodes — both M_out drains connect to IOUT port

Step 5: Guard Ring

• P+ diffusion ring around entire device array, 1μm wide, filled with contacts to M1
• M1 ring connects P+ guard ring to VSS

Step 6: Verification
57. Run DRC: fix all violations
58. Run LVS: verify M_ref W=4μm×2fingers and 2×M_out W=4μm×2fingers, all connections correct
59. Run PEX: extract R and C
60. Post-layout simulation: verify IOUT/IREF = 2 ± 0.5% over SS/TT/FF at -40°C/27°C/125°C
61. Monte Carlo: verify 3σ current mismatch < 1%

Project 2: Folded Cascode OTA

Specifications:
• TSMC 28nm HKMG, VDD = 1.0V, AVDD = 1.1V
• DC Gain > 60 dB, GBW > 100 MHz, Phase Margin > 60°
• Load capacitance = 1 pF

Architecture:
• PMOS differential input pair (M1, M2): W=12μm/L=0.2μm, 12 fingers each
• Tail current source (M3): PMOS, W=8μm/L=0.2μm
• NMOS cascode (M4, M5): W=8μm/L=0.2μm, 8 fingers each
• PMOS cascode (M6, M7): W=16μm/L=0.2μm, 16 fingers each
• NMOS cascode bias (M8): W=8μm/L=0.2μm
• PMOS cascode bias (M9): W=16μm/L=0.2μm

Layout Plan:
62. P-well (bottom): NMOS cascode M4/M5 block
63. N-well (top): PMOS diff pair M1/M2 (center, common centroid), PMOS casodes M6/M7 (interdigitated pair)
64. Tail M3 above M1/M2
65. Bias devices M8, M9 to the side

Critical layout steps:

• M1/M2: ABBA/BAAB common centroid with 2 dummy on each side. Total 28 fingers array. Gate connections:
M1 gate to IN+, M2 gate to IN-. Route IN+/IN- as symmetric, shielded differential pair from input ports.
• M4/M5 cascode pair: interdigitated M4/M5 below P/N boundary
• VCASP, VCASN bias wires: horizontal routes with 1pF bypass caps in MIM
• VOUT node: minimal parasitic routing → single wide M2 to load
• Guard rings: P+ ring around NMOS area, N-well ring + P+ ring around PMOS area, outer guard ring around all
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 • Deep N-well under entire OTA if available

Project 3: Two-Stage Miller-Compensated Op-Amp

Stage 1: Differential input
• PMOS diff pair M1/M2 (common centroid, 8+8 fingers with 4 dummies)
• NMOS current mirror load M3/M4 (interdigitated)
• PMOS tail current M5

Stage 2: Common-source amplifier

• NMOS M6 (large, W/L = 40μm/0.15μm, 40 fingers) — drives output
• PMOS M7 load (W/L = 20μm/0.15μm)

Compensation:
• Cc (Miller cap): MIM cap, 500fF, placed between Stage1 output (Vout1) and Stage2 output (Vout)
• Rc (nulling resistor, optional): in series with Cc to move RHP zero → increases PM

Layout plan:
• Stage 1 diff pair: center of block, highest priority
• Stage 1 load mirrors: on sides of diff pair
• Stage 2 M6: large device below, separate from Stage 1 to avoid output coupling to input
• Cc: MIM cap, bottom plate to Vout1 (lower impedance side preferred), top plate to Vout
• Input pads IN+/IN-: come from top, balanced routing
• Output: VOUT to the right
• All bias wires: horizontal, bypassed

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 PART 17
CADENCE VIRTUOSO GUIDE

Part 17: Cadence Virtuoso Complete Guide

17.1 Schematic Design in Virtuoso
Creating a Cell:
66. File → New → Cellview → Select Library, Cell name, Schematic
67. Press 'I' to add instance → select foundry PDK cells (nmos4, pmos4, res, cap)
68. Press 'W' to add wire, 'L' for label, 'P' for port
69. Set device parameters: right-click device → Properties → set W, L, fingers, multiplier
70. Add power/ground symbols: vdd! and gnd! for global supply/ground
71. Check & Save: Design → Check & Save (eliminates unconnected pins, floating labels)

Common Keyboard Shortcuts in Schematic:

Key Action

I Add Instance (place device)

W Add Wire

L Add Wire Label/Net name

P Add Port (pin)

Q Properties of selected object

F Fit view to window

Ctrl+S Save

U Undo

Del Delete selected

M Move selected

C Copy selected

17.2 ADE — Analog Design Environment

Setting up a simulation:
72. Open ADE: Launch → ADE L (or ADE XL for corners)

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 73. Load testbench schematic
74. Select simulator: Spectre preferred for analog (HSPICE for digital)
75. Setup → Model Libraries → add foundry .scs model files (TT/SS/FF)
76. Analyses → Choose → Add analysis type:
• DC sweep: sweep Vin, print ID vs VGS → extract Vth, gm, gds
• AC analysis: small-signal, set start/stop frequency → extract gain, phase, GBW, PM
• Transient: time-domain, set stop time and step → settling time, slew rate
• Noise: noise spectral density, integrate for total noise
• PSS: Periodic Steady State for PLLs, oscillators
77. Variables: Setup → Variables → define device parameters, set sweep ranges for corners
78. Outputs: Choose what to plot (currents, voltages, gain)
79. Run: Simulation → Netlist and Run

Monte Carlo in ADE XL:

80. ADE XL → Setup → Process/Mismatch → Enable MC
81. Set number of iterations (200–1000 for 3σ)
82. Run Mismatch MC (local variation) and Process MC (global) separately or combined
83. Plot histograms of key specs (VOS, gain, bandwidth)
84. Extract mean and σ from distribution → verify spec: spec_limit > mean ± 3σ

17.3 Layout XL in Virtuoso

Opening Layout:
85. From schematic: Connectivity → Generate → All from Source → creates layout from schematic with devices
(not yet routed)
86. OR: New cellview → Layout type → blank canvas

Key Layout Operations:

• Select layer: In LSW (Layer Selection Window) on left — click desired layer
• Draw rectangle: Press 'R', click two corners
• Draw path (wire): Press 'P' for path, select width → route like a wire
• Add contact: Select contact cell from PDK library, place with 'I'
• Rotate: Press 'R' during placement to rotate
• Mirror: Edit → Mirror → choose axis
• Snap grid: Virtuoso snaps to manufacturing grid (e.g., 0.005μm for 28nm)

Assura vs Calibre in Virtuoso:

Assura: Cadence's native DRC/LVS tool — integrated, faster setup, but may not match foundry sign-off rules
Calibre: Mentor/Siemens tool — industry standard, exact foundry sign-off rules, slower setup but trusted
For foundry tapeout: always use Calibre with foundry-provided rule files. Assura for quick checks during
development.

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17.4 Calibre DRC Run Flow
87. In Virtuoso Layout: Calibre → Run DRC
88. DRC Setup window: Specify rule file path, top cell name, output directory
89. Layout: Export GDS (or run in-memory stream-out)
90. Run → Calibre DRV opens showing violations
91. In DRV: double-click a violation → layout highlights the offending shapes
92. Fix each violation:
• M1 spacing: Select one shape → Edit → Properties → adjust width or position
• Enclosure violation: Extend enclosing layer rectangle
• Density: Add metal fill (use automatic metal fill after completing circuit)
93. Re-run DRC → confirm 0 violations → sign off

17.5 Calibre nmLVS Run Flow

94. Export schematic CDL netlist: In schematic, File → Export Netlist → CDL → save .cdl file
95. In Virtuoso Layout: Calibre → Run nmLVS
96. LVS Setup: Select LVS rule file, load schematic CDL as reference, select top cell
97. Run → Calibre generates layout-extracted netlist and compares to schematic CDL
98. View LVS output:
• Discrepancies: Listed as shorts, opens, device mismatches
• Highlighting: Select a net mismatch → highlights in both layout and schematic
• Net list comparison: Shows matched and unmatched nets
99. Common fix workflow:
• Short: Find the shorted nets, locate in layout, remove or separate overlapping shapes
• Open: Trace the broken net → find missing contact, via, or metal → add it
• Device W mismatch: Check that layout W matches schematic exactly (account for fingers × individual W)

17.6 PEX (Parasitic Extraction) Flow

100. In Virtuoso Layout: Calibre → Run PEX
101. PEX Setup: Select RC extraction rule file (xRC or QRC), output format (SPECTRE or HSPICE)
102. Set extraction type: C-only, RC, or RC+Coupling
103. Run → generates extracted netlist (.spi) with R and C annotations
104. In Virtuoso: File → Open → extracted view (av_extracted or pex cellview)
105. In ADE: Change schematic to extracted view → re-run simulations
106. Compare pre-layout vs post-layout results → document degradations

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 PART 18
CAREER ROADMAP

Part 18: Roadmap to Become Top 1% Analog Layout Engineer

This roadmap is based on real hiring practices at NVIDIA, Intel, Qualcomm, TI, and Broadcom. It takes you from
zero to interview-ready in 12 months with a structured daily plan.

18.1 Month-by-Month 12-Month Roadmap

Month Topics to Master Projects Resources

1 Semiconductor fundamentals, Simulate MOSFET IV curves in Neamen Semiconductor

PN junction, MOSFET basics, LTSPICE or Ngspice Physics, Razavi CMOS
band theory textbook Chapter 1-3

2 MOSFET regions, gm, go, body Sweep VGS/VDS, extract gm, Tsividis MOS Transistor book,
effect, channel length ro. Plot gm vs ID. Razavi Ch 1-4
modulation, SCE

3 CMOS circuits: inverter, Design and simulate a basic Razavi Design of Analog
current mirrors, diff pair, current mirror and diff pair CMOS ICs, Allen & Holberg
cascode basics

4 Fabrication: STI, wells, gate, Learn Virtuoso basics using TSMC educational materials,
contacts, BEOL. Layout layers. free trial or university access YouTube Virtuoso tutorials

5 Layout rules (DRC), matching Layout a current mirror using Maloberti Layout of Analog
(common centroid, proper matching techniques CMOS ICs, Baker CMOS
interdigitation, dummies), Circuit Design
Pelgrom

6 Passive devices (poly R, MIM Layout resistor and capacitor Razavi RF Microelectronics
cap, spiral inductor), parasitics, arrays. Run PEX and compare (inductor chapter), foundry
extraction schematic vs extracted. PDK documents

7 Reliability: EM, IR drop, ESD, Analyze EM violations in a Weste & Harris CMOS VLSI
latch-up, antenna, NBTI, TDDB given layout. Calculate Design, Klaassen reliability
current density. papers

8 Advanced circuits: OTA, op- Full layout + DRC + LVS + PEX Johns & Martin Analog IC
amp, comparator, bandgap + post-layout sim of a folded Design, Razavi Design of
layout cascode OTA Analog ICs

9 LDO, charge pump, PLL layout. Layout a basic LDO or charge Leung LDO Regulators, IEEE
Floorplanning strategies. pump. Verify all specs post- JSSC papers on PLLs
layout.

10 ADC/DAC layout (SAR ADC, SAR ADC capacitor array Razavi Principles of Data

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 current DAC). Advanced layout. Monte Carlo matching Conversion, IEEE JSSC ADC
matching. analysis. papers

11 FinFET, advanced nodes, RF Study 7nm design rule FinFET process papers
layout, substrate noise, multi- manuals. Layout an LNA if RF (IEDM), TSMC/Intel
patterning tools available. technology briefs

12 Interview prep: 500+ Q&A Full design project: complete This handbook, company job
review, full project portfolio, OTA or bandgap from spec to descriptions, LinkedIn
company research post-layout sim research

18.2 Daily Schedule (During Active Job Search)

Time Activity Details

6:00–7:00 AM Review fundamentals Read 10 pages of core textbook. Review yesterday's notes.

7:00–9:00 AM Hands-on layout Work on current project in Virtuoso. Practice DRC/LVS

debugging.

9:00–11:00 AM Interview Q&A Study 20 Q&A from this handbook. Write answers in your own
words.

11:00–12:00 YouTube / Video lecture Watch a Virtuoso tutorial or circuit lecture. Take notes.
PM

1:00–3:00 PM Simulation practice Run ADE simulations: DC, AC, Transient, Noise, MC. Analyze
results.

3:00–5:00 PM Reading / Research Read 2 IEEE JSSC papers in your target area. Summarize key
points.

5:00–6:00 PM Mock interview Practice explaining concepts aloud. Record yourself. Review.

6:00–7:00 PM Networking LinkedIn connections, industry forums, attend virtual seminars.

18.3 Essential Books

• Razavi — Design of Analog CMOS Integrated Circuits (Bible of Analog IC Design)
• Razavi — RF Microelectronics (for RF/Wireless roles)
• Johns & Martin — Analog Integrated Circuit Design
• Allen & Holberg — CMOS Analog Circuit Design
• Maloberti — Layout of Analog CMOS Integrated Circuits (THE layout book)
• Weste & Harris — CMOS VLSI Design: A Circuits and Systems Perspective
• Neamen — Semiconductor Physics and Devices
• Baker — CMOS Circuit Design, Layout, and Simulation (hands-on)
• Pelgrom — Analog-to-Digital Conversion
• Tsividis — Operation and Modeling of the MOS Transistor (advanced device physics)

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18.4 Key IEEE Journals and Conferences
• IEEE Journal of Solid-State Circuits (JSSC) — premier analog IC journal
• IEEE Transactions on Circuits and Systems I & II (TCAS)
• ISSCC — International Solid-State Circuits Conference (industry benchmark papers)
• CICC — Custom Integrated Circuits Conference
• VLSI Symposium (VLSI Circuits and Technology)
• IEEE Transactions on Electron Devices (TED) — device physics
• IEDM — International Electron Devices Meeting (process technology)

18.5 Online Resources and YouTube Channels

• Cadence on YouTube: Official tutorials for Virtuoso, ADE, Calibre
• NPTEL IIT courses: Free video courses on VLSI design and semiconductor devices
• EEVblog: Practical electronics concepts
• MIT OpenCourseWare 6.012: Microelectronic Devices and Circuits
• Coursera/edX: VLSI CAD courses by UIUC
• SiliconMentor YouTube: Cadence Virtuoso tutorials, DRC/LVS walkthroughs
• CMOS Layout on Udemy: Practical layout courses with hands-on exercises

18.6 Skills Expected by Top Companies

Company Primary Layout Focus Key Technical Expectations

NVIDIA GPU mixed-signal, PLL, SerDes, power PLL layout, EM/IR analysis, FinFET, advanced
delivery node (7nm/5nm)

Intel CPU analog IPs, VCO, LDO, SerDes PHY Intel process knowledge, FinFET/RibbonFET,
EMIB packaging

Qualcomm RF, modem analog, 5G mm-wave RF layout, inductor, PA, LNA, matching
network, Smith chart

AMD CPU/GPU analog, I/O, memory PHY TSMC 7nm/5nm layout, SerDes, DDR PHY,
chiplet design

TI Precision analog, ADC/DAC, power Precision matching, bandgap, LDO,

management SAR/Delta-Sigma ADC layout

Broadcom Ethernet PHY, optical, data center ICs High-speed SerDes, PAM-4, CDR, 100G+
Ethernet PHY

Samsung DRAM/NAND, Exynos SoC, RF chips Memory analog (sense amp, charge pump),
FinFET/GAA (3nm)

Micron DRAM, NAND analog IPs Sense amplifier matching, charge pump,
high-voltage device layout

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18.7 Interview Day Checklist
Technical Preparation (1 week before):
• Review all 18 parts of this handbook
• Practice drawing layouts on paper (common centroid, diff pair, current mirror)
• Know your projects: explain what, why, how, and results
• Prepare 3 examples of DRC/LVS/PEX debug you have done
• Know the company's process node and products (research on website)

Concepts to know cold (no hesitation):

• Why common centroid? How does it work?
• What is Pelgrom's law? σVth formula?
• What causes EM? How to prevent?
• What is latch-up? How guard rings help?
• What is antenna effect? How to fix?
• Why use fingers? Effect on Rgate and noise?
• What is body effect? VSB effect on Vth?
• 3 regions of MOSFET operation with ID equations
• What is the difference between DRC, LVS, PEX?
• How does substrate noise couple? How to isolate?

Soft Skills:
• Be ready to draw on whiteboard: layout patterns, cross-sections, circuit topologies
• Think aloud: interviewers want to hear your reasoning process
• Ask clarifying questions before answering complex design problems
• Show enthusiasm for the specific company's technology area

18.8 Final Key Principles for the Top 1%

107. Physical intuition first: Always understand WHY before HOW. Rules without intuition → mistakes
under pressure.
108. Matching is king: 80% of analog layout quality comes from matching technique. Master common
centroid.
109. Parasitics are everywhere: Never forget that every line you draw has R and C. Simulate after PEX.
110. Reliability is non-negotiable: EM, IR, ESD, latch-up failures destroy products. Learn rules, follow
them.
111. Verification closes the loop: DRC + LVS + PEX + simulation = one complete iteration. Never skip steps.
112. Document everything: Track your layout decisions. Future you (and your team) will thank you.
113. Understand the process: Visit foundry documents. Know STI, wells, poly, contacts at 180nm AND at
7nm.
114. Think system-level: Great layout engineers consider how their block affects the full chip (substrate
noise, IR drop, thermal).

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 115. Continuous learning: Semiconductor technology changes every 2 years. Read ISSCC, IEDM papers
regularly.
116. Build a portfolio: Have at least 3 complete layout projects with DRC/LVS/PEX clean status and post-
layout simulation results.

END OF HANDBOOK — You now have everything needed to become an industry-ready Analog Layout
Engineer.

Good luck — the industry needs skilled analog layout engineers. Go build great chips.

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