Microprocessor Memory Interfacing Practice
1. Understanding the Concept: Interfacing 4KB RAM using 1KB RAM
Chips
For a microprocessor to see four 1KB chips as a single continuous 4KB memory block, we use
a technique called Memory Decoding. Here is how it works:
1. Number of Chips: You need 4 chips (4KB ÷ 1KB = 4).
2. Address Lines per Chip (1KB): 1KB is equal to 210 (1024) bytes. Therefore, each chip has 10
address lines (A0 to A9). These pins are connected in parallel across all four chips.
3. Address Lines for the Entire System (4KB): 4KB requires 12 address lines (212 = 4096). The
system will use A0 to A11.
4. Decoder Function (Chip Selection): The two extra address lines (A10 and A11) are fed into
a 2-to-4 Line Decoder (e.g., IC 74LS138) to select the correct chip:
◦ A11=0, A10=0 → Enables Chip 1 (000H - 3FFH)
◦ A11=0, A10=1 → Enables Chip 2 (400H - 7FFH)
◦ A11=1, A10=0 → Enables Chip 3 (800H - BFFH)
◦ A11=1, A10=1 → Enables Chip 4 (C00H - FFFH)
Diagram: Interfacing 4KB RAM using four 1KB RAM chips
CS
RAM 1
(1KB)
MICROPROCESSOR
Y0
A11 2-to-4 Y1
A10 Decoder Y2 CS
RAM 2
(74LS138) (1KB)
Y3
Address Bus (A0 - A9) CS
RAM 3
(1KB)
Data Bus (D0 - D7)
CS
RAM 4
(1KB)
2. Practice Questions
Question 1: Address Lines Calculation
If you are tasked with designing an 8KB memory system using 2KB RAM chips:
a. How many 2KB chips will you need?
b. How many address lines will need to be connected directly to each chip (A0 to An)?
c. Which address lines will be fed into the decoder for 'Chip Selection'?
Question 2: Address Mapping
In the system mentioned above (creating a 4KB RAM using 1KB RAM chips), if the very first
chip starts at the address 0000H, at what Hexadecimal address will the second chip (Chip 2)
start? (Show your working).
Question 3: Understanding Decoder Function
The system diagram shows a microprocessor using a 2-to-4 decoder to interface RAM. If the
microprocessor's outputs on the address bus are A11=1 and A10=0, while the remaining
address lines (A9 to A0) are all 1 (i.e., 11 1111 1111 in binary):
a. Which of the four chips (Chip 1, 2, 3, or 4) will be active (enabled)?
b. Write down this physical memory address in Hexadecimal format.
Question 4: Memory Capacities (Word Size Difference)
There is a difference between increasing storage capacity and increasing word length. You are
given two RAM chips with a capacity of 1K × 4-bit. Your microprocessor uses an 8-bit data bus.
Explain how you will connect these two chips so that your processor can read and write 8-bit
data simultaneously. (State how you will connect the Address lines and Data lines).
Question 5: Control Signals Interfacing
When interfacing SRAM, we use three main control pins: Chip Enable/Select (CE/CS), Output
Enable (OE), and Write Enable (WE).
If the processor wants to read (READ operation) data from the RAM, state the required status
(Logic: High or Low) for these three pins (CS, OE, and WE) for the read operation to be
successful.
3. Marking Scheme
Answer to Question 1
a. Chips required = 8KB / 2KB = 4 Chips.
b. 2KB = 2048 bytes = 211. Therefore, you will need 11 address lines (A to A ) for each chip.
0 10
c. The entire 8KB system is 213, meaning it uses 13 address lines (A to A ). Since A to A
0 12 0 10
go to the chips, A11 and A12 will go into the decoder.
Answer to Question 2
A 1KB chip has a size of 1024 bytes. In Hexadecimal, 1024 is represented as 400H (162 × 4).
If Chip 1 occupies from 0000H to 03FFH (which is a step of 1024), then the second chip will
start where the first chip ends. Thus, Chip 2 will start at the address 0400H.
Answer to Question 3
a. The decoder uses A11 and A10. If A11=1 and A10=0, in binary 10 means 2 (starting from 0).
Therefore, it will enable Chip 3 (or the third chip in the sequence).
b. The address is: A11=1, A10=0, and A9 to A0 = 11 1111 1111.
In binary, this is: 0000 1011 1111 1111.
In Hexadecimal, it is: 0BFF H.
Answer to Question 4
To create a 1K × 8-bit memory from 1K × 4-bit chips, you need to connect them in parallel to
increase the 'word size'.
• Address lines: All 10 address lines (A0 - A9) will be connected in parallel to both chips. Chip
Select (CS) will also be connected in parallel since both need to be active at the same time.
• Data lines: The first chip will handle the first half of the data bus (e.g., D0 to D3), and the
second chip will handle the second half of the data bus (D4 to D7).
Answer to Question 5
For a READ operation:
• CS (Chip Select): Must be LOW (Active) to enable the chip.
• OE (Output Enable): Must be LOW (Active) to allow data to exit the memory onto the data
bus.
• WE (Write Enable): Must be HIGH (Inactive) to prevent new data from being written into
the memory during a read cycle.