Lesson Plan
Academic year: 2025-26
College Name: Dr. SMCE
(W.E.F: 23-02-2026 to 25-06-2026)
Programme: BE / Branch: ECE / Scheme: 2022 Semester: IV SEM
Course Name: VLSI Design and Testing LAB Course Code: BECL606
Total contact hours:
IA Marks: 50
10 LAB Hours
Faculty Name: Dr. Kishan Chand T.R Reviewed by: Mrs. Sushma R
Signature: Signature:
Significance of the Course:
The significance of vlsi design and testing lab is to enable efficient signal processing, data transmission, and
reception, enabling seamless connectivity and improved communication capabilities.
Course Objectives:
1) Design, model, simulate and verify digital circuits.
2) Perform ASIC design flow and understand the process of synthesis, synthesis constraints and evaluating the synthesis
reports to obtain optimum gate level netlist.
3) Perform RTL-GDSII flow and understand the ASIC Design flow.
Course Outcomes:
CO1: Design and simulate combinational and sequential digital circuits using Verilog HDL.
CO2: Understand the synthesis process of digital circuits using EDA tool.
CO3: Perform ASIC design flow and understand the process of synthesis, synthesis constraints and evaluating the synthesis
reports to obtain optimum gate level netlist.
CO4: Design and simulate basic CMOS circuits like inverter, NOR gate and any Boolean expression.
CO5: Perform RTL_GDSII flow and understand the stages in ASIC design.
Module No Teaching Blooms
Class & Hours aids Date level
Topic to be covered CO’s Remarks
No as per (CT/Online/ (Refer
University PPT) Planned Completed Below)
Design a 4-Bit Adder LAB 1
• Write a Verilog
1. description. 1
• Verify the Functionality
using Test-bench.
• Synthesize the design by LAB 1
setting proper constraints
IPCC LAB and generate the gate level
netlist. From the report
2. generated identify Critical 1
path, Maximum delay, Total
number of cells, Power
requirement and Total area
required.
4-Bit Shift and add LAB 1
3. 1
Multiplier\
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• Write Verilog Code.
• Verify the Functionality
using Test-bench.
Synthesize the design by LAB 1
setting proper constraints
and obtain the gate level
netlist. From the report
4. generated identify Critical 1
path, Maximum delay, Total
number of cells, Power
requirement and Total area
required.
32-Bit ALU Supporting 4- LAB 1 2
Logical and 4-Arithmetic
operations, using case and if
statement for ALU
5.
Behavioral Modeling
• Write Verilog description.
• Verify functionality using
Test-bench.
• Synthesize the design LAB 1,2 2
targeting suitable library and
by setting area and timing
constraints.
6.
• Tabulate the Area, Power
and Delay for the
Synthesized netlist.
• Identify Critical path.
Flip-Flops ( D,SR and JK ) • LAB 1,2 2
Write the Verilog
7. description.
• Verify the Functionality
using Test-bench.
• Synthesize the design by LAB 1,2 2
setting proper constraints
and obtain the gate level
netlist. From the report gate
level netlist identify Critical
path, Maximum delay, Total
8. number of cells, Power
requirement and Total area
required. • Verify the
functionality using Gate
level netlist and compare the
results at RTL and gate level
netlist.
Four bit Synchronous MOD- LAB 1,2 3
N counter with
Asynchronous reset
9.
• Write Verilog Code.
• Verify functionality using
Test-bench.
• Synthesize the design LAB 1,2 3
10.
targeting suitable library and
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by setting area and timing
constraints.
• Tabulate the Area, Power
and Delay for the
Synthesized netlist Identify
Critical path.
• Verify the functionality
using Gate level netlist and
compare the results at RTL
and gate level netlist.
a) Construct the schematic LAB 1,2,3 3
of CMOS inverter with load
capacitance of 0.1pF and set
the widths of inverter with
Wn = Wp, Wn = 2Wp, Wn
= Wp/2 and length at
selected technology. Carry
out the following:
i. Set the input signal to a
pulse with rise time, fall
time of 1ns and pulse width
11. of 10ns and the time period
of 20ns and plot the input
voltage and output voltage
of designed inverter?
ii. From the simulation result
compute tpHL, tpLH and td
for all three geometrical
settings of width?
iii. Tabulate the results of
delay and find the best
geometry for minimum
delay for CMOS inverter.
b) Draw layout of inverter LAB 1,2 3
with Wp/Wn = 40/20, use
optimum layout methods.
Verify for DRC and LVS,
12. extract parasitic and perform
post layout simulations,
compare the results with pre
layout simulations and
compare the results.
Capture the schematic of 2- LAB 1,2 4
input CMOS NOR gate
having similar delay as that
of CMOS inverter computed
in experiment above.
Verify the functionality of
13.
NOR gate and also find out
the delay td for all four
possible combinations of
input vectors.
Table the results. Increase
the drive strength to 2X and
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4X and tabulate the results.
Construct the schematic of LAB 1,2,3 4
the Boolean Expression Y=
AB+CD+E using CMOS
Logic.
Verify the functionality of
14.
the expression find out the
delay td for some
combination of input
vectors.
Tabulate the results.
a) Construct the schematic LAB 1,2,3 4
of Common Source
Amplifier with PMOS
Current Mirror Load and
find its transient response
and AC response?
15. Measure the Unit Gain
Bandwidth (UGB),
amplification factor by
varying transistor
geometries, study the impact
of variation in width to
UGB.
b) Draw Layout of common LAB 1,2 4
source amplifier, use
optimum layout methods.
Verify for DRC & LVS,
16. extract parasitic and perform
post layout simulations,
compare the results with
pre-layout simulations.
Record the observations.
a) Construct the schematic LAB 1,2,3 5
of two-stage operational
amplifier and measure the
following:
i. Unity gain Bandwidth. ii.
dB Bandwidth.
iii. Gain Margin and phase
margin with and without
coupling capacitance.
17. iv. Use the op-amp in the
inverting and non-inverting
configuration and verify its
functionality.
v. Study the UGB, 3dB
bandwidth, gain and power
requirement in op-amp by
varying the stage wise
transistor geometries and
record the observations.
b) Draw layout of two-stage LAB 1,2 5
18.
operational amplifier with
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minimum transistor width
set to 300 (in 180/90/45 nm
technology), choose
appropriate transistor
geometries as per the results
obtained in part a. Use
optimum layout methods.
Verify for DRC and LVS,
extract parasitic and perform
post layout simulations,
compare the results with
pre-layout simulations and
perform the comparative
analysis.
UART LAB 1,2 5
• Write Verilog description.
19.
• Verify the Functionality
using Test-bench.
• Synthesize the design LAB 1,2 5
targeting suitable library and
by setting area and timing
constraints.
20.
• Tabulate the Area, Power
and Delay for the
Synthesized netlist, Identify
Critical path.
Design and characterize 6T LAB 1,2 5
binary SRAM cell and
21. measure the following:
• Read Time, Write Time,
SNM, Power.
• Draw Layout of 6T LAB 1 5
SRAM, use optimum layout
methods. Verify for DRC &
LVS, extract parasitic and
22. perform post layout
simulations, compare the
results with pre-layout
simulations. Record the
observations.
23. LAB TEST LAB
* GL: Guest Lecture/IV: Industrial Visits/CS: Case Studies/AA: Article based Assignment or
Survey/SDE: Skill Development Exercises /PS: Presentations/ RP: Role Play/SG:
Simulation Games/QZ: Quiz/V: Videos/PSS: Problem Solving Skills/PC: Practicals
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Bloom’s Taxonomy Level
L1-Remembering L2-Understanding L3-Applying L4-Analysing L5-Evaluating
Course Articulation Matrix
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1
CO2
CO3
CO4
CO5
Curricula Gap Analysis
Date- Resource % of Relevance
Sl.
Curricula Gap Action taken Month- Person with students to POs,
No
Year designation present PSOs
Signature of Faculty Signature of HOD
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