SYNOPSIS
Design and Implementation of RISC-V RV32I Processor
I. Introduction
RISC-V is an open standard instruction set architecture (ISA) based on reduced
instruction set computer (RISC) design principles. It defines how software communicates
with a processor’s hardware, allowing anyone to design compatible CPUs without
licensing fees. Its openness and modularity have made it a major force in modern
processor research and development.
Type: Open RISC instruction set architecture
Introduced: 2010 (University of California)
Governance: RISC-V International
Licensing: Royalty-free, open standard
Applications: Embedded systems, IoT, AI accelerators, and high-performance computing
RISC-V defines a minimal base integer instruction set (RV32I, RV64I, or RV128I),
which can be extended with optional modules.
RISC-V is an open-source instruction set architecture based on reduced instruction set
computing (RISC) principles. It provides a simple, modular, and flexible approach for
processor design, making it suitable for both academic and industrial applications.
In this project, a 32-bit RISC-V RV32I processor is designed and implemented using
Verilog HDL. The RV32I is the base integer instruction set of RISC-V, which supports
essential operations such as arithmetic, logical, memory access, and control instructions.
The processor is developed by dividing it into key components such as the Program
Counter, Instruction Memory, Register File, Arithmetic Logic Unit (ALU), and Control
Unit. These modules work together to fetch, decode, and execute instructions efficiently.
This project helps in understanding the internal working of a processor and provides
practical knowledge of digital design and hardware implementation using Verilog.
II. Problem Statement
In modern digital systems, processor design plays a crucial role in achieving efficient and
high-speed computation. However, many existing processor architectures are complex
and proprietary, which makes them difficult to study and implement for academic
purposes.
There is a need for a simple, open-source, and efficient processor architecture that can be
easily understood and implemented. RISC-V provides such a platform by offering a
modular and flexible instruction set.
Hence, this project focuses on designing and implementing a 32-bit RISC-V RV32I
processor using Verilog HDL to understand the internal working of a processor and to
develop a simplified hardware model.
III. Literature Survey
The structural foundation of this project is established by the original RISC-V Instruction
Set Manual by Asanović et al., which defines the essential RV32I base integer formats,
register conventions, and memory models required for standard compliance. To translate
this theoretical ISA into a physical datapath, the architectural principles detailed by
Patterson and Hennessy provide the critical framework. Their work outlines the core
concepts of Reduced Instruction Set Computing (RISC), guiding the logical partitioning
of the processor into efficient fetch, decode, and arithmetic execution stages.
Transitioning from architectural theory to hardware realization, recent studies have
demonstrated the feasibility of Register Transfer Level (RTL) modeling. Research by S.
Rao et al. validates the use of Verilog HDL to map the RV32I ISA into distinct structural
modules, establishing a transparent academic baseline that avoids the complexities of
proprietary designs. Furthermore, implementation strategies by A. Sharma et al. highlight
the timing and structural integration challenges encountered when bridging these sub-
modules into a cohesive executing unit. This project builds upon these foundational
hardware models by introducing strict pipeline boundaries to resolve these integration
challenges for both Intel FPGA and Cadence ASIC physical synthesis targets.
IV. Objectives
To design a 32-bit RISC-V RV32I processor using Verilog HDL
To understand the architecture and instruction set of RISC-V
To implement key modules such as Program Counter, Register File, ALU, and
Control Unit
To perform arithmetic, logical, and memory operations
To simulate and verify the design using Intel Quartus Prime and perform RTL to
GDSII flow using Cadence tools
To analyze the functionality and performance of the processor
V. Methodology
Study the architecture and instruction formats of RISC-V (RV32I), including R-type I-
type, S-type, B-type, and U-type instructions.
Design the RTL of the processor using Verilog HDL by dividing it into modules such
as Program Counter, Instruction Memory, Register File, ALU, and Control Unit.
Implement pipelining in the processor design to improve performance by enabling
parallel execution of instructions.
Develop and integrate all modules to form the complete RISC-V processor datapath
and control logic.
Simulate and verify the functionality of the design using Intel Quartus Prime (Altera)
with appropriate testbenches.
Implement and test the design on the Terasic DE10-Lite FPGA board to validate real-
time hardware functionality.
Analyze the simulation and hardware results to verify correct execution of instructions
through waveform observation.
Perform RTL to GDSII flow using Cadence tools.
Verify the physical design and analyze timing, area, and overall performance of the
processor.
Block Diagram of RISC-V RV32I Processor
Fig 2: Block Diagram of RISC-V Processor
Tools & Technologies
Verilog HDL – for designing the processor
Intel Quartus Prime – for simulation and verification
ModelSim – for waveform simulation
Cadence tools – for RTL to GDSII flow (synthesis, placement, and routing)
Terasic DE10-Lite FPGA Board – for hardware implementation and testing
Expected Results
The Program Counter (PC) should generate sequential addresses, and based on these
addresses, the instruction memory should provide correct instructions. The fetched
instructions are decoded properly, where the register file reads the required operands and
the control unit generates appropriate control signals.
The ALU should perform arithmetic and logical operations correctly according to the
instruction, and for memory-related operations, the data memory should read and write
data accurately. The results produced should be correctly passed through different stages
without errors.
The pipelining operation should enable multiple instructions to be processed
simultaneously, thereby improving the overall performance of the processor. The pipeline
registers should correctly transfer data between stages, and the pipeline is expected to
operate correctly without hazards such as data hazards, control hazards, or structural
hazards.
The simulation results and FPGA implementation should confirm the correct execution of
instructions and proper functioning of all modules.
Current Status of This Project
The fetch stage of the RISC-V processor has been successfully designed and
implemented. The Program Counter (PC) generates sequential addresses, and the
instruction memory provides the corresponding instructions correctly.
The functionality of the fetch stage has been verified through simulation, and the obtained
outputs are correct as expected.
Based on this progress, the next step is to implement the remaining stages of the
processor, including decode and execute, and to extend the design towards pipelined
operation.
Fig 2 : Fetch Stage of RISC-V RV32I Processor
Conclusion
In this project, the design and implementation of a RISC-V RV32I processor has been
initiated using Verilog HDL. The fetch stage of the processor has been successfully
designed and verified through simulation, and the obtained results are correct as expected.
This work provides a clear understanding of processor architecture, instruction flow, and
hardware design concepts. The project can be further extended by implementing the
remaining stages such as decode and execute, and by incorporating pipelining for
improved performance.
Improvements
The project can be further extended by implementing the remaining stages of the
processor, including the decode and execute stages, to achieve a complete processor
design. The design can also be enhanced by developing a fully pipelined architecture to
improve overall performance.
Further improvements can be made by incorporating hazard detection and forwarding
techniques to efficiently handle data and control hazards. The processor can be expanded
by adding support for more RISC-V instructions and advanced features.
Additionally, the design can be optimized for better speed, area, and power efficiency. A
complete RTL to GDSII implementation and detailed physical analysis can be carried out
using Cadence tools. Advanced features such as cache memory can also be integrated to
enhance performance.
References
1. Krste Asanović et al., “The RISC-V Instruction Set Manual, Volume I: User-Level
ISA,” 2016.
2. David Patterson and John L. Hennessy, “Computer Organization and Design: The
Hardware/Software Interface,” 5th ed., Morgan Kaufmann, 2014.
3. S. Rao et al., “Design of RISC-V Processor Using Verilog HDL,” IEEE
Conference, 2019.
4. A. Sharma et al., “Implementation of RV32I Processor Architecture,”
International Journal of Engineering Research, 2020.
5. John L. Hennessy and David Patterson, “Computer Architecture: A Quantitative
Approach,” 6th ed., 2017.
6. M. Patel et al., “Pipeline Hazard Detection Techniques in RISC-V,” IEEE
Conference, 2021.
7. R. Kumar et al., “FPGA Implementation of RISC-V Processor,” IEEE
Conference, 2022.
8. Intel, “Intel Quartus Prime User Guide,” and Cadence Design Systems
Documentation.