SRI RAMAKRISHNA ENGINEERING COLLEGE
VATTAMALAIPALAYAM, N.G.G.O. COLONY POST,
COIMBATORE – 641 022.
Module 3
Design for Testability
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Testability
• Testability is a concept that deals with costs associated with testing.
• Increase testability of a circuit
– Some test cost is being reduced
• Test application time
• Test generation time
• Fault simulation time
• Fault location time
• Test equipment cost
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Design for Testability (DFT)
Goal: keep test cost within a reasonable bound and ensure product quality exceeds
desired level.
Definition - Design for Testability (DFT) refers to those design techniques that
make test generation and testing cost-effective and ensure high-quality testing.
• DFT mainly addresses the difficulty of testing sequential circuits.
• DFT helps in making the internal flipflops easily controllable and observable.
• Controllable means you can initialize them into any value you want;
observable means we can see or read out their values whenever we want.
Some DFT techniques./methods
1. Ad-hoc techniques
2. Scan technique - full and partial
3. Built-in self-test (BIST) Structured techniques
4. Boundary scan
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Important factors of testability
Important factors of Testability
1. Controllability: Measure the ease of controlling a line ie., it can be set
to any value.
2. Observability: Measure the ease of observing a line at a PO (primary
output).
• In general, DFT deals with ways for improving controllability and
observability
Costs associated with DFT :
• Pins
• Area/Yield
• Performance
• Design time
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Adhoc Testing
Technique
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Adhoc Testing
• Adhoc testing refers to collections of ideas that are aimed at reducing the
combinational explosion of testing.
• Insert test points to increase controllability and observability.
CP: Control Points – Primary inputs used to enhance controllability;
OP: Observation Points – Primary outputs used to enhance observability.
• To increase the testability , it is necessary to make nodes more accessible at some
cost by physically inserting more access circuits to the original design.
The different designs are as follows:
1) Insert Test points to improve controllability and Observability
2) Partition and Multiplexer techniques
3) Disable Internal Oscillators and Clocks
4) Avoid Asynchronous Logic and Redundant Logic
5) Avoid delay dependent logic
6) Avoid clock gating
7) Initialize sequential logic
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Methods of Adhoc Testing
1) Insert Test points to improve controllability and Observability
• When a node has difficult access from primary inputs or outputs (pads of
the circuit), a very efficient method is to add internal pads.
Drawbacks:
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Modifications
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2. Partition and Multiplexer techniques
With this design technique, the number of accessible nodes can be
increased and the number of test patterns can be reduced.
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3. Disable Internal Oscillators and Clocks
• To avoid synchronization problems during testing, internal oscillators
and clocks should be disabled.
• Disable =1
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4. Avoid Asynchronous Logic and Redundant Logic
• Design and test of an asynchronous logic circuit are more difficult than for a
synchronous logic circuit. Its state transition times are difficult to predict.
• The operation of an asynchronous logic circuit is sensitive to input test patterns,
often causing race problems and hazards of having momentary signal values
opposite to the expected values.
• Logic redundancy is used to mask a static hazard condition for reliability.
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5. Avoid Delay-Dependent Logic
• Chains of inverters can be used to design in delay times and use AND operation
of their outputs along with inputs to generate pulses
• ATPG programs
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6. Avoid clock gating
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7. Initialize sequential logic
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Disadvantages of Adhoc testing
• Circuit too large for manual inspection and test generation.
• Not too many testability experts to consult.
• High fault coverage not guaranteed
• Design iterations required
• All the techniques do not represent an exhaustive list for Ad Hoc
Testing, but give a set of rules to respect as possible.
• Some of these guidelines goals are the simplification of test
vectors generation, others goals are the simplification of test
vectors application, and many others are to avoid timing problems
in the design.
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Ad-hoc Design for Testability
• Design guidelines
– Avoid asynchronous logic
– Avoid clock gating etc.,
• Insert test points
- Employ test points to enhance Controllability & Observability
- CP: Control Points – Primary inputs used to enhance controllability
- OP: Observation Points – Primary outputs used to enhance
observability
Disadvantages
• High fault coverage not guaranteed
• Design iterations required
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Scan Based Design for Testability
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Scan Design
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Scan Concept
Mode switch - 0/1 enables the mux ; say 0 for normal mode and 1 for test/scan-in mode
During normal mode, o/p of of CL is fed to FF i/p whose output is fed back to the i/p of CL.
During test mode, scan–in input is fed to the FF and scan-out is observed.
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Tests for Full Scan Circuits
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Scan Flipflop (SFF)
When TC=1, o/p of inverter is 0 and hence AND gate o/p is 0. Therefore D is fed directly
to the i/p of FF and FF is in normal mode of operation.
When TC = 0, inverter o/p is 1 and hence o/p of AND gate is SD which is fed to the FF .
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Level Sensitive Scan Design FF
(LSSD-SFF)
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Scan Design Rules
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Scan Rule Violation - Example
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Bus contention – normal mode
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Problems with Full Scan
- due to larger FFs and extra routing
Performance Degradation :
Due to increase in delay of normal data paths that includes
extra gate delay due to the mux,
extra capacitive loading delay due to scan wiring of the FF output.
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Partial Scan Approach
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Partial Scan for cycle-free structure
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Clocking Schemes for Partial scan circuits
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Partial Scan with a separate scan clock or gated
clock
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Using System clock for scan operation:
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Timing driven partial scan
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Summary of Sequential ATPG and Partial Scan
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System Level DFT Approaches
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Figure
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Thank You
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