SRI RAMAKRISHNA ENGINEERING COLLEGE

VATTAMALAIPALAYAM, N.G.G.O. COLONY POST,

COIMBATORE – 641 022.

Module 1-Introduction to Testing

Logic Simulation

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 Simulation Defined

• Definition: Simulation refers to modeling of a design, its function and

performance.
• A software simulator is a computer program; an emulator is a hardware
simulator.
• Simulation is used for design verification:
• Validate assumptions
• Verify logic
• Verify performance (timing)
• Types of simulation:
• Logic or switch level
• Timing
• Circuit
• Fault Source: Vishwani slides

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 Simulation for Verification

Specification

Synthesis

Response Design Design

analysis changes (netlist)

Computed True-value
Input stimuli
responses simulation

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 Modeling for Simulation

• Modules, blocks or components described by

• Input/output (I/O) function
• Delays associated with I/O signals
• Examples: binary adder, Boolean gates, FET, resistors and
capacitors
• Interconnects represent
• ideal signal carriers, or
• ideal electrical conductors
• Netlist: a format (or language) that describes a design as an
interconnection of modules. Netlist may use hierarchy.

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 Signal States

• Two-states (0, 1) can be used for purely combinational logic with

zero-delay.
• Three-states (0, 1, X) are essential for timing hazards and for sequential
logic initialization.
• Four-states (0, 1, X, Z) are essential for MOS devices. See example
below.
• Analog signals are used for exact timing of digital logic and for analog
circuits.
Note: X= unknown state
Z= high impedance state

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 Modeling Levels

Modeling Circuit Signal Timing Application

Level description values

Function, Programming 0, 1 Clock Architectural and

behavior, RTL language-like HDL boundary functional
verification
Logic Connectivity of 0, 1, X Zero-delay Logic verification
Boolean gates, and Z unit-delay, and test
flip-flops and multiple- delay
transistors
Switch Transistor size 0, 1 Zero-delay Logic
and connectivity, and X verification
node capacitances
Timing Transistor technology Analog Fine-grain Timing verification
data, connectivity, voltage timing
node capacitances
Circuit Tech. Data, active/ Analog Continuous Digital timing
passive component voltage, time and analog
connectivity current Circuit verification

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 Kinds of Logic Level Simulation

• Compiled-code simulation
• Applicable to zero-delay combinational logic
• Also used for cycle-accurate synchronous sequential circuits for logic
verification
• Efficient for highly active circuits, but inefficient for low-activity
circuits
• High-level (e.g., C language) models can be used
• Event-driven simulation
• Only gates or modules with input events are evaluated (event means a
signal change)
• Delays can be accurately simulated for timing verification
• Efficient for low-activity circuits
• Can be extended for fault simulation

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 Logic States for Simulation

• Combinational and synchronous circuits with a known initial state

– Two logic states (0, 1)
•Good to compute logic behavior
•Not enough for detecting hazards

• Sequential circuits with an unknown initial state

– Three states (0, 1 & u) -ie.,(3-valued logic)
•u (unknown state) represents
– Initial state of flip-flops & RAMs
– Interpreted as either 0 or 1

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 Truth Table for 3-valued Logic

outputs
AND 0 1 u
0 0 0 0
inputs
1 0 1 u
u 0 u u

outputs
OR 0 1 u
0 0 1 u
inputs

1 1 1 1
u u 1 u

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 Information Loss of 3-valued Logic

Source: T. Kim Cheng slides

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 Compiled code Algorithm

• Step 1: Levelize combinational logic and encode in a compilable

programming language
• Step 2: Initialize internal state variables (flip-flops)
• Step 3: For each input vector
– Set primary input variables
– Repeat (until steady-state or max. iterations)
• Execute compiled code
– Report or save computed variables

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 Compiled code simulation - example

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 Contd.,

•Elements are simulated in ascending order of logic level

•Time required to simulate a vector = t*N
• t : time required to simulate an element & N : number of
elements

Problems with compiled simulators

•0-delay model : timing cannot be properly modeled
•No hazard or signal propagation is predicted
•Simulation time = t*N could be slow

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 Event Driven Simulation

• For each new input vector, the ratio of lines which change values to the
total number of lines in the circuit is called the activity A.
–Typically A = 2 to10 %
• An event is a change in value of a signal line.
• The output of a gate i will only change value when one or more of its
inputs change value.
–Element i need only be simulated when an event occurs at one of its
inputs
• When an event does occur, then every element to which this line fans out
to, is called potentially active.
• Simulating these potentially active lines alone can result in significant
savings in computation time.

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 Contd.,

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 Algorithm – simplified version

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 Data Structure

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 Delay Models

Zero delay: Output changes instantly in response to an input

Unit delay: All gates have one unit delay
Transport delay:
–transition independent
–transition dependent : rise & fall delays are specified separately
Ambiguous delay or Minmax delay
Inertial delay: All circuits require energy to switch states. The minimum duration
for which an input change should persist in order for the device to switch states is
called inertial delay.
• Input inertial delay dI
– An input pulse whose duration is less than dI is filtered (or suppressed) by
the gate.
• Output inertial delay dO
– The gate output cannot generate a pulse whose duration is less than dO

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 Example

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 Event -driven Simulation with Delay

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 Time Flow Mechanism and Scheduling

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 Time Wheel

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 Example for event driven with scheduling

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 Thank You

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