Module 2: Digital Design and Hardware

Implementation of Cryptographic Primitives

SECTION A – Very Short Answer Questions
(2 Marks)
CO Mapping: CO2 (PCC-CS404.2)
Module: 2
Textbook: Hardware Security: Design, Threats and Safeguards – Debdeep Mukhopadhyay &
Rajat Subhra Chakraborty
Relevant Chapters: Chapter 3 (Modern Hardware Design Practices), Chapter 4 (Hardware
Design of AES), Chapter 5 (Efficient Design of Finite Field Arithmetic on FPGAs), Chapter 6
(ECC Implementation on FPGAs)

Q.N Question Mar Bloom Difficu CO Reference Book Expected

o. ks Level lty Mappi Topic Chapt Keywords
ng er
1 What is an 2 Remem Easy CO2 Introductio Ch.3.1 Reconfigurab
FPGA? ber n to FPGA le hardware,
programmabl
e logic
2 Expand 2 Remem Easy CO2 FPGA Ch.3.1 Field
FPGA. ber Basics Programmabl
e Gate Array
3 State one 2 Underst Easy CO2 FPGA Ch.3.1 Reconfigurab
advantage of and Architectur ility, lower
FPGA-based e development
implementati cost
ons over
ASICs.
4 What is a 2 Remem Easy CO2 FPGA Ch.3.1 Logic block,
Configurable ber Architectur .1 LUT
Logic Block e
(CLB) in an
FPGA?
5 What is the 2 Underst Easy CO2 FPGA Ch.3.1 Logic
function of a and Architectur .1 implementati
Look-Up e on,
Table (LUT) combinationa
in an FPGA? l logic
6 Define 2 Remem Easy CO2 FPGA Ch.3.1 Design,
FPGA ber Design .2 synthesis,
 design flow. Flow implementati
on
7 What is 2 Remem Easy CO2 FPGA Ch.3.1 HDL to gate-
synthesis in ber Design .2 level
FPGA Flow conversion
design?
8 What is 2 Underst Moder CO2 FPGA Ch.3.1 Placement,
meant by and ate Design .2 routing
place-and- Flow resources
route in
FPGA
implementati
on?
9 What is 2 Remem Easy CO2 VHDL/ Ch.3 Hardware
Hardware ber Verilog modeling
Description Basics
Language
(HDL)?
10 Expand 2 Remem Easy CO2 VHDL Ch.3 VHSIC
VHDL. ber Basics Hardware
Description
Language
11 Expand 2 Remem Easy CO2 Verilog Ch.3 Hardware
Verilog ber Basics Description
HDL. Language
12 Mention one 2 Underst Moder CO2 HDL Ch.3 Syntax,
difference and ate Compariso language
between n style
VHDL and
Verilog.
13 What is 2 Underst Moder CO2 VHDL Ch.3 Parallel
meant by and ate Basics hardware
concurrent execution
execution in
VHDL?
14 Define a 2 Remem Easy CO2 Verilog Ch.3 Design unit,
module in ber Basics module
Verilog. declaration
15 Why is 2 Underst Easy CO2 Modular Ch.5 Encryption,
modular and Arithmetic finite field
arithmetic Hardware operations
important in
cryptographi
c hardware?
16 What is 2 Remem Easy CO2 Modular Ch.5 Multiplicatio
modular ber Arithmetic n under
 multiplicatio modulus
n?
17 What is the 2 Underst Easy CO2 Cryptograp Ch.3, Speed,
primary and hic Ch.4 security,
objective of Hardware efficiency
implementin
g
cryptographi
c algorithms
on FPGAs?
18 Name the 2 Remem Easy CO2 AES Ch.4 SubBytes,
four major ber Hardware ShiftRows,
AES round Design MixColumns
transformati ,
ons. AddRoundK
ey
19 What is an 2 Remem Easy CO2 AES Ch.4.3 Substitution
AES S-Box? ber Hardware table
Design
20 What is 2 Underst Moder CO2 AES Ch.4.5 Parallelism,
pipelining in and ate Architectur throughput
FPGA-based e
cryptographi
c
implementati
ons?
21 What type of 2 Remem Easy CO2 DES Ch.4 Feistel
network is ber Implement Network
used in DES ation
architecture?
22 What is 2 Underst Moder CO2 Design Ch.3, Data rate,
meant by and ate Considerati Ch.4 performance
throughput ons
in hardware
cryptographi
c design?
23 What is 2 Remem Moder CO2 Design for Ch.10 Side-channel
power ber ate Security protection
analysis
resistance in
secure
hardware
design?
24 Mention one 2 Underst Moder CO2 Secure Ch.10 Masking,
design and ate Hardware balancing
technique Design
 used to
improve
resistance
against
power
analysis
attacks.
25 Why is 2 Analyze Moder CO2 Design for Ch.3, Information
security ate Security Ch.10 leakage, side-
considered channel
during attacks
hardware
design of
cryptographi
c systems?

Module 2: Digital Design and Hardware

Implementation of Cryptographic Primitives
SECTION B – Short Answer Questions (5
Marks)
CO Mapping: CO2 (PCC-CS404.2)
Module: 2
Textbook: Hardware Security: Design, Threats and Safeguards – Debdeep Mukhopadhyay &
Rajat Subhra Chakraborty
Relevant Chapters: Chapter 3 (Modern Hardware Design Practices), Chapter 4 (Hardware
Design of AES), Chapter 5 (Finite Field Arithmetic on FPGAs), Chapter 6 (ECC/FPGA
Architectures)

Q.N Question Mar Bloom Difficu CO Reference Book Expected

o. ks Level lty Mappi Topic Chapt Keywords
ng er
1 Explain the 5 Underst Easy CO2 FPGA Ch.3.1 CLB, LUT,
basic and Architectur .1 routing
architecture e resources,
of an FPGA I/O blocks
and discuss
the function
of its major
components.
2 Describe the 5 Underst Easy CO2 FPGA Ch.3.1 HDL,
FPGA and Design .2 synthesis,
design flow Flow mapping,
from place-and-
hardware route
description
to hardware
implementat
ion.
3 Discuss the 5 Analyze Easy CO2 FPGA Ch.3.1 Reconfigurab
advantages Applicatio ility,
of using ns parallelism,
FPGAs for prototyping
cryptographi
c hardware
implementat
ions.
4 Explain the 5 Underst Moder CO2 FPGA Ch.3.1 Logic
role of and ate Logic .1 realization,
Look-Up Blocks combinationa
Tables l circuits
(LUTs) in
FPGA-based
digital
design.
5 Explain the 5 Underst Easy CO2 HDL Ch.3 Hardware
importance and Basics abstraction,
of hardware design
modeling description
languages in
digital
system
design.
6 Discuss the 5 Underst Easy CO2 VHDL Ch.3 Entity,
key features and Basics architecture,
of VHDL concurrent
and its role statements
in FPGA
design.
7 Explain the 5 Underst Easy CO2 Verilog Ch.3 Module,
structure of and Basics input, output,
a basic behavioral
Verilog description
module with
suitable
examples.
8 Compare 5 Analyze Moder CO2 HDL Ch.3 Strong
VHDL and ate Compariso typing,
Verilog with n syntax
respect to simplicity
syntax,
design style,
and
industrial
usage.
9 Explain why 5 Underst Moder CO2 Modular Ch.5 Finite field
modular and ate Arithmetic operations,
arithmetic is Hardware encryption
widely used
in
cryptographi
c hardware
implementat
ions.
10 Discuss the 5 Analyze Moder CO2 Modular Ch.5 Area, speed,
challenges ate Arithmetic resource
involved in Hardware utilization
implementin
g modular
arithmetic
operations
on FPGA
platforms.
11 Explain the 5 Underst Moder CO2 AES Ch.4 Throughput,
architectural and ate Hardware area, latency
consideratio Design
ns involved
in
implementin
g AES on
FPGA
hardware.
12 Describe the 5 Underst Moder CO2 AES S- Ch.4.3 Substitution,
role of the and ate Box non-linearity
AES S-Box Design
in hardware
implementat
ion.
13 Discuss the 5 Apply Moder CO2 AES Ch.4.5 Throughput,
advantages ate Architectur parallel
of pipelining e processing
in FPGA-
 based AES
implementat
ions.
14 Explain the 5 Underst Moder CO2 DES Ch.4 Feistel
basic and ate Hardware rounds,
hardware Design encryption
architecture
of DES and
its Feistel
structure.
15 Compare the 5 Analyze Moder CO2 AES vs Ch.4 Area,
hardware ate DES complexity,
implementat Hardware security
ion
requirements
of AES and
DES.
16 Discuss the 5 Analyze Hard CO2 Design Ch.3, Optimization,
trade-offs Considerat Ch.4 resources
between ions
area, speed,
and power
consumption
in
cryptographi
c hardware
design.
17 Explain how 5 Apply Moder CO2 FPGA Ch.3 LUTs,
FPGA ate Optimizati registers,
resources on routing
can be
utilized
efficiently
for
cryptographi
c
applications.
18 Describe the 5 Underst Moder CO2 Secure Ch.10 Information
concept of and ate Hardware leakage,
side-channel Design power traces
leakage in
hardware
cryptographi
c
implementat
ions.
19 Explain the 5 Analyze Moder CO2 Power Ch.10 Security,
importance ate Analysis side-channel
of power Resistance attacks
analysis
resistance in
secure
hardware
design.
20 Discuss 5 Apply Hard CO2 Secure Ch.10 Masking,
basic design Hardware balancing,
approaches Design hiding
used to
improve
resistance
against
power
analysis
attacks.

Module 2: Digital Design and Hardware

Implementation of Cryptographic Primitives
SECTION C – Descriptive Questions (10
Marks)
CO Mapping: CO2 (PCC-CS404.2)
Module: 2
Textbook: Hardware Security: Design, Threats and Safeguards – Debdeep Mukhopadhyay &
Rajat Subhra Chakraborty
Relevant Chapters: Chapter 3 (Modern Hardware Design Practices), Chapter 4 (Hardware
Design of AES), Chapter 5 (Finite Field Arithmetic on FPGAs), Chapter 6 (FPGA
Cryptoprocessors)

Q.N Question Mar Bloom Difficu CO Reference Book Expected

o. ks Level lty Mappi Topic Chapt Keywords
ng er
1 Explain the 10 Underst Modera CO2 FPGA Ch.3.1 CLB, LUT,
architecture and te Architectur .1 switch
of an FPGA e matrix,
in detail. routing
Discuss the network, I/O
 functions of blocks
Configurable
Logic
Blocks
(CLBs),
Look-Up
Tables
(LUTs),
routing
resources,
and I/O
blocks.
2 Describe the 10 Underst Modera CO2 FPGA Ch.3.1 HDL design,
complete and te Design .2 synthesis,
FPGA Flow mapping,
design flow placement,
from routing,
hardware configuratio
description n
to bitstream
generation.
Explain the
purpose of
each stage.
3 Explain how 10 Apply Modera CO2 Mapping Ch.3.2 Datapath,
an algorithm te Algorithms controller,
can be to FSM,
mapped into Hardware architecture
hardware
architecture.
Discuss the
role of
datapath and
control path
in FPGA-
based
systems.
4 Compare 10 Analyze Modera CO2 VHDL and Ch.3 Syntax,
VHDL and te Verilog abstraction,
Verilog with concurrency,
respect to industrial
language usage
structure,
design
methodology
, simulation,
 and
synthesis.
5 Explain the 10 Analyze Modera CO2 Modular Ch.5 Modulo
significance te Arithmetic operations,
of modular Hardware efficiency,
arithmetic in resource
cryptographi utilization
c hardware.
Discuss the
challenges
involved in
implementin
g modular
operations
on FPGAs.
6 Discuss the 10 Underst Modera CO2 AES Ch.4 SubBytes,
hardware and te Hardware ShiftRows,
implementati Design MixColumn
on of AES. s,
Explain the AddRoundK
major AES ey
round
transformati
ons and their
hardware
realization.
7 Explain 10 Analyze Hard CO2 AES Ch.4.2 Pipelining,
various Optimizati , parallelism,
architectural on Ch.4.5 resource
optimization sharing
techniques
used in
FPGA-based
AES
implementati
ons.
8 Describe the 10 Apply Hard CO2 AES S- Ch.4.3 Substitution
design and Box logic,
implementati composite
on fields,
consideratio optimization
ns of the
AES S-Box
in hardware.
9 Explain the 10 Underst Modera CO2 DES Ch.4 Feistel
hardware and te Hardware structure,
 implementati Design round
on of DES function,
and discuss encryption
the role of
the Feistel
network in
its design.
10 Compare 10 Analyze Modera CO2 AES vs Ch.4 Performance
FPGA-based te DES ,
implementati Hardware complexity,
ons of AES security
and DES in
terms of
architecture,
resource
utilization,
throughput,
and security.
11 Discuss the 10 Analyze Hard CO2 Hardware Ch.3, Throughput,
trade-offs Design Ch.4 optimization
among area, Considerati , resources
speed, ons
latency, and
power
consumption
in
cryptographi
c hardware
design.
12 Explain the 10 Apply Modera CO2 FPGA Ch.4.5 Pipeline
concept of te Optimizati stages,
pipelining on latency,
and Techniques throughput
serialization
in FPGA-
based
cryptographi
c systems.
Discuss their
impact on
performance.
13 Describe the 10 Analyze Modera CO2 Secure Ch.3, Side
importance te Hardware Ch.10 channels,
of secure Design information
hardware leakage
design in
 cryptographi
c
implementati
ons. Explain
how
hardware
vulnerabilitie
s can
compromise
security.
14 Explain the 10 Analyze Hard CO2 Power Ch.10 SPA, DPA,
basics of Analysis leakage,
power Resistance countermeas
analysis ures
attacks and
discuss why
resistance to
such attacks
must be
considered
during
hardware
design.
15 Discuss 10 Evaluate Hard CO2 Secure Ch.10 Masking,
various Hardware hiding,
design Design balancing,
approaches secure
used to architecture
improve
resistance
against
power
analysis
attacks in
FPGA-based
cryptographi
c systems.

Module 2: Digital Design and Hardware

Implementation of Cryptographic Primitives
SECTION D – Analytical / Design-Oriented
Questions (15 Marks)
CO Mapping: CO2 (PCC-CS404.2)
Module: 2
Textbook: Hardware Security: Design, Threats and Safeguards – Debdeep Mukhopadhyay &
Rajat Subhra Chakraborty
Relevant Chapters: Chapter 3 (Modern Hardware Design Practices), Chapter 4 (Hardware
Design of AES), Chapter 5 (Efficient Design of Finite Field Arithmetic on FPGAs), Chapter 6
(High-Speed FPGA Cryptoprocessors)

Q.N Question Mar Bloo Difficu CO Reference Book Expected

o. ks m lty Mappi Topic Chapt Keywords
Level ng er
1 Design an 15 Create Hard CO2 Modular Ch.3, Datapath,
FPGA-based Arithmetic Ch.5 controller,
architecture Hardware modular
for operations,
implementin LUT
g a modular utilization
arithmetic
unit used in
cryptographi
c
applications.
Discuss
datapath
design,
control logic,
resource
utilization,
and
performance
consideration
s.
2 Analyze the 15 Analy Hard CO2 FPGA Ch.3.1 Synthesis,
FPGA design ze Design .2 place-and-
flow for Flow route, timing
implementin closure
ga
cryptographi
c algorithm.
Explain how
synthesis,
 mapping,
placement,
routing, and
timing
analysis
influence the
final
hardware
performance.
3 A hardware 15 Evalu Hard CO2 FPGA Ch.3.1 Reconfigurab
engineer ate Architectur ility, cost,
must choose e development
between cycle
FPGA and
ASIC
implementati
on for a
secure
cryptographi
c processor.
Compare
both
approaches
and justify
the selection
of FPGA for
rapid
cryptographi
c
prototyping.
4 Design a 15 Create Hard CO2 AES Ch.4 AES rounds,
high-level Hardware pipelining,
FPGA Design optimization
architecture
for AES
implementati
on. Explain
how
throughput,
latency,
pipelining,
and resource
utilization
affect the
design.
5 Critically 15 Evalu Hard CO2 AES Ch.4.2 Parallelism,
 analyze ate Optimizati , serialization,
various on Ch.4.5 pipelining
optimization
techniques
used in
FPGA-based
AES
implementati
ons. Discuss
their impact
on area,
speed, and
power
consumption.
6 Compare the 15 Evalu Hard CO2 AES vs Ch.4 SPN, Feistel
hardware ate DES network,
implementati Hardware performance,
on of AES security
and DES
from the
perspectives
of
architecture,
complexity,
scalability,
resource
requirements
, and
security.
Recommend
the more
suitable
algorithm for
modern
FPGA-based
systems with
justification.
7 Design a 15 Create Hard CO2 Secure Ch.10 Masking,
secure Hardware balancing,
FPGA-based Design side-channel
cryptographi resistance
c module that
incorporates
basic
protection
against
 power
analysis
attacks.
Explain the
architectural
modification
s required
and evaluate
their
effectiveness
.
8 A defense 15 Analy Hard CO2 Hardware Ch.3, Optimization,
organization ze Design Ch.4 resource
plans to Considerati management,
deploy ons efficiency
cryptographi
c hardware in
a power-
constrained
embedded
system.
Analyze the
trade-offs
among
throughput,
area, latency,
and power
consumption,
and propose
an optimized
FPGA design
strategy.
9 Develop a 15 Create Hard CO2 VHDL and Ch.3 HDL coding,
design Verilog simulation,
methodology Design verification
for
implementin
g
cryptographi
c primitives
on FPGAs
using VHDL
or Verilog.
Discuss
coding style,
modular
 design,
testing,
verification,
and synthesis
consideration
s.
10 Evaluate the 15 Evalu Hard CO2 Design for Ch.3, Side
importance ate Security Ch.10 channels,
of secure leakage,
hardware secure
design in architecture
modern
cryptographi
c systems.
Discuss how
improper
FPGA
implementati
on can lead
to side-
channel
vulnerabilitie
s and
propose
suitable
countermeas
ures.