Chapter 11 Differential and Multistage Amplifiers 825

CHECKPOINT
After studying this chapter, the reader should have the ability to:
✓ Describe the mechanism by which a differential-mode signal and common-
mode signal are produced in a BJT diff-amp.
✓ Describe the dc transfer characteristics of a BJT diff-amp.
✓ Define common-mode rejection ratio.
✓ Describe the mechanism by which a differential-mode signal and common-
mode signal are produced in a MOSFET diff-amp.
✓ Describe the dc transfer characteristics of a MOSFET diff-amp.
✓ Design a MOSFET diff-amp with an active load to yield a specified differential-
mode voltage gain.
✓ Analyze a simplified BJT operational amplifier circuit.
✓ Design a simplified MOSFET operational amplifier circuit.

REVIEW QUESTIONS
1. Define differential-mode and common-mode input voltages.
2. Sketch the dc transfer characteristics of a BJT differential amplifier.
3. From the dc transfer characteristics, qualitatively define the linear region of
operation for a differential amplifier.
4. What is meant by matched transistors and why are matched transistors important
in the design of diff-amps?
5. Explain how a differential-mode output signal is generated.
6. Explain how a common-mode output signal is generated.
7. Define the common-mode rejection ratio, CMRR. What is the ideal value?
8. What design criteria will yield a large value of CMRR in an emitter-coupled pair?
9. Sketch the differential-mode and common-mode half-circuit models for an
emitter-coupled diff-amp.
10. Define differential-mode and common-mode input resistances.
11. Sketch the dc transfer characteristics of a MOSFET differential amplifier.
12. Sketch and describe the advantages of a MOSFET cascode current source used
with a MOSFET differential amplifier.
13. Sketch a simple MOSFET differential amplifier with an active load.
14. Explain the advantages of an active load.
15. Describe the loading effects of connecting a second stage to the output of a BJT
diff-amp.
16. Explain the frequency response of the differential-mode voltage gain.
17. Sketch a BJT Darlington pair circuit and explain the advantages.
18. Describe the three stages of a simple BJT operational amplifier.

PROBLEMS
Section 11.2 Basic BJT Differential Pair
11.1 (a) A differential-amplifier has a differential-mode gain of Ad = 250 and a
common-mode rejection ratio of CMRRdB = ∞. A differential-mode input
signal of vd = 1.5 sin ω t mV is applied along with a common-mode input
signal of vcm = 3 sin ω t V. Assuming the common-mode gain is positive,
determine the output voltage. (b) Repeat part (a) if the common-mode
826 Part 2 Analog Electronics

rejection ratio is CMRRdB = 80 dB. (c) Repeat part (a) if the common-
mode rejection ratio is CMRRdB = 50 dB.
11.2 Consider the circuit shown in Figure P11.2. Assume gm = 1.0 mA/V. As-
sume the input signal voltages are v1 = 0.7 + 0.1 sin ω t V and v2 =
0.7 − 0.1 sin ω t V. (a) Determine the signal voltages (i) vo1 , (ii) vo2 , and
(iii) vo1 − vo2 . (b) Using the results of part (a), determine the small-signal
voltage gains (i) Ad1 = vo1 / (v1 − v2 ),(ii) Ad2 = vo2 / (v1 − v2 ), and
(iii) Ad3 = (vo1 − vo2 ) / (v1 − v2 ).

V+ = 5 V

R= R=
5 kΩ 5 kΩ

vO1 vO2

gmv2

v1 +– gmv1 +
–
v2

Figure P11.2

11.3 Consider the differential amplifier shown in Figure P11.3 with transistor
parameters β = 150, VB E (on) = 0.7 V, and V A = ∞. (a) Design the circuit
such that the Q-point values are IC1 = IC2 = 100 µA and v O1 =
v O2 = 1.2 V for v1 = v2 = 0. (b) Draw the dc load line and plot the Q-point
for transistor Q 2 . (c) What are the maximum and minimum values of the
common-mode input voltage?

+3 V +5 V

R1 = RC = RC =
I1 IC4
IC1 RC RC IC2 8.5 kΩ 2 kΩ 2 kΩ

+
Q4 VCE4 Q5
vO1 vO2 –
Q1 Q2
Q3 IC2

+ v1 v2 + +
– – Q1 Q2 VCE2
IE RE
–

–3 V –5 V

Figure P11.3 Figure P11.4

11.4 The differential amplifier in Figure P11.4 is biased with a three-transistor cur-
rent source. The transistor parameters are: β = 100, VB E (on) = 0.7 V, and
 Chapter 11 Differential and Multistage Amplifiers 827

VA = ∞. (a) Determine I1, IC2, IC4, VC E2 , and VC E4 . (b) Determine a new

value of R1 such that VC E4 = 2.5 V. What are the values of IC4, IC2, I1, and R1?
*D11.5 For the transistors in the circuit in Figure P11.5, the parameters are β = 100
and VB E (on) = 0.7 V. The Early voltage is V A = ∞ for Q1 and Q2, and is
VA = 50 V for Q3 and Q4. (a) Design resistor values such that I3 = 400 µA
and VC E1 = VC E2 = 10 V. (b) Find Ad, Acm, and CMRRdB for a one-sided
output at vO2. (c) Determine the differential- and common-mode input
resistances.

V + = 15 V

RC RC I1 R1

IC1 IC2 vO2

10 kΩ 10 kΩ
Q1 Q2

+ v1 + v2
– –
I3

Q3 Q4

V – = –15 V

Figure P11.5

11.6 The diff-amp in Figure 11.3 of the text has parameters V + = +5 V,

V − = −5 V, RC = 8 k , and I Q = 0.5 mA. The transistor parameters are
β = 120, VB E (on) = 0.7 V, and V A = ∞. (a) Using Figure 11.3(a), deter-
mine the maximum common-mode input voltage vcm that can be applied
such that the transistors Q1 and Q2 remain biased in the active region.
(b) Using Figure 11.3(b), determine the change in vC2 from its dc value if
vd = 18 mV. (c) Repeat part (b) if vd = 10 mV.
D11.7 The diff-amp configuration shown in Figure P11.7 is biased at ±3 V. The
maximum power dissipation in the entire circuit is to be no more than
1.2 mW when v1 = v2 = 0. The available transistors have parameters:
β = 120, VB E (on) = 0.7 V, and V A = ∞. Design the circuit to produce
the maximum possible differential-mode voltage gain, but such that the
common-mode input voltage can be within the range −1 ≤ vC M ≤ 1 V and
the transistors are still biased in the forward-active region. What is the value
of Ad? What are the current and resistor values?
11.8 Consider the circuit in Figure P11.8, with transistor parameters: β = 100,
VB E (on) = 0.7 V, and V A = ∞. (a) For v1 = v2 = 0, find IC1, IC2, IE, VCE1,
and VCE2. (b) Determine the maximum and minimum values of the
common-mode input voltage. (c) Calculate Ad for a one-sided output at the
collector of Q2.
828 Part 2 Analog Electronics

V+ +10 V

+5 V

I1 R1 IC1 RC IC2 RC RC = 50 kΩ RC = 50 kΩ
RC = RC =
IC1 100 kΩ 100 kΩ IC2

v1 Q1 Q2 vO1 vO2
v2
RB = 0.5 kΩ RB = 0.5 kΩ
v1 Q1 Q2 v2 Q1 Q2
IC4
2 kΩ 2 kΩ + v v2 +–
– 1
Q3 Q4
IE RE = 85 kΩ IE RE

V– –5 V –10 V

Figure P11.7 Figure P11.8 Figure P11.9

*11.9 The transistor parameters for the circuit in Figure P11.9 are: β = 100,
VB E (on) = 0.7 V, and V A = ∞. (a) Determine RE such that I E = 150 µA.
(b) Find Ad, Acm, and CMRRdB for a one-sided output at vO2. (c) Determine
the differential- and common-mode input resistances.
11.10 The bias voltages for the diff-amp shown in Figure P11.10 are V + = 3 V
and V − = −3 V. The transistor current gains are β = 80, the nominal value
of VB E (on) is 0.6 V, and V A = ∞. (a) Design the circuit such that the qui-
escent collector currents are 50 µA and vC1 = vC2 = −1.5 V for
v1 = v2 = 0. (b) Determine vC1 and vC2 when (i) v1 = v2 = 1 V and
(ii) v1 = 0.994 V, v2 = 1.006 V.

V+ V+

RE IQ

v1 Q1 Q2 v2 v1 Q1 Q2 v2

vC1 vC2 vC1 vC2

RC RC RC RC

V– V–

Figure P11.10 Figure P11.11

11.11 Consider the circuit shown in Figure P11.11. The circuit and transistor
parameters are V + = +3 V, V − = −3 V, RC = 360 k , I Q = 12 µA,
β = 60, VE B (on) = 0.6 V, and V A = ∞. The output resistance of the
current source is Ro = 4 M . (a) Determine the Q-points of the transistors
for v1 = v2 = 0. (b) Determine the differential- and common-mode voltage
gains for (i) v O = vC1 − vC2 and (ii) v O = vC2 .